CN110399318A - A kind of SPI system hardware architecture and its operational process - Google Patents
A kind of SPI system hardware architecture and its operational process Download PDFInfo
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- CN110399318A CN110399318A CN201910669059.2A CN201910669059A CN110399318A CN 110399318 A CN110399318 A CN 110399318A CN 201910669059 A CN201910669059 A CN 201910669059A CN 110399318 A CN110399318 A CN 110399318A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
- G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Stored Programmes (AREA)
Abstract
The invention discloses a kind of SPI system hardware architecture and its operational processes, including startup power supply, initialization module, data read module, information capturing module, information display module, instruct read module, instruction operation module B, module is keyed in instruction, instruct setting module A, instruct setting module B and instruction setting module C, startup power supply connection initialization module, initialization module connects data read module, data read module link information display module, information display module link order runs module B, beneficial effects of the present invention: the more traditional operational process of operational process of the present invention is more systematic comprehensively, more command informations can be performed, suitable for a variety of equipment based on SPI hardware configuration, it is more convenient and practical.
Description
Technical field:
The invention belongs to mechanical equipment technical field, in particular to a kind of SPI system hardware architecture and its operational process.
Background technique:
Traditional system hardware architecture operational process is single, it is difficult to execute more command informations, be only applicable to few kind of needs
The running equipment of system hardware architecture, while inconvenient, practicability, wide usage are low.
Summary of the invention:
The object of the invention is that providing a kind of SPI system hardware architecture and its operation stream to solve the above-mentioned problems
Journey.
To solve the above-mentioned problems, the present invention provides a kind of technical solutions:
A kind of SPI system hardware architecture, including startup power supply, initialization module, data read module, information capture mould
Block, information display module, instruction read module, instruction operation module B, instruction key entry module, instruction setting module A, instruction are set
Cover half block B and instruction setting module C, the startup power supply connection initialization module, the initialization module connection data are read
Modulus block, the data read module link information display module, the information display module link order run module B, institute
It states instruction operation module B and is separately connected instruction setting module A, instruction setting module B and instruction setting module C, described instruction
It runs between module B and instruction setting module A, instruction is run between module B and instruction setting module B and instruction operation module
Module connection is keyed in by instruction between B and instruction setting module C.
It is connected to instruction setting module A, instruction setting module B preferably, described instruction keys in module side and refers to
Setting module C is enabled, described instruction keys in the module other end and is connected to data read module.
Preferably, being equipped with information capturing module, the information between the data read module and information display module
Capture module one end link information display module, the information capturing module other end link order read module, the information
Instruction read module, the operation of described instruction read module one end link order are equipped between display module and instruction operation module B
Module B, the described instruction read module other end key in module by link order.
Preferably, the described instruction setting module A other end is connect by execution module A with data read module, it is described
The instruction setting module B other end is connect by execution module B with data read module, and the described instruction setting module C other end is logical
Execution module C is crossed to connect with data read module.
A kind of operational process of SPI hardware configuration, comprising the following steps:
A. main equipment and the power supply from equipment are connected；
B. main equipment initializes spi messaging parameter, initializes spi messaging parameter from equipment；
C. main equipment SPI chip selection signal, by from the temporary instruction of device register, data and address, and set delay with
And judgement processing；
D. it is handled from judgement after equipment reading director data, and carries out data command in register and execute；
E. information of the main equipment by processing information is judged and from equipment after register carries out data command execution is collected；
F. command information is inputted.
Preferably, main equipment in the step A and be same power supply from the power supply of equipment, is also turned on.As
It is preferred that the main equipment in the step B initializes spi messaging parameter, carries out, need simultaneously from equipment initialization spi messaging parameter
Main equipment and spi messaging parameter from equipment can just enter downstream after initializing.
Preferably, the main equipment in step A is at most equipped with one, be equipped with from equipment it is several, and each from equipment and master
Equipment shares same power supply.
Beneficial effects of the present invention:
The present invention connects main equipment and the power supply from equipment first, and then main equipment initializes spi messaging parameter, from setting
Standby initialization spi messaging parameter, then main equipment SPI chip selection signal, by from the temporary instruction of device register, data and ground
Location, and delay and judgement processing are set, then handle judgement after reading director data from equipment, and counted in register
According to instructing and executing, main equipment is finally collected by judgement and handles information and from equipment after register carries out data command execution
Information, according to information input command information, the more traditional operational process of operational process it is more systematic comprehensively, can be performed more finger
Information is enabled, it is more convenient and practical suitable for a variety of equipment based on SPI hardware configuration.
Detailed description of the invention:
Detailed description will be given by the following detailed implementation and drawings by the present invention for ease of explanation,.
Fig. 1 is the structural diagram of the present invention；
Fig. 2 is operational flow diagram of the invention.
In figure: 1, startup power supply；2, initialization module；3, data read module；4, information capturing module；5, information is shown
Module；6, read module is instructed；7, instruction operation module B；8, module is keyed in instruction；9, setting module A is instructed；10, mould is executed
Block A；11, execution module B；12, execution module C；13, setting module C is instructed；14, setting module B is instructed.
Specific embodiment:
As shown in Figs. 1-2, present embodiment uses a kind of following technical scheme: SPI system hardware architecture, including opens
Dynamic power supply 1, initialization module 2, data read module 3, information capturing module 4, information display module 5, instruction read module 6,
Instruction operation module B7, instruction key in module 8, instruction setting module A9, instruction setting module B14 and instruction setting module
C13,1 connection initialization module 2 of startup power supply, the initialization module 2 connect data read module 3, and the data are read
3 link information display module 5 of modulus block, 5 link order of information display module run module B7, and described instruction runs module
B7 is separately connected instruction setting module A9, instruction setting module B14 and instruction setting module C13, described instruction run module
Between B7 and instruction setting module A9, instruction is run between module B7 and instruction setting module B14 and instruction operation module B7
Module 8 is keyed in by instruction between instruction setting module C13 to connect.
Wherein, described instruction keys in 8 side of module and is connected to instruction setting module A9, instruction setting module B14 and refers to
Setting module C13 is enabled, described instruction keys in 8 other end of module and is connected to data read module 3, convenient to run module B7 to instruction
In data carry out judgement processing.
Wherein, information capturing module 4 is equipped between the data read module 3 and information display module 5, the information is caught
Catch 4 one end link information display module 5 of module, 4 other end link order read module 6 of information capturing module, the letter
It ceases and is equipped with instruction read module 6 between display module 5 and instruction operation module B7, the connection of 6 one end of described instruction read module refers to
Operation module B7 is enabled, 6 other end of described instruction read module keys in module 8, the convenient letter to each module by 15 link orders
Breath carries out judgement processing.
Wherein, the described instruction setting module A9 other end is connect by execution module A10 with data read module 3, described
The instruction setting module B14 other end is connect by execution module B11 with data read module 3, and described instruction setting module C13 is another
One end is connect by execution module C12 with data read module 3, convenient for operating to each instruction execution.
A kind of operational process of SPI hardware configuration, comprising the following steps:
A. main equipment and the power supply from equipment are connected；
B. main equipment initializes spi messaging parameter, initializes spi messaging parameter from equipment；
C. main equipment SPI chip selection signal, by from the temporary instruction of device register, data and address, and set delay with
And judgement processing；
D. it is handled from judgement after equipment reading director data, and carries out data command in register and execute；
E. information of the main equipment by processing information is judged and from equipment after register carries out data command execution is collected；
F. command information is inputted.
Wherein, the main equipment in the step A and from the power supply of equipment be same power supply, be also turned on, allow to
It operates simultaneously.
Wherein, the main equipment in the step B initializes spi messaging parameter, simultaneously from equipment initialization spi messaging parameter
It carries out, downstream can be just entered after needing main equipment and the spi messaging parameter from equipment to initialize, there is whole flow process
Sequence not disorder.
Wherein, the main equipment in step A is at most equipped with one, be equipped with from equipment it is several, and each from equipment and main equipment
Same power supply is shared, overall structure is optimized.
It is specific: a kind of SPI system hardware architecture and its operational process, first connection main equipment and the electricity from equipment
Source, then main equipment initializes spi messaging parameter, initializes spi messaging parameter from equipment, then main equipment SPI chip selection signal,
By keeping in instruction, data and address from device register, and delay and judgement processing are set, then makes to refer to from equipment reading
Enable judgement after data handle, and carry out data command in register and execute, finally collect main equipment will judgement processing information with
And the information from equipment after register carries out data command execution, according to information input command information, operational process is more traditional
Operational process it is more systematic comprehensively, more command informations can be performed, suitable for a variety of equipment based on SPI hardware configuration, more
Add convenient and practical, wherein instruction keys in 8 side of module and is connected to instruction setting module A9, instruction setting module B14 and instruction
Setting module C13, instruction key in 8 other end of module and are connected to data read module 3, the convenient number in instruction operation module B7
According to carrying out judgement processing；Information capturing module 4, information capturing module are equipped between data read module 3 and information display module 5
4 one end link information display modules 5,4 other end link order read module 6 of information capturing module and refer to information display module 5
It enables and is equipped with instruction read module 6 between operation module B7, instruction 6 one end link order of read module runs module B7, and instruction is read
6 other end of modulus block keys in module 8 by 15 link orders, convenient to carry out judgement processing to the information of each module；Instruction setting
9 other end of modules A is connect by execution module A10 with data read module 3, and the instruction setting module B14 other end passes through execution
Module B11 is connect with data read module 3, and the instruction setting module C13 other end passes through execution module C12 and data read module
3 connections, convenient for being operated to each instruction execution.
The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention, the technology of the industry
Personnel are it should be appreciated that the present invention is not limited to the above embodiments, and the above embodiments and description only describe this
The principle of invention, without departing from the spirit and scope of the present invention, various changes and improvements may be made to the invention, these changes
Change and improvement all fall within the protetion scope of the claimed invention, the claimed scope of the invention by appended claims and its
Equivalent thereof.
Claims (8)
1. a kind of SPI system hardware architecture, including startup power supply (1), initialization module (2), data read module (3), information
Capture module (4), information display module (5), instruction read module (6), instruction operation module B (7), instruction key in module (8),
Instruct setting module A (9), instruction setting module B (14) and instruction setting module C (13), it is characterised in that: the starting electricity
Source (1) connection initialization module (2), the initialization module (2) connect data read module (3), the data read module
(3) link information display module (5), information display module (5) link order run module B (7), and described instruction runs mould
Block B (7) is separately connected instruction setting module A (9), instruction setting module B (14) and instruction setting module C (13), the finger
It enables between operation module B (7) and instruction setting module A (9), between instruction operation module B (7) and instruction setting module B (14)
And module (8) connection is keyed in by instruction between instruction operation module B (7) and instruction setting module C (13).
2. a kind of SPI system hardware architecture according to claim 1, it is characterised in that: described instruction keys in module (8) one
Side is connected to instruction setting module A (9), instruction setting module B (14) and instruction setting module C (13), and described instruction is keyed in
Module (8) other end is connected to data read module (3).
3. a kind of SPI system hardware architecture according to claim 1, it is characterised in that: the data read module (3) and
Information capturing module (4) are equipped between information display module (5), information capturing module (4) one end link information shows mould
Block (5), information capturing module (4) other end link order read module (6), the information display module (5) and instruction
It runs and is equipped with instruction read module (6) between module B (7), described instruction read module (6) one end link order runs module B
(7), described instruction read module (6) other end keys in module (8) by (15) link order.
4. a kind of SPI system hardware architecture according to claim 3, it is characterised in that: described instruction setting module A (9)
The other end is connect by execution module A (10) with data read module (3), and described instruction setting module B (14) other end passes through
Execution module B (11) is connect with data read module (3), and described instruction setting module C (13) other end passes through execution module C
(12) it is connect with data read module (3).
5. a kind of operational process of SPI system hardware architecture, which comprises the following steps:
A. main equipment and the power supply from equipment are connected；
B. main equipment initializes spi messaging parameter, initializes spi messaging parameter from equipment；
C. main equipment SPI chip selection signal by keeping in instruction, data and address from device register, and sets delay and sentences
Disconnected processing；
D. it is handled from judgement after equipment reading director data, and carries out data command in register and execute；
E. information of the main equipment by processing information is judged and from equipment after register carries out data command execution is collected；
F. command information is inputted.
6. a kind of SPI system hardware architecture according to claim 5 and its operational process, it is characterised in that: the step A
In main equipment and from the power supply of equipment be same power supply, be also turned on.
7. a kind of SPI system hardware architecture according to claim 5 and its operational process, it is characterised in that: the step B
In main equipment initialize spi messaging parameter, carried out simultaneously from equipment initialization spi messaging parameter, need main equipment and from equipment
Spi messaging parameter initialize after can just enter downstream.
8. a kind of SPI system hardware architecture according to claim 5 and its operational process, it is characterised in that: in step A
Main equipment is at most equipped with one, is equipped with from equipment several, and each shares same power supply from equipment and main equipment.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910669059.2A CN110399318A (en) | 2019-07-23 | 2019-07-23 | A kind of SPI system hardware architecture and its operational process |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910669059.2A CN110399318A (en) | 2019-07-23 | 2019-07-23 | A kind of SPI system hardware architecture and its operational process |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114826811A (en) * | 2021-01-28 | 2022-07-29 | 南宁富桂精密工业有限公司 | Data transmission method and system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103488601A (en) * | 2012-06-12 | 2014-01-01 | 京信通信技术(广州)有限公司 | Clock delay method, clock delay system, clock delay equipment, data access method, data access system and data access equipment |
| CN103984540A (en) * | 2014-04-14 | 2014-08-13 | 美的集团股份有限公司 | Method and device for generating hardware interface running program |
| CN104809094A (en) * | 2015-05-25 | 2015-07-29 | 中国电子科技集团公司第四十七研究所 | SPI (Serial Peripheral Interface) controller and communication method for SPI controller |
| CN107832250A (en) * | 2017-11-02 | 2018-03-23 | 北京中电华大电子设计有限责任公司 | A kind of master-slave communication timing method and method for reliable transmission based on SPI |
-
2019
- 2019-07-23 CN CN201910669059.2A patent/CN110399318A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103488601A (en) * | 2012-06-12 | 2014-01-01 | 京信通信技术(广州)有限公司 | Clock delay method, clock delay system, clock delay equipment, data access method, data access system and data access equipment |
| CN103984540A (en) * | 2014-04-14 | 2014-08-13 | 美的集团股份有限公司 | Method and device for generating hardware interface running program |
| CN104809094A (en) * | 2015-05-25 | 2015-07-29 | 中国电子科技集团公司第四十七研究所 | SPI (Serial Peripheral Interface) controller and communication method for SPI controller |
| CN107832250A (en) * | 2017-11-02 | 2018-03-23 | 北京中电华大电子设计有限责任公司 | A kind of master-slave communication timing method and method for reliable transmission based on SPI |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114826811A (en) * | 2021-01-28 | 2022-07-29 | 南宁富桂精密工业有限公司 | Data transmission method and system |
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Application publication date: 20191101 |