CN101127027B - FPGA loading method and its equipment - Google Patents
FPGA loading method and its equipment Download PDFInfo
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- CN101127027B CN101127027B CN2007101541071A CN200710154107A CN101127027B CN 101127027 B CN101127027 B CN 101127027B CN 2007101541071 A CN2007101541071 A CN 2007101541071A CN 200710154107 A CN200710154107 A CN 200710154107A CN 101127027 B CN101127027 B CN 101127027B
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Abstract
The utility model relates to an FPGA loading method and a device; wherein the device comprises a digital signal processor (11) and an FPGA (12) connected with the digital signal processor, an application device and non-volatile storage medium which stores configuration data; wherein the digital signal processor (11) is optionally connected with the FPGA or the application device through own synchronous serial port and corresponding pin switching module (32); wherein the method comprises: in FPGA loading phase, the pin switching module (32) is switched to be connected with the FPGA; the synchronous serial port is configured and used for passive serial mode loading the FPGA (12); after loading is completed, the pin switching module (32) is switched to be connected with the application device; the synchronous serial port is configured and used for completing detailed application. The utility model has the advantages of making full use of synchronous serial port source, not affecting normal use, decreasing GPIO source waste upon DSP, improving loading speed and remarkably lower cost of using special PROM.
Description
Technical field
The present invention relates to DSP and use, be specifically related to a kind of FPGA loading method and device thereof.
Background technology
At present, field programmable gate array Field Programmable Gate Array (being called for short FPGA) becomes " glue " of modern digital application system with its inner abundant numerous I/O pin of trigger and outside, it also is that so the programmable features of FPGA has promoted the interface capability of DSP for the effect of digital signal processor Digital Singnal Processor (being called for short DSP) chip application system.The logic of fpga chip internal operation is that the form with configuration file is kept on certain storage medium, need when powering up, load, common practices is the data among the outside PROM initiatively to be read in by serial mode dispose in the sheet among the RAM, and after configuration was finished, FPGA entered duty.After the power down, FPGA reverts to white, and the internal logic relation disappears.When needs are revised the FPGA function, only need change a slice PROM and get final product.Revise at the fpga logic that the R﹠D process of product has repeatedly, special after operation because of the logical update of FPGA, former burned PROM chip in batches has to discard, and the characteristic of this personality PROM one-time programming and fancy price can be brought huge waste, increase meaningless cost expense.
The loading of FPGA can also realize by the passive serial mode in fact: configuration file stores on non-volatile memory medium FLASH, can realize repeatedly erasable, thereby saved a large amount of costs.In the passive serial load mode, general universaling I/O port General-Purpose Input/Output (the being called for short GPIO) pin that adopts carries out, as shown in Figure 1, need 5 I/O pin altogether, wherein GPIO1～2 are as the synchronous clock and the data output of loading procedure, the control pin that GPIO3 loads as profile data, GPIO4～5 are as the status poll in the loading procedure.Having on the DSP of synchronous serial interface, GPIO1～2 pin can substitute with synchronous serial interface.But this method can take GPIO and synchronous serial interface resource, and GPIO belongs to scarce resource and is complexing pin mostly in the DSP application system, operational and few.And synchronous serial interface MsBsp typical case is used for connecting audio A and DA device, and structure as shown in Figure 2.
Summary of the invention
The technical issues that need to address of the present invention provide a kind of FPGA loading method and device thereof, can use the passive serial mode to load, and save the pin resource of DSP simultaneously.
Above-mentioned first technical matters of the present invention solves like this, and a kind of FPGA loading method is provided, and digital signal processor may further comprise the steps by self synchronous serial interface McBsp and corresponding pin handover module selection connection FPGA or application device:
1.1) in the FPGA load phase, switch described pin handover module and connect FPGA, dispose and utilize described synchronous serial interface that FPGA is carried out the passive serial mode and load;
1.2) load finish after, switch described pin handover module and connect application device, dispose and utilize described synchronous serial interface to finish concrete application.
Make full use of the loading of FPGA and the use sequencing relation in time of McBsp like this, McBsp is done some changes and configuration,, make it be configured to the assembly of synchronous serial interface and GPIO earlier in the FPGA load phase by outside simple circuit; After the FPGA loading is finished, be the McBsp recovery configuring that normal serial ports uses again.
According to loading method provided by the invention, it is audio frequency D/A and A/D converter spare or T1 framer and T1 deframer or E1 framer and E1 deframer or high-speed serial bus HighWay interchanger or the like that described application device includes, but are not limited to.
According to loading method provided by the invention, described step 1.2) connect in is that AD_CLK, AD_DOUT, the AD_WCLK pin of corresponding respectively DA_CLK, DA_DIN, DA_WCLK and the A/D converter spare with the D/A switch device of self-defined CLKX, DX, FSX, CLKR, DR, FSR pin in the described synchronous serial interface links to each other.
According to loading method provided by the invention, described step 1.1) connects in that to be that self-defined CLKX, DX, CLKR, DR, FSR pin in the described synchronous serial interface is corresponding respectively link to each other with LG_CLK, LG_DIN, PROGRAM, DONE, the INIT pin of FPGA.
According to loading method provided by the invention, it is that the configuration data that digital signal processor reads in the connected non-volatile memory medium utilizes described synchronous serial interface that FGPA is loaded again that described passive serial mode loads.
According to loading method provided by the invention, described pin handover module is one group of triple gate; Described triple gate is in the same way or the reverse signal switch, that is: before and after switching sense constant or switch before and after the change-over switch that changes of sense.
According to loading method provided by the invention, the switching of described pin handover module is controlled by the GPIO pin of connected FPGA, that is: the GPIO pin of FPGA two kinds of control signals of output or a kind of control signal add no-output.
Above-mentioned another technical matters of the present invention solves like this, a kind of FPGA charger is provided, the non-volatile memory medium that comprises digital signal processor and connected FPGA, application device and preservation configuration data, digital signal processor is by self synchronous serial interface and corresponding pin handover module selection connection FPGA or voice applications device.。
According to charger provided by the invention, it is audio frequency D/A and A/D converter spare or T1 framer and T1 deframer or E1 framer and E1 deframer or high-speed serial bus HighWay interchanger or the like that described application device includes, but are not limited to.
According to charger provided by the invention, described pin handover module is one group of triple gate, and described triple gate is in the same way or reverse change-over switch, that is: before and after switching sense constant or switch before and after the change-over switch that changes of sense.
FPGA loading method provided by the invention and device thereof compared with prior art, have following advantage:
1. make full use of the resource of McBsp, do not influence the normal use of McBsp;
2. reduce the waste to the GPIO resource of DSP, the present invention only needs 1 GPIO pin to be used for the control of triple gate, and this IO pin can be provided by FPGA;
3.McBsp be built-in with shift register, reduced the shifting function of software, improved loading velocity;
4. significantly reduce the cost of personality PROM.
Description of drawings
Further the present invention is described in detail below in conjunction with the drawings and specific embodiments.
Fig. 1 is that the FPGA passive serial loads synoptic diagram;
Fig. 2 is the typical annexation synoptic diagram of DSP synchronous serial interface McBsp and audio A/D, D/A;
Fig. 3 is the structural representation according to an embodiment of FPGA charger provided by the invention;
Fig. 4 is the change-over switch in the same way in the pin handover module in the device shown in Figure 3;
Fig. 5 is the reverse change-over switch in the pin handover module in the device shown in Figure 3;
Fig. 6 is of the present invention FPGA loading method schematic flow sheet corresponding with Fig. 3.
Embodiment
At first, basis of the present invention is described:
(1) as shown in Figure 1, FPGA passive serial load mode: this system is made up of digital signal processor of being responsible for loading 11 and loading object FPGA12.LG_CLK and LG_DIN are used separately as the synchronous clock and the data input of loading, and the FPGA configuration file is sent from the pin of digital signal processor 11 with synchronous clock with serial data form, and 1 clock sends lbit, is unit with 1byte; The control pin that PROGRAM loads as configuration data, low pulse that certain width arranged empty the operation that just can load FPGA12 behind the configuration RAM of FPGA inside; Whether INIT and DONE inquire about INIT as the status poll in the loading procedure after emptying configuration RAM, be used for judging whether FPGA empties action effective, inquire about INIT after having loaded 1byte, wrong in order to judge loading data.DONE uprises the loading of expression configuration file and finishes.
(2) as shown in Figure 2, digital signal processor voice applications: in this system, digital signal processor 11 utilizes the transmitting terminal 24 among the synchronous serial interface McBsp to link to each other with audio frequency D/A device 22, in order to carry out the conversion of DAB to analogue audio frequency, all signals are all exported for digital signal processor 11; Digital signal processor 11 utilizes the receiving end 25 among the synchronous serial interface McBsp to link to each other with audio A/D device 23, and in order to carry out the conversion of analogue audio frequency to DAB, all signals are all imported for digital signal processor 11.
In second step, the present invention is described in conjunction with the specific embodiment of the invention:
(1) corresponding intrument
This device, structure are made up of digital signal processor 11, pin handover module 32, pin line 33, switch control unit 34 as shown in Figure 3.Digital signal processor 11 is responsible for the configuration of McBsp pin and the transmitting-receiving of data, in the FPGA load phase, McBsp is the assembly of synchronous serial interface and GPIO, and transmitting terminal works in the synchronous serial interface mode, as the transmission of data, and receiving end is used for controlling and status poll as GPIO.McBsp reverted to normal serial ports mode of operation after loading was finished, and carried out the transmitting-receiving of voice data, and its pin CLKS inserts external clock.Pin handover module 32 is in order to load the switching that is connected pin with non-load phase, relevant pins at power on default and load phase McBsp is connected with the relevant pins that FPGA loads, particularly the CLKX of McBsp, DX, CLKR, DR, FSR link to each other with LG_LK, LG_DIN, PROGRAM, DONE, the INIT of FPGA, McBsp was connected with the relevant pins of AD, DA after loading was finished, particularly the CLKX of McBsp, DX, FSX link to each other with DA_CLK, DA_DIN, DA_WCLK respectively, and CLKR, DR, FSR link to each other with AD_CLK, AD_DOUT, AD_WCLK respectively.For the constant change-over switch of sense before and after switching, as shown in Figure 4, use triple gate combination 321, for the change-over switch that sense changes, as shown in Figure 5, use triple gate combination 322.Switch control unit 34 is used for the control that pin switches, and powers on default and load phase is a high level, and this moment, switching controls did not have input signal with GPIO, loads to finish the back switching controls and put 0 with GPIO and guarantee that low level is to finish the integral body switching of pin handover module 32; This switching controls can be a GPIO pin that is loaded on the FPGA with GPIO.
(2) principle of work
The workflow of this device as shown in Figure 6, may further comprise the steps:
4002) the I/O pin of initialization DSP guarantees that the relevant tube of McBsp and FPGA links to each other;
4004) configuration McBsp debit is GPIO to port, sets the direction of each pin;
4006) put low PROGRAM, RAM carries out zero clearing to the FPGA configuration, and low state is kept a period of time;
4008) put high PROGRAM;
4010) wait for 50～75us, wait configuration RAM zero clearing to finish;
4012) whether inquiry INIT pin is high, be height explanation configuration RAM clear operation success, otherwise failure need skip to step 4006), be configured the clear operation of RAM again;
4014) configuration RAM clear operation is finished, the loading of beginning FPGA;
4016) from load document, read in 1byte, write transmitter register;
4018) the I/O pin of DSP is by bit output profiles data, and the I/O in this example is the DX pin of McBsp transmitting terminal;
4020) send 1byte after, whether inquiry INIT pin is high, goes to step 4022 for height explanation profile data writes success) carry out, otherwise the wrong needs of ablation process skip to step 4006), be configured the RAM clear operation again;
4022), whether inquiry DONE pin is high, finishes to go to step 4024 for height explanation profile data writes) carry out, otherwise ablation process does not finish to skip to step 4016), continue loading configuration file;
4024) FPGA configuration file loaded, FPGA starts, and can export to switch control unit 304 output low levels;
4026) switching McBsp is connected with audio A/DA device;
4028) configuration McBsp recovers normal serial ports mode of operation.
Claims (9)
1. a FPGA loading method is characterized in that, digital signal processor (11) may further comprise the steps by self synchronous serial interface McBsp and corresponding pin handover module (32) selection connection FPGA (12) or application device:
1.1) in the FPGA load phase, self-defined CLKX, the DX among the described synchronous serial interface McBsp, CLKR, DR, FSR pin are corresponding respectively to link to each other with LG_CLK, LG_DIN, PROGRAM, DONE, the INIT pin of FPGA; Switch described pin handover module (32) and connect FPGA, dispose and utilize described synchronous serial interface McBsp that FPGA (12) is carried out the passive serial mode and load; The LG_CLK of FPGA and LG_DIN are used separately as the synchronous clock and the data input of loading, and the FPGA configuration file is sent from the pin of digital signal processor (11) with synchronous clock with serial data form, and 1 clock sends 1, is unit with 1 byte; The control pin that the PROGRAM of FPGA loads as configuration data after a low pulse that certain width arranged empties the configuration RAM of FPGA inside, loads the operation of FPGA; The INIT of FPGA and DONE are as the status poll in the loading procedure, inquire about INIT behind the RAM emptying configuration, be used for judging whether FPGA empties action effective, inquire about INIT after having loaded 1 byte, in order to judge whether loading data is wrong, DONE uprises the loading of expression configuration file and finishes;
1.2) load finish after, switch described pin handover module (32) and connect application device, dispose and utilize described synchronous serial interface McBsp to finish concrete application.
2. according to the described loading method of claim 1, it is characterized in that described application device is audio frequency D/A (22) and mould/number (23) switching device, perhaps framer and deframer.
3. according to the described loading method of claim 2, it is characterized in that described step 1.2) in to connect be that AD_CLK, AD_DOUT, the AD_WCLK pin of corresponding respectively DA_CLK, DA_DIN, DA_WCLK and the A/D converter spare (23) with D/A switch device (22) of self-defined CLKX, DX, FSX, CLKR, DR, FSR pin among the described synchronous serial interface McBsp links to each other.
4. according to the described loading method of claim 1, it is characterized in that it is that the configuration data that digital signal processor (11) reads in the connected non-volatile memory medium utilizes described synchronous serial interface McBsp that FPGA (12) is loaded again that described passive serial mode loads.
5. according to the described loading method of claim 1, it is characterized in that described pin handover module (32) is one group of triple gate; Described triple gate is (321) or oppositely (322) change-over switch in the same way.
6. according to the described loading method of claim 5, it is characterized in that the switching of described pin handover module is controlled by the GPIO pin of connected FPGA.
7. FPGA charger, comprise digital signal processor (11) and connected FPGA (12), the non-volatile memory medium of application device and preservation configuration data, it is characterized in that, digital signal processor (11) is by self synchronous serial interface McBsp and corresponding pin handover module (32) selection connection FPGA (12) or application device, digital signal processor (11) is responsible for the configuration of synchronous serial interface McBsp pin and the transmitting-receiving of data, in the FPGA load phase, synchronous serial interface McBsp is the assembly of synchronous serial interface and GPIO, transmitting terminal works in the synchronous serial interface mode, as the transmission of data, and receiving end is used for controlling and status poll as GPIO; Synchronous serial interface McBsp reverted to normal serial ports mode of operation after loading was finished, and carried out the transmitting-receiving of voice data;
Relevant pins at power on default and load phase synchronous serial interface McBsp is connected with the relevant pins that FPGA loads, and specifically is that CLKX, DX, CLKR, DR, the FSR of synchronous serial interface McBsp links to each other with LG_CLK, LG_DIN, PROGRAM, DONE, the INIT of FPGA; Synchronous serial interface McBsp was connected with the relevant pins of AD, DA after loading was finished, CLKX, the DX, the FSX that specifically are synchronous serial interface McBsp link to each other with DA_CLK, DA_DIN, DA_WCLK respectively, and CLKR, DR, FSR link to each other with AD_CLK, AD_DOUT, AD_WCLK respectively.
8. according to the described charger of claim 7, it is characterized in that described application device is audio frequency D/A (22) and mould/number (23) switching device, perhaps framer and deframer.
9. according to the described charger of claim 7, it is characterized in that described pin handover module (32) is one group of triple gate, described triple gate is (321) or oppositely (322) change-over switch in the same way.
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| CN2007101541071A CN101127027B (en) | 2007-09-12 | 2007-09-12 | FPGA loading method and its equipment |
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| CN2007101541071A CN101127027B (en) | 2007-09-12 | 2007-09-12 | FPGA loading method and its equipment |
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| CN101127027A CN101127027A (en) | 2008-02-20 |
| CN101127027B true CN101127027B (en) | 2011-08-10 |
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| CN101826025A (en) * | 2010-03-22 | 2010-09-08 | 太仓市同维电子有限公司 | Device for upgrading firmware of field programmable logic device and method thereof |
| CN102968326A (en) * | 2012-12-04 | 2013-03-13 | 中国北方车辆研究所 | Field programmable gate array (FPGA) parallel dynamic loading method |
| CN109407059A (en) * | 2018-09-28 | 2019-03-01 | 航天恒星科技有限公司 | A kind of Strapdown decoupling implementation method |
| CN112988271A (en) * | 2021-03-19 | 2021-06-18 | 四川航天神坤科技有限公司 | System and method for dynamically configuring FPGA (field programmable Gate array) in passive SelectMAP (selectable MAP) mode |
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