CN102968326A

CN102968326A - Field programmable gate array (FPGA) parallel dynamic loading method

Info

Publication number: CN102968326A
Application number: CN2012105289555A
Authority: CN
Inventors: 王文涛; 李姝�; 颜廷海; 宋海平; 周莲
Original assignee: China North Vehicle Research Institute
Current assignee: China North Vehicle Research Institute
Priority date: 2012-12-04
Filing date: 2012-12-04
Publication date: 2013-03-13

Abstract

The invention relates to an FPGA parallel dynamic loading method and belongs to the technical field of electro-optical countermeasures. The method comprises the steps that a mapping file to be loaded is generated according to a product requirement and a functional demand; the mapping file is written into an FLASH storage; a core digital signal processor (DSP) reads the mapping file; and the core DSP loads the mapping file into an FPGA chip to be loaded in a parallel transmission mode through a bus. The technical scheme includes that the mapping file is loaded to the FPGA chip through the parallel transmission mode which is based on the bus. Compared with an existing serial transmission mode, the parallel transmission mode improves the loading speed greatly. The mapping file which meets the requirement of the chip and the application demand can be generated through a joint test action group (JTAG) programming mode in advance, so that the mapping file can be updated at any time, the flexibility of a system is improved effectively, the trouble in repeated inserting and pulling of the FLASH storage in the prior art is avoided at the same time, and the time cost of an operator is reduced greatly.

Description

A kind of FPGA dynamic loading method that walks abreast

Technical field

The present invention relates to the photoelectronic warfare field, be specifically related to the parallel dynamic loading method of a kind of FPGA, it can be applicable in the hardware circuit design of weapon platform DSP+FPGA framework.

Background technology

FPGA (Field-Programmable Gate Array, field programmable gate array) the loaded in parallel mode of mainstream applications is to adopt the modes such as external FLASH storer, synchronous serial interface to load at present.

Because the FLASH storer that the manufacturer of FPGA is provided for loading more, it meets the loading sequential of FPGA, support simultaneously JTAG (Joint Test Action Group, joint test behavior organizational standard) programmes, from ordinary meaning, it is a kind of very easily download scenarios, certainly, also can adopt synchronous serial interface to realize loading.

But no matter be that the FLASH storer loads or synchronous serial interface loads, all can't provide good speed of download, this is under fairly large application scenario, and its load time often surpasses 300ms, affects the toggle speed of system.In addition, adopting FLASH storer mode to load also can be because of the change of demand, thereby ceaselessly the FLASH storer is transferred to separately xcopy, thereby has greatly increased process complexity, has increased the weight of staff's time cost.

Therefore, how to develop the new FPGA load mode under a kind of DSP of being applied to (Digital Signal Processor, digital signal processor)+FPGA framework, with the requirement of the aspects such as the high speed that adapts to loading velocity and system flexibility.

Summary of the invention

The technical matters that (one) will solve

The technical problem to be solved in the present invention is how to improve the speed of FPGA loading procedure in the prior art, the dirigibility of system applies, and the artificial time cost that how to reduce existing FPGA loading scheme.

(2) technical scheme

In order to solve the problems of the technologies described above, the invention provides the parallel dynamic loading method of a kind of FPGA, the method comprises the steps:

Step S1: according to the product application requirements of fpga chip to be loaded and the function needs in the concrete practical application, generate the image file to fpga chip to be loaded;

Step S2: described image file is write in the FLASH storer;

Step S3: read image file in the described FLASH storer by the DSP core processor;

Step S4:DSP core processor is loaded on described image file in the described fpga chip to be loaded by the mode of bus with parallel transmission.

Wherein, among the described step S1, generate the image file to fpga chip to be loaded by the JTAG programming mode.

Wherein, among the described step S2, by the JTAG programming mode described image file is write in the FLASH storer.

(3) beneficial effect

Technical solution of the present invention possesses following some beneficial effect compared with prior art:

(1) loads image file to fpga chip by the parallel transmission mode based on bus, thereby compare existing serial transmission mode, greatly promoted loading velocity.

(2) owing to can generate the image file that meets chip requirement and application demand by the JTAG programming mode in advance, thereby can realize the at any time renewal of image file, in the Effective Raise system flexibility, also avoid repeatedly plugging in the prior art trouble of FLASH storer, greatly reduced operating personnel's time cost.

Description of drawings

Fig. 1 is the process flow diagram of technical solution of the present invention.

Fig. 2 is the interface synoptic diagram that generates image file in the technical solution of the present invention.

Fig. 3 is the schematic diagram that disposes interlock circuit in the technical solution of the present invention with fpga chip.

Embodiment

For making purpose of the present invention, content and advantage clearer, below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.

Be the speed that improves FPGA loading procedure in the prior art, the dirigibility of system applies, and the artificial time cost that how to reduce existing FPGA loading scheme, the invention provides the parallel dynamic loading method of a kind of FPGA, as shown in Figure 1, the method comprises the steps:

Step S1: according to the product application requirements of fpga chip to be loaded and the function needs in the concrete practical application, generate the image file to fpga chip to be loaded by the JTAG programming mode;

Step S2: described image file is write in the FLASH storer by the JTAG programming mode;

Specify below in conjunction with embodiment.

Embodiment

Present embodiment comes implementation based on technique scheme, and its description comprises: circuit design part, image file generating portion and image file loading section.

1, circuit design

The DSP core processor of present embodiment product-based ADSP-TS101 designs.

As shown in Figure 2, wherein, fpga chip loads by the external bus of DSP core processor.

The M[2:0 of FPGA is set] be 110, FPGA namely is set in Slave Parallel pattern, the PROGRAM signal of FPGA is used for removing FPGA under this pattern, whether the INIT signal is used to indicate reset mode and finishes, and whether the DONE signal is used to indicate loading successful, D[0:7] input as data, CCLK is as input clock, CS selects as sheet, and/WR is as written allowance signal, and BUSY is as the FPGA busy signal.

Because the cycle of FPGA is much smaller than the operating cycle of DSP, so the not use of BUSY signal, and is unsettled.

FLAG1 is set as the output signal of DSP, and the reset signal of DSP through diode line with after be used for controlling the PROGRAM signal;

FLAG2 is set as the input signal of DSP, is used for detecting the INIT signal of FPGA;

The DONE signal of FPGA is connected to light emitting diode, is used to refer to the stress state of FPGA;

The D[0:7 of FPGA] with DSP_D[0:7] link to each other;

Because FPGA is only had write operation, so FPGA /the WR signal ground;

The MS1 connection is connected in CS sheet choosing with DSP;

CCLK is connected WRL and is connected with DSP;

2, image file generates

At first, utilize Xilinx ISE to edit the project file that will download to FPGA, load test through JTAG, confirm that function meets design requirement.

Double-click the Genrate Programming File in the Process for Current Source hurdle, eject an impact software window this moment, selects Xilinx PROM File Formatter.Select PROM Properties in the File menu, eject Option Box, the setting in the Format tab as shown in Figure 3.

Click " determining ", can preserve into required FPGA data streaming file this moment.

The * .HEX that generates is burnt to the FPGA destination address of FLASH by the VDSP software of ADSP-TS101.And the file destination size write the 0x200000 deviation post.

3, Bootload flow process

The Bootload flow process is as follows:

1) reads the FPGA destination address of FLASH+0x200000 skew, calculate the size of FPGA file destination;

2) it is low putting the PROGRAM signal;

3) wait for, until the INIT signal is low.

4) put the PROGRAM signal for high;

5) wait for, until the INIT signal is high.The read-write counter zero clearing.

6) if read-write counter is big or small less than file destination, carries out following steps, otherwise transfer to next step:

The FPGA target data skew of a) reading among the FLASH is the value of counter position.

B) write this and be worth MS1 address space to DSP.

7) wait for 10ms.

8) check the level of DONE signal, if be height, return and load successfully, load unsuccessfully otherwise return.

The above only is preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the technology of the present invention principle; can also make some improvement and distortion, these improvement and distortion also should be considered as protection scope of the present invention.

Claims

1. the parallel dynamic loading method of FPGA is characterized in that the method comprises the steps:

Step S2: described image file is write in the FLASH storer;

2. the parallel dynamic loading method of FPGA as claimed in claim 1 is characterized in that, among the described step S1, generates the image file to fpga chip to be loaded by the JTAG programming mode.

3. the parallel dynamic loading method of FPGA as claimed in claim 1 is characterized in that, among the described step S2, by the JTAG programming mode described image file is write in the FLASH storer.