CN102184158B - Daughter board with two-stage FPGA chip and collocation method of two-stage FPGA chip - Google Patents
Daughter board with two-stage FPGA chip and collocation method of two-stage FPGA chip Download PDFInfo
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Abstract
The invention relates to the field of video processing, and discloses a daughter board with a two-stage FPGA chip and a collocation method of the two-stage FPGA chip. For the daughter board, during the electrifying process, the first-stage FPGA chip obtains the self configuration data from a first nonvolatile memory so as to finish configuration and initialization; each second-stage FPGA chip obtains the self configuration data from a second nonvolatile memory so as to finish configuration and initialization; and the types and configuration data of all the second-stage FPGA chips are fully the same. Since the nonvolatile memory does not need to be configured for each FPGA chip and a microprocessor does not need to be increased on the daughter board, the daughter board is low in cost and realizes the configuration management of all the FPGA chips in the daughter board conveniently for the CPU system board .
Description
Technical field
The present invention relates to field of video processing, particularly the configuring technical of the fpga chip in Video processing.
Background technology
Large-size screen monitors control system is generally complicated multifunction system, according to functional module, divides: substantially can be divided into video input functional module (as video inputs such as VGA, HDMI, DVI, BNC, IP network), master control function module (central processor CPU system), output function module (as video outputs such as DVI, HDMI, VGA).In modern system design, often each functional module is gone to realization with plank independently, can be divided into tablet, master control borad, output board, between each plank, can be connected on a public backboard, by bus (being generally PCIE or network), communicate the annexation of large each plank of screen controller as shown in Figure 1.In large screen system, CPU is only present in master control borad, and master control borad is responsible for whole system (be mainly input, output board, be referred to as daughter board) control and management, carries out interactive communication by network and remote server simultaneously.Each daughter board is mainly responsible for the processing of video image, and internal main will be with field programmable gate array (Field Programmable Gate Array, be called for short " FPGA ") chip be responsible for the cutting apart of video image, splicing, stack, convergent-divergent and doubly hardwood process, in this system, between master control borad and each daughter board, can only carry out data communication by bus.
In large-size screen monitors application or monitoring field, because fpga chip is having the plurality of advantages such as be applicable to Video segmentation, splicing, stack, convergent-divergent, times frame and video output time delay is little, time-delay consistency is good very much aspect Video processing, therefore in this field, be widely used.
Fpga chip is when its normal work, the configuration data of FPGA is stored in static RAM (Static Random Access Memory, be called for short " SRAM ") in, because SRAM is volatile memory, fpga chip configuration information after power down will be lost, while so just requiring to power on, all require external circuit that configuration data is loaded in the SRAM in sheet again, after internal register and I/O initialization complete, FPGA could normal work at every turn.At present as follows to the allocation plan of FPGA:
A kind of scheme is to join special-purpose nonvolatile memory to every fpga chip, FPGA (Master) equipment of deciding now, as long as the configure dedicated pin of FPGA is connected with nonvolatile memory, the configuration data that while powering on, FPGA can produce configuration sequential reading non-volatile storage is automatically to on-chip SRAM, complete configuration and initialization procedure, conventionally nonvolatile memory mainly comprises FLASH and EEPROM (Electrically Erasable Programmable Read Only Memo) (Electrically Erasable Programmable ROM is called for short " EEPROM ").
Another kind of scheme is being applied containing in the system of microprocessor, generally has equally the FLASH (or EEPROM) of storage FPGA configuration data, and be directly connected with microprocessor in this system.Now FPGA does the equipment from (Slave), microprocessor (Master) equipment of deciding, and microprocessor reads the FPGA configuration data of FLASH (or EEPROM) and produces configuration sequential and completes the configuration to FPGA.
Yet, the present inventor finds, owing to using the difference of processing capacity and the restriction of cost, in daughter board, often there is the fpga chip of two or more types, a kind of is high-end fpga chip, supporting bus is directly connected with master control borad, and another kind of fpga chip not supporting bus is directly connected with master control borad.If adopt the first allocation plan, all join a slice nonvolatile memory need to every a slice fpga chip, cost is higher.Because the configuration data of each fpga chip is stored in separately independently in nonvolatile memory, master control borad cannot carry out unified management and configuration to it, cannot carry out remote maintenance.If adopt the second allocation plan, increase microprocessor need to every input, output board, then with microprocessor, go to realize the configuration management of all fpga chips or those fpga chips that are not directly connected with master control borad, this microprocessor must support PCIE or network service could realize with master control borad to communicate by letter, and this class processor price is generally all very high.
Summary of the invention
The object of the present invention is to provide the collocation method of a kind of daughter board with two-stage fpga chip and two-stage fpga chip, with low-cost and realize easily the configuration management of cpu system plate to all FPGA in daughter board.
For solving the problems of the technologies described above, embodiments of the present invention provide a kind of daughter board with two-stage fpga chip, comprise: the first nonvolatile memory, the second nonvolatile memory, the first order on-site programmable gate array FPGA chip being connected with master control borad by bus, the second level fpga chip that at least one is not connected with master control borad by bus, the model of each second level fpga chip is identical with configuration data;
The first nonvolatile memory is connected with first order fpga chip, for storing the configuration data of first order fpga chip;
The second nonvolatile memory is connected with each second level fpga chip, for storing the configuration data of second level fpga chip;
First order fpga chip, for obtain the configuration data of self from the first nonvolatile memory when powering on, completes configuration and initialization;
Each second level fpga chip, for obtain the configuration data of self from the second nonvolatile memory when powering on, completes configuration and initialization.
Embodiments of the present invention also provide a kind of collocation method of two-stage fpga chip, comprise following steps:
When powering on, the first order on-site programmable gate array FPGA chip being connected with master control borad by bus obtains the configuration data of self from the first nonvolatile memory being connected with this first order fpga chip, completes configuration and initialization;
Each second level fpga chip not being connected with master control borad by bus obtains the configuration data of self from the second nonvolatile memory being connected with each second level fpga chip, completes configuration and initialization;
Wherein, the model of each second level fpga chip is identical with configuration data.。
Compared with prior art, the key distinction and effect thereof are embodiment of the present invention:
The first order fpga chip being connected with master control borad by bus is connected with the first nonvolatile memory, each second level fpga chip not being connected with master control borad by bus is connected with the second nonvolatile memory, and the model of each second level fpga chip is identical with configuration data.When powering on, first order fpga chip obtains the configuration data of self from the first nonvolatile memory, completes configuration and initialization; Each second level fpga chip obtains the configuration data of self from the second nonvolatile memory, completes configuration and initialization.Because all second level fpga chip is all same type, configuration data is also identical, therefore only need can complete smoothly the data configuration of all second level fpga chip when powering on by second nonvolatile memory, do not need to be equipped with separately a nonvolatile memory for each fpga chip, and need on daughter board, not increase microprocessor, low-cost and realized easily the configuration management of cpu system plate to all FPGA in daughter board.
Further, daughter board with two-stage fpga chip also comprises output enable control circuit, first order fpga chip is connected with the input end of output enable control circuit, and the output terminal of output enable control circuit is connected with each second level fpga chip with the second nonvolatile memory; The output terminal of output enable control circuit is defaulted as high-impedance state.First order fpga chip is also in the time need to upgrading to the configuration data of second level fpga chip, the output of controlling output enable control circuit is effective, be communicated with the second nonvolatile memory, and the configuration data of the second level fpga chip of storing in the second nonvolatile memory is upgraded, after completing upgrading, first order fpga chip controls the output terminal of output enable control circuit for original state (output terminal that is about to output enable control circuit is controlled as high-impedance state).Control by first order fpga chip to the output channel of output enable control circuit, makes first order fpga chip can read and write and wipe the configuration data of the second nonvolatile memory, completes the upgrading of the configuration data of second level fpga chip.Owing to going second level fpga chip to be configured data management by first order fpga chip, realized master control borad to the configuration management of all FPGA in daughter board and data upgrading, therefore all FPGA configuration informations can carry out network remote renewal by server, and needn't go to scene carry out burning or tear chip open, facilitated the follow-up maintenance of product.And, to the logical resource of first order fpga chip and I/O mouth, take all less, simple and convenient.
Further, first order fpga chip is after the upgrading of configuration data that completes second level fpga chip, can, by the dedicated data line being connected with each second level fpga chip, indicate each second level fpga chip to reload configuration data, thereby realize the online upgrading of fpga chip.
Further, first order fpga chip both can directly be connected with master control borad by bus, also can through backboard, be connected with master control borad by bus, made the present invention not be limited to the annexation of daughter board and master control borad, possessed application scenarios widely.。
Accompanying drawing explanation
Fig. 1 is according to the schematic diagram of each plank annexation of large screen controller of the prior art;
Fig. 2 is according to the structural representation of the daughter board with two-stage fpga chip of first embodiment of the invention;
Fig. 3 is according to the structural representation of the daughter board with two-stage fpga chip of second embodiment of the invention;
Fig. 4 is according to the collocation method process flow diagram of the two-stage fpga chip of third embodiment of the invention.
Embodiment
In the following description, in order to make reader understand the application better, many ins and outs have been proposed.But, persons of ordinary skill in the art may appreciate that even without these ins and outs and the many variations based on following embodiment and modification, also can realize each claim of the application technical scheme required for protection.
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, embodiments of the present invention are described in further detail.
First embodiment of the invention relates to a kind of daughter board with two-stage fpga chip.In the present embodiment, cpu system plate (being master control borad) is directly connected with daughter board by bus, and as shown in Figure 2, bus can be but be not limited to pciE or network-bus.In daughter board, there are two kinds of dissimilar fpga chips: the first order fpga chip being connected with master control borad by bus (being the FPGA0 in Fig. 2) and the second level fpga chip not being connected with master control borad by bus (being the FPGA1-FPGAn in Fig. 2), the model of each second level fpga chip is identical with configuration data.In daughter board, also comprise the first nonvolatile memory (being the nonvolatile memory 1 in Fig. 2), the second nonvolatile memory (being the nonvolatile memory 2 in Fig. 2) and output enable control circuit.
Wherein, master control borad is connected with FPGA0 by bus, and FPGA0 is connected with nonvolatile memory 1, and nonvolatile memory 2 is connected with FPGA1-FPGAn.FPGA0 is connected with the input end of output enable control circuit, and the output terminal of output enable control circuit is connected with FPGA1-FPGAn chip with nonvolatile memory 2.The output terminal of output enable control circuit is defaulted as high-impedance state.FPGA0 can pass through the control to output enable control circuit, is communicated with the output channel of self and nonvolatile memory 2, as shown in Figure 2.That is to say, under default situations, the output terminal of output enable control circuit is high-impedance state (it is invalid to export), between FPGA0 and nonvolatile memory 2 with respect to open circuit, but when needed, it is effective that FPGA0 can control the output of output terminal of output enable control circuit, is communicated with nonvolatile memory 2, and nonvolatile memory 2 is wiped and read-write operation.
Nonvolatile memory 1 is for storing the configuration data of FPGA0 chip.While powering on FPGA0 initiatively the configuration data of reading non-volatile storage 1 in self SRAM, complete configuration and initialization.Nonvolatile memory 2 is for storing the configuration data of FPGA1-FPGAn chip.Because the model of FPGA1-FPGAn chip is identical with configuration data, therefore the configuration data that is actually a kind of fpga chip of storing in nonvolatile memory 2, while powering on, FPGA1-FPGAn obtains the configuration data of self from nonvolatile memory 2, completes configuration and initialization.Specifically, in FPGA1-FPGAn chip, choose in advance one (as FPGA1 chip), by FPGA1 chip configuration, be that aggressive mode (Master) all the other (FPGA2-FPGAn chips) is all configured to from pattern (Slave), the FPGA1 chip of aggressive mode provides configurable clock generator to nonvolatile memory 2 and all the other all fpga chips from pattern (FPGA2-FPGAn chip) when powering on, and send to nonvolatile memory 2 address that instructions and FPGA1-FPGAn configuration data are stored in nonvolatile memory 2, nonvolatile memory 2 is after receiving this instruction, according to the address of receiving, FPGA1-FPGAn configuration data is exported, FPGA1-FPGAn receives data by the data line being connected with nonvolatile memory 2, get the configuration data of self, complete configuration and initialization.Due to when powering on or normally work, the output terminal of output enable control circuit is high-impedance state, be that FPGA0 and nonvolatile memory 2 paths are for disconnecting, therefore nonvolatile memory 2 can only receive the trigger pip of second level fpga chip, makes second level fpga chip can carry out smoothly data configuration.
In the present embodiment, first order fpga chip is also upgraded for the configuration data of first order fpga chip that the first nonvolatile memory is stored.That is to say, while normally working, FPGA0 can receive the instruction read-write non-volatile memory 1 from master control borad, completes the upgrade maintenance of cpu system to self configuration data.If need to the configuration data of second level fpga chip be upgraded, first order fpga chip is also effective for controlling the output of output enable control circuit, be communicated with the second nonvolatile memory, and the configuration data of the second level fpga chip of storing in the second nonvolatile memory is upgraded, after completing upgrading, the output terminal of output enable control circuit is controlled as original state.That is to say, the relevant configuration pin I/O mouth that FPGA0-FPGAn is connected with output enable control circuit when normal work need to be configured to high-impedance state, but FPGA0 can control when needed output enable circuit and make its output effectively, now FPGA0 just can read and write the configuration data with erasable nonvolatile memory 2, complete the configuration data upgrading of FPGA0-FPGAn, and control output enable circuit makes its output invalid after completing data upgrading.When power on next time, FPGA0-FPGAn can reconfigure according to the interior new configuration data of nonvolatile memory 2.
Be not difficult to find, in the present embodiment, because all second level fpga chip is all same type, configuration data is also identical, therefore only need can complete smoothly the data configuration of all second level fpga chip when powering on by second nonvolatile memory, do not need for each fpga chip is equipped with separately a nonvolatile memory, and need on daughter board, not increase microprocessor, low-cost and realized easily the configuration management of cpu system plate to all FPGA in daughter board.
And the control by first order fpga chip to the output channel of output enable control circuit, makes first order fpga chip can read and write and wipe the configuration data of the second nonvolatile memory, completes the upgrading of the configuration data of second level fpga chip.Owing to going second level fpga chip to be configured data management by first order fpga chip, realized master control borad to the configuration management of all FPGA in daughter board and data upgrading, therefore all FPGA configuration informations can carry out network remote renewal by server, and needn't go to scene carry out burning or tear chip open, facilitated the follow-up maintenance of product.And, the logical resource of first order fpga chip and I/O mouth are taken all less, if not volatile memory 2 is SPI FLASH (serial communication bus FLASH), the inner SPI controller of configuration that only needs of FPA0, simple and convenient.Because FPGA0-FPGAn in present embodiment adopts Ganged Serial Configuration pattern, require FPGA1-FPGAn to be necessary for the chip of same model, and duty must be configured to just the same.In order to guarantee correct configuration, configurable clock generator frequency suitably should be reduced.
In addition, be appreciated that in the present embodiment, first order fpga chip only has one, i.e. FPGA0 chip, but in actual applications, first order fpga chip also can have a plurality of, for each first order fpga chip disposes separately a nonvolatile memory.Using the FPGA0 chip of any one first order fpga chip in present embodiment wherein, connect the input end that enables control circuit.
Second embodiment of the invention relates to a kind of daughter board with two-stage fpga chip.The second embodiment and the first embodiment are basic identical, and difference is mainly:
In the first embodiment, first order fpga chip is directly connected with master control borad by bus; And in the present embodiment, first order fpga chip is connected with master control borad through backboard by bus, as shown in Figure 3.It will be understood by those skilled in the art that backboard is the transmission channel of data, thus in present embodiment the annexation of two-stage fpga chip and the function of realization and the first embodiment identical, do not repeat them here.
Because first order fpga chip both can directly be connected with master control borad by bus, also can through backboard, be connected with master control borad by bus, make the present invention not be limited to the annexation of daughter board and master control borad, possess application scenarios widely.
In addition, it is worth mentioning that, in the present embodiment, between first order fpga chip and each second level fpga chip, also be provided with dedicated data line, first order fpga chip, can be by the dedicated data line being connected with each second level fpga chip after the upgrading of configuration data that completes second level fpga chip, indicate each second level fpga chip to reload configuration data, thereby realize the online upgrading of fpga chip.
Third embodiment of the invention relates to a kind of collocation method of two-stage fpga chip, and idiographic flow as shown in Figure 4.
In step 410, when powering on, the first order fpga chip being connected with master control borad by bus obtains the configuration data of self from the first nonvolatile memory being connected with this first order fpga chip, completes configuration and initialization.Each second level fpga chip not being connected with master control borad by bus obtains the configuration data of self from the second nonvolatile memory being connected with each second level fpga chip, completes configuration and initialization.Wherein, the model of each second level fpga chip is identical with configuration data.
It is specific as follows that each second level fpga chip obtains self the mode of configuration data from the second nonvolatile memory:
In each second level fpga chip, select one in advance, the second level fpga chip of selection is configured to aggressive mode, non-selected all the other second level fpga chips are configured to from pattern.When powering on, the second level fpga chip of aggressive mode provides configurable clock generator to the second nonvolatile memory and each second level fpga chip from pattern when powering on, and send to the second nonvolatile memory the address that instruction and second level fpga chip configuration data are stored in the second nonvolatile memory, the second nonvolatile memory is after receiving this instruction, according to the address of receiving, second level fpga chip configuration data is exported, second level fpga chip receives data by the data line being connected with the second nonvolatile memory, get the configuration data of self, complete configuration and initialization.
At first order fpga chip and second level fpga chip, complete after configuration and initialization, enter normal operating conditions, enter step 420.
In step 420, in normal operation, first order fpga chip judges whether to upgrade to configuration data.If first order fpga chip gets the instruction that will upgrade to configuration data from the needs of master control borad by bus, enter step 430; Otherwise return to this step.
In step 430, whether the configuration data that the judgement of first order fpga chip need to be upgraded is the configuration data of first order fpga chip, if, enter step 440, first order fpga chip is upgraded to the configuration data of the first order fpga chip of storing in the first nonvolatile memory.If first order fpga chip judges that the configuration data that need to upgrade is not the configuration data of first order fpga chip, the configuration data of second level fpga chip need to be upgraded, and enters step 450.
In step 450, first order fpga chip is upgraded to the configuration data of the second level fpga chip of storing in the second nonvolatile memory.
Specifically, the output of first order fpga chip control output enable control circuit is effective, the input end of this output enable control circuit is connected with this first order fpga chip, output terminal is connected with each second level fpga chip with the second nonvolatile memory, and output terminal is defaulted as the control circuit of high-impedance state.First order fpga chip is effective by the output of control output enable control circuit, be communicated with the second nonvolatile memory, and the configuration data of the second level fpga chip of storing in the second nonvolatile memory is upgraded, after completing upgrading, first order fpga chip controls the output terminal of output enable control circuit for original state.When power on next time, second level fpga chip can reconfigure according to configuration data new in the second nonvolatile memory.
Be not difficult to find, present embodiment is the method embodiment corresponding with the first embodiment, present embodiment can with the enforcement of working in coordination of the first embodiment.The correlation technique details of mentioning in the first embodiment is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in present embodiment also can be applicable in the first embodiment.
Four embodiment of the invention relates to a kind of collocation method of two-stage fpga chip.The 4th embodiment and the 3rd embodiment are basic identical, and difference is mainly:
In the 3rd embodiment, after the configuration data upgrading that completes second level fpga chip, second level fpga chip is when power on next time, according to configuration data new in the second nonvolatile memory, reconfigures.
And in the present embodiment, after the configuration data upgrading that completes second level fpga chip, first order fpga chip also can, by the dedicated data line being connected with each second level fpga chip, indicate each second level fpga chip to reload configuration data, to realize online upgrading.
Be not difficult to find, present embodiment is the method embodiment corresponding with the second embodiment, present embodiment can with the enforcement of working in coordination of the second embodiment.The correlation technique details of mentioning in the second embodiment is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in present embodiment also can be applicable in the second embodiment.
It should be noted that, each method embodiment of the present invention all can be realized in modes such as software, hardware, firmwares.No matter the present invention realizes with software, hardware or firmware mode, instruction code can be stored in the storer of computer-accessible of any type (for example permanent or revisable, volatibility or non-volatile, solid-state or non-solid-state, fixing or removable medium etc.).Equally, storer can be for example programmable logic array (Programmable Array Logic, be called for short " PAL "), random access memory (Random Access Memory, be called for short " RAM "), programmable read only memory (Programmable Read Only Memory, be called for short " PROM "), ROM (read-only memory) (Read-Only Memory, be called for short " ROM "), Electrically Erasable Read Only Memory (Electrically Erasable Programmable ROM, be called for short " EEPROM "), disk, CD, digital versatile disc (Digital Versatile Disc, be called for short " DVD ") etc.
Although by with reference to some preferred embodiment of the present invention, the present invention is illustrated and described, those of ordinary skill in the art should be understood that and can to it, do various changes in the form and details, and without departing from the spirit and scope of the present invention.
Claims (9)
1. the daughter board with two-stage fpga chip, it is characterized in that, comprise: the first nonvolatile memory, the second nonvolatile memory, the first order on-site programmable gate array FPGA chip being connected with master control borad by bus, the second level fpga chip that at least two are not connected with master control borad by bus, described in each, the model of second level fpga chip is identical with configuration data;
Described the first nonvolatile memory is connected with described first order fpga chip, for storing the configuration data of described first order fpga chip;
Described the second nonvolatile memory is connected with second level fpga chip described in each, for storing the configuration data of described second level fpga chip;
Described first order fpga chip, for obtain the configuration data of self from described the first nonvolatile memory when powering on, completes configuration and initialization;
Described in each, second level fpga chip, for obtain the configuration data of self from described the second nonvolatile memory when powering on, completes configuration and initialization;
The described daughter board with two-stage fpga chip also comprises output enable control circuit, described first order fpga chip is connected with the input end of described output enable control circuit, and the output terminal of described output enable control circuit is connected with second level fpga chip described in each with described the second nonvolatile memory; The output terminal of described output enable control circuit is defaulted as high-impedance state;
Described first order fpga chip is also in the time need to upgrading to the configuration data of described second level fpga chip, the output of controlling described output enable control circuit is effective, be communicated with described the second nonvolatile memory, and the configuration data of the described second level fpga chip of storing in described the second nonvolatile memory is upgraded, after completing described upgrading, the output terminal of described output enable control circuit is controlled as original state.
2. the daughter board with two-stage fpga chip according to claim 1, it is characterized in that, described first order fpga chip is also for after the upgrading of configuration data that completes described second level fpga chip, by the dedicated data line with second level fpga chip is connected described in each, indicate second level fpga chip described in each to reload configuration data.
3. the daughter board with two-stage fpga chip according to claim 1, is characterized in that, in the described described second level fpga chip comprising with the daughter board of two-stage fpga chip, a second level fpga chip is configured to aggressive mode; All the other second level fpga chips are configured to from pattern;
The second level fpga chip of described aggressive mode for providing configurable clock generator to described the second nonvolatile memory and described each second level fpga chip from pattern when powering on.
4. the daughter board with two-stage fpga chip according to claim 1, is characterized in that, described first order fpga chip is also upgraded for the configuration data of described first order fpga chip that described the first nonvolatile memory is stored.
5. the daughter board with two-stage fpga chip according to claim 1, is characterized in that, described first order fpga chip is directly connected with described master control borad by bus, or described first order fpga chip is connected with described master control borad through backboard by bus.
6. a collocation method for two-stage fpga chip, is characterized in that, comprises following steps:
When powering on, the first order on-site programmable gate array FPGA chip being connected with master control borad by bus obtains the configuration data of self from the first nonvolatile memory being connected with this first order fpga chip, completes configuration and initialization;
Each second level fpga chip not being connected with master control borad by bus obtains the configuration data of self from the second nonvolatile memory being connected with second level fpga chip described in each, completes configuration and initialization; Described second level fpga chip is greater than one;
Wherein, described in each, the model of second level fpga chip is identical with configuration data;
In the time need to upgrading to the configuration data of described second level fpga chip, the output of described first order fpga chip control output enable control circuit is effective, the input end of described output enable control circuit is connected with this first order fpga chip, output terminal is connected with second level fpga chip described in each with described the second nonvolatile memory, and output terminal is defaulted as the control circuit of high-impedance state;
Described first order fpga chip is effective by the output of the described output enable control circuit of control, be communicated with described the second nonvolatile memory, and the configuration data of the described second level fpga chip of storing in described the second nonvolatile memory is upgraded, after completing described upgrading, described first order fpga chip controls the output terminal of described output enable control circuit for original state.
7. the collocation method of two-stage fpga chip according to claim 6, is characterized in that, described first order fpga chip, after the upgrading of configuration data that completes described second level fpga chip, is also carried out following steps:
By the dedicated data line with second level fpga chip is connected described in each, indicate second level fpga chip described in each to reload configuration data.
8. the collocation method of two-stage fpga chip according to claim 6, is characterized in that, also comprises following steps:
Described in each, in the fpga chip of the second level, select one in advance, the second level fpga chip of selection is configured to aggressive mode, non-selected all the other second level fpga chips are configured to from pattern;
Before described each second level fpga chip obtains the step of configuration data of self from the second nonvolatile memory, also comprise following steps:
The second level fpga chip of described aggressive mode provides configurable clock generator to described the second nonvolatile memory and described each second level fpga chip from pattern when powering on.
9. the collocation method of two-stage fpga chip according to claim 6, is characterized in that, also comprises following steps:
In the time need to upgrading to the configuration data of described first order fpga chip, described first order fpga chip is upgraded to the configuration data of the described first order fpga chip of storing in described the first nonvolatile memory.
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