CN101771663A - Verification system based on UCPS protocol - Google Patents
Verification system based on UCPS protocol Download PDFInfo
- Publication number
- CN101771663A CN101771663A CN200810208233A CN200810208233A CN101771663A CN 101771663 A CN101771663 A CN 101771663A CN 200810208233 A CN200810208233 A CN 200810208233A CN 200810208233 A CN200810208233 A CN 200810208233A CN 101771663 A CN101771663 A CN 101771663A
- Authority
- CN
- China
- Prior art keywords
- chip
- hdmi
- algorithm
- ucps
- fpga
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Storage Device Security (AREA)
Abstract
The invention discloses a verification system based on a UCPS protocol, which comprises an FPGA chip, an HDMI receiving chip, an HDMI sending chip, an SRAM module, an EEPROM module, an MCU configuration module, a second EEPROM module and a power supply module, wherein the FPGA chip is used for realizing various algorithms of the UCPS protocol, the HDMI receiving chip, the HDMI sending chip, the SRAM module and the EEPROM module are connected with the FPGA chip, and the MCU configuration module and the second EEPROM module are connected with the HDMI sending chip, the FPGA chip and the HDMI sending chip through buses. The invention can lower the development difficulty of the UCPS protocol on the basis of ensuring the speed of the algorithms of the UCPS protocol.
Description
Technical field
The present invention relates to the multimedia field, particularly relate to a kind of UCPS agreement verification system of (Unified ContentProtection System unifies the numerical protection agreement).
Background technology
The principal character of Digital Television is the total digitalization processing of program making, transmission, reception and storage.Abundant in content colorful be the key of Digital Television development.Digital Television has also further strengthened the worry of content supplier for digitized content bringing high-quality audio frequency and video effect to the user when.Content supplier thinks in case the audio-video frequency content digitlization, unwarrantedly duplicates and sells with regard to easier suffering.In fact, no matter be number format or analog format, how protecting the copyright of audio-video frequency content not encroached on, is that film and music dealer make a profit and the matter of utmost importance of surviving.At present,, greatly influenced the enthusiasm and the commercial interest of content supplier, also had influence on the development of Digital Television owing to the illegal use of content.For head it off, adopted transmission means abroad based on HDCP (High-bandwidth Digital Content Protection High-bandwidth Digital Content Protectio) agreement.The HDCP agreement is the audio-video frequency content that is used for protecting on the high frequency interface.From technical elements; famous in the world chip, complete-system vendor have carried out related work; alliance or independent development have been formed; formed the technical specification and the product of some digital TV contents protections, transmitted and received chip as a series of HDMI (high-definition media interface) of HDCP agreement that are with of AD9889, the AD9398 etc. of ADI company.
In view of this, under national audio frequency and video bid committee instructs, set up the UCPS standard group, form the industry technology standard.Target is to set up the Digital Television unified content resist technology standard of independent intellectual property right.
The UCPS agreement is the numerical protection agreement with independent intellectual property right that China proposes, and can be used for the various multimedia equipments of portable multimedia apparatus to high definition DTV (Digital Television).UCPS agreement basic ideas are by to technical specification etc. outside the analysis of all kinds of physical interfaces of digital audio ﹠ video equipment, the comparator; set up unified content resist technology framework at interfaces such as HDMI, DVI, USB, 1394, CI and Displayport; form independent intellectual property right, construct perfect digital TV contents protection system.Therefore, the verification system at the UCPS agreement is that economic worth is arranged very much down to the chip product exploitation.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of verification system based on the UCPS agreement, can reduce the degree of raising difficult questions of UCPS agreement on the basis that guarantees UCPS protocol algorithm speed.
For solving the problems of the technologies described above, the verification system based on the UCPS agreement of the present invention comprises:
One FPGA (Field Programmeble Gate Array field programmable gate array) chip, programmable hardware circuit by FPGA becomes algorithmic system with the software ARM that operates in FPGA inside (high-end Reduced Instruction Set Computer) set of systems, is used to realize the various algorithms of UCPS agreement;
One HDMI receiving chip and connected HDMI interface, the HDMI receiving chip is connected with fpga chip, is used to receive the digital video-audio signal, and sends it to fpga chip;
One HDMI sends chip and connected HDMI interface, and HDMI sends chip and is connected with fpga chip, and the digital video-audio signal after the deciphering that fpga chip is sent is sent to the DTV demonstration through the HDMI interface;
One SRAM module is connected with fpga chip, is used for ARM application cache district, and the data buffer area of enciphering and deciphering algorithm, to solve the problem of FPGA off-capacity;
One EEPROM module is connected with fpga chip, is used to store the HDMI configuration parameter;
One MCU configuration module sends chip by bus with HDMI chip, fpga chip and HDMI and is connected, and is used to dispose the state information of initialization HDMI receiving chip, HDMI transmission chip and fpga chip;
One the 2nd EEPROM module sends chip by bus with HDMI chip, fpga chip and HDMI and is connected, and is used to deposit the expanded display recognition data of key and equipment;
Power module is for each module of described verification system provides power supply.
Because the verification system based on the UCPS agreement of the present invention adopts way of hardware and software combination to realize Digital Television unified content protection system agreement (UCPS agreement).Realize the scheduling of top layer software to each algorithm by the ARM system, the algorithm that operand is big adopts hardware to realize.Way of hardware and software combination has reduced UCPS protocol development difficulty on the basis that guarantees UCPS protocol algorithm speed, obtained good technical effect, and test result proves that verification system of the present invention is feasible fully.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is the complete transmission system schematic that constitutes according to the UCPS agreement;
Fig. 2 is the verification system structure chart based on the UCPS agreement of the present invention;
Fig. 3 is the verification system theory diagram based on the UCPS agreement of the present invention;
Fig. 4 is HDMI signal line wiring main points;
Fig. 5 is the algorithm structure figure of FPGA system;
Fig. 6 is the program flow diagram of ARM system;
Fig. 7 is Vsyn and the Hsyn signal waveform that receives through AD9389;
Fig. 8 is through the UCPS encryption but the image of not deciphering;
The image that reduces after Fig. 9 process UCPS encryption and decryption.
Embodiment
The UCPS agreement is to realize having the secret transmission of audio frequency and video digital content between the legitimate device interface of protection demand, the integrality that the phase related control information of realization digital content transmits between the legitimate device interface, the integrality of maintenance system.
Referring to shown in Figure 1, in the digital television signal transmission, finish the integrality of the device systems of transmission and reception by the UCPS agreement.At first after two equipment were authenticated to be legitimate device mutually, audio-video frequency content slave unit A sent to equipment B by the A2 interface of type X through the B1 of the type X of equipment B interface.The S unit of audio-video frequency content slave unit A sets out, the identification administrative unit of the device A of flowing through, need to judge whether to encrypt, flow to the A2 interface of device A subsequently, transmission medium by the centre is to the B1 interface of equipment B, identification administrative unit by equipment B need to judge whether deciphering, finally arrives the S unit of equipment B.Finished transmission like this according to UCPS actualizing audio-video frequency content.
The UCPS protocol contents comprises:
(1) device authentication: comprise the authentication of the authentication between equipment and its own interfaces, two equipment room interfaces and the authentication of two equipment rooms;
(2) cipher key delivery: comprise that the secret transmission of protected content reaches the complete transmission of the control information relevant with this protected content;
(3) system integrity is safeguarded: comprise generation, checking and the renewal of CRL (CRL).
The protection system that constitutes by the UCPS agreement as can be known, this system needs a pair of encryption and decryption system.The relevant hardware system design encrypts transmission board by two almost completely identical circuit boards and the deciphering dash receiver constitutes.Accordingly, the verification system based on the UCPS agreement of the present invention also constitutes by encrypting transmission board and deciphering dash receiver, as shown in Figure 2.This verification system receives the digital audio-video signal that the HDMI interface by DVD sends out, and after encrypting through the encryption transmission board of verification system, sends to the deciphering dash receiver of verification system by the HDMI interface, and the deciphering back sends to DTV by the HDMI interface and shows.This verification system all is made up of digital circuit, does not contain analog circuit, has both reduced the system design difficulty, is convenient to design and exploitation, has guaranteed systemic-function again.
Referring to shown in Figure 3, described in one embodiment of this invention verification system is by forming with the lower part:
One FPGA (field programmable gate array) chip is selected XC3S5000 type fpga chip in the present embodiment for use, and it is the signal processing core cell of described verification system, and various UCPS protocol algorithm are all finished in this fpga chip.
One HDMI receiving chip and connected HDMI interface, the HDMI receiving chip is connected with fpga chip, is used to receive the digital video-audio signal, and sends it to fpga chip;
One HDMI sends chip and connected HDMI interface, and HDMI sends chip and is connected with fpga chip, and the digital video-audio signal after the deciphering that fpga chip is sent is sent to the DTV demonstration through the HDMI interface.
One SRAM module is connected with fpga chip, is used for ARM application cache district, and the data buffer area of enciphering and deciphering algorithm, to solve the problem of FPGA off-capacity.
One EEPROM module is connected with fpga chip, is used to store the HDMI configuration parameter.
One MCU configuration module sends chip by bus with HDMI chip, fpga chip and HDMI and is connected, and is used to dispose the state information of initialization HDMI receiving chip, HDMI transmission chip and fpga chip.
One the 2nd EEPROM module sends chip by bus with HDMI chip, fpga chip and HDMI and is connected, and is used to deposit the expanded display recognition data (EDID) of key and equipment.
Power module is for each module of described verification system provides power supply.
In described verification system design, power module is that system design is indispensable and vital, and the power consumption of system also is a key index of system design.Not only consider input voltage, output voltage and electric current when selecting power supply, also to think over efficient that the stability, power supply of the total power consumption of system, power supply realizes, power unit to the transient response ability of load variations, Primary Component tolerance and the corresponding power supply ripple that allows to power-supply fluctuation, and heat dissipation problem etc.In verification system of the present invention, need 5 kinds of power supply: 5V, 3.3V, 2.5V, 1.8V, 1.2V altogether.Wherein the 5V power supply is the input power supply of system, and remaining power supply all is to be produced by the 5V power supply.3.3V be the power supply of I/O interface power supply and other chips, 1.2V is the core power of FPGA.3.3V and the 1.2V power is bigger, all adopts high power D C-DC power conversion chip, to improve power-efficient, reduces power consumption and heat.
Need the test signal point in the system debug process for making things convenient for, increase by 8 LED lamps and (be used to verify whether operate as normal of FPGA specially in verification system of the present invention in the debug phase; Be used for the state that indication mechanism is moved in the verification system normal work period) and 30 signal testing points.Described LED lamp and signal testing point all are connected on the vacant I/O interface of FPGA or draw from the vacant I/O interface of FPGA.
Because the HDMI interface can be realized hot plug, so when system design, considered the anti-plug of the antistatic discharge performance of system.Being interfaced at HDMI has increased anti-static precautions and (has received joint to having increased antistatic protection chip CM2021 between the HDMI receiving chip at HDMI between the HDMI main control chip (promptly receiving and send chip); send chip at HDMI and between HDMI transmission joint, increased antistatic protection chip CM2020); the system that can guarantee so can not destroy the stability of system, the anti-interference of enhanced system in the course of the work because of the plug joint.
In described verification system, the HDMI transmission speed can be up to 4G, need think better of for the wiring of 4 pairs of differential lines of HDMI main control chip.The transfer impedance of at first guaranteeing these 4 pairs of differential lines remains on about 50 ohm, differential pair transmission line via hole definitely can not occur (when via hole is meant the design circuit plate when wiring simultaneously, a holding wire need be when two copper layer wirings, need to realize the continuity of same signal between the different Cu layer by beating a via hole) situation, if there is via hole must cause the motional impedance of transmission line to guarantee, its consequence is to cause high frequency radiation serious, and transmission bandwidth descends, even whole system can't normally be moved.Fig. 4 is the HDMI interface of verification system and the wiring of the difference transmission lines between the AD9381 chip (the AD9381 chip is the HDMI receiving chip), because clock (clock) differential lines can't realize connecting up in order, need to realize the atresia wiring around half-turn, other 3 pairs of data (data) differential lines all can connect up in order.
FPGA need receive 24 parallel-by-bit data, and these data frequencys will be up to 165M, and Gao Su single-ended signal like this needs to consider the transmission DYNAMIC REFLECTION PROPERTY of signal, to guarantee the quality of signal transmission.In verification system of the present invention, adopted three kinds of modes to guarantee signal performance:
(1) in signal source end termination 22～56 Ohmic resistances, determined that by emulation mode the resistance of terminating resistor is 33 ohm by circuit design simulation software.The signal source end refers to the data-signal of HDMI receiving chip after deciphering.
(2) signal transmssion line is short as far as possible, and the synchronous signal live width is consistent, and it is isometric substantially that line length keeps, and guarantees the impedance of transmission.
(3) integrality on maintenance stratum in the HW High Way zone guarantees the signal transmission integrity.
FPGA is as the signal processing core cell, and directly key is to the success or failure of system design.And key factor of FPGA Application Design is exactly the power configuration to FPGA, and wherein the use of filter capacitor is again the important indicator of power source performance.Therefore, in the present invention to the filter capacitor of every kind of power supply of FPGA all need to distribute three kinds of 0.1uF, 10uF and 47uF etc., wherein 47uF electric capacity should be tried one's best and be arranged near the FPGA back side, and the power pin of accomplishing each chip as far as possible all disposes a 0.1uF electric capacity, to guarantee the power supply performance of power supply, guarantee that FPGA can normally move.
All algorithms of UCPS agreement all are in the inner realization of FPGA.These algorithms comprise:
(A) software is finished ECVP (elliptic curve verification algorithm) digital verification and ECSP (ellipse curve signature algorithm) digital signature;
(B) software is finished HMAC-256 (256 hash messages are confirmed) hash algorithm;
(C) hardware is realized AES (superencipherment algorithm) and stream enciphering and deciphering algorithm.
Wherein ECVP digital verification and ECSP Digital Signature Algorithm comprise:
(a) software is finished SHA-1 (Secure Hash Algorithm) algorithm;
(b) the software and hardware combining mode is finished the scalar multiplication based on ECC (elliptic curve cipher system);
(c) hardware is realized big digital-to-analogue multiplication algorithm;
(d) hardware is realized the mould algorithm for inversion;
(e) hardware realizes that random number produces algorithm.
And in the HMAC-256 hash algorithm, then comprised the SHA-256 algorithm of realizing by software.
Above described algorithm realize by the hardware circuit of FPGA and the software ARM system that operates in FPGA inside.The algorithmic system structured flowchart of FPGA as shown in Figure 5.
Software ARM system is the scheduling controller of described algorithmic system as the top layer of algorithmic system, finishes the cooperation and the scheduling of all hardware algorithm; Hardware circuit is as the bottom of algorithmic system; Carry out communication by 32 bit data bus and 32 bit address buses between the two.
In software ARM system, each algorithm is dispatched by the C code.The scheduling problem that adopts software view to solve algoritic module can be avoided very complicated state machine occurring by the hardware scheduling of FPGA, reduces the exploitation debugging difficulty.In software ARM system, need the algorithm of operation that HMAC-256 hash algorithm, ECVP digital verification and ECSP digital signature and SHA-1 algorithm (" dot product " and " times point " is the subalgorithm of " scalar is taken advantage of " in Fig. 5, carries out data interaction between " scalar is taken advantage of " and " ECVP and ECSP ") are arranged.The algorithm of being realized by programmable hardware circuit has: big digital-to-analogue multiplication algorithm, mould algorithm for inversion function, random number produce algorithm, AES (128) and stream cipher algorithm.Based on the scalar multiplication of ECC by software ARM system and programmable hardware circuit in conjunction with realization.The register tables of programmable hardware circuit is revised by 32 bus read-write modes by software ARM system, calls algorithm and carries out.
Described programmable hardware circuit comprises:
One Register File (register file) chip by bus and software ARM system communication, is taken advantage of function module, mould inverse function module, random number generation function module, safe transmission module to call big digital-to-analogue.
Big digital-to-analogue is taken advantage of function module, is connected with Register File chip, realizes big digital-to-analogue multiplication algorithm.
Mould inverse function module is connected with Register File chip, realizes the mould algorithm for inversion.
Random number generation function module is connected with Register File chip, realizes that random number produces algorithm.
The safe transmission module is connected with Register File chip, realizes AES (128) and stream cipher algorithm.The input of described safe transmission module is connected input video, audio frequency, clock and control signal with the MDMI receiving chip, and its output sends chip with MDMI and is connected output video, audio frequency, clock and control signal.
In software ARM system the control flow of C program in machine code as shown in Figure 6, detailed process is:
Step 1, ARM power on: all chip solution are removed and are resetted, and enter normal holding state;
Step 2, configuration function: configuration HDMI receives and sends chip;
Step 3, initialization: initialization UCPS protocol transmission register, reception begins synchronously with transmitting terminal;
Step 4, carry out the UCPS protocol authentication, if protocol authentication not by authentication again otherwise carried out for the 5th step.
Step 5, the transfer of data of carrying out: the audio/video flow transmission ends is encrypted, and receiving terminal is decrypted.
The verification system platform is made of verification system, DVD (digital video disk (DVD)), DTV (Digital Television) respectively.PC by RS232 respectively with verification system in encryption plate and deciphering plate communication, with the control verification system and can obtain the running status of current verification system.By oscilloscope can the testing authentication system signal performance.Vsyn and Hsyn signal that Fig. 7 comes out for the detected FPGA that is received by AD9389 of oscilloscope.Signal quality still is extraordinary as can be seen from Figure 7, and the edge is very steep, and signal peak is little, and transitional processes is short.Designed as can be seen system satisfies the hardware designs demand aspect signal transmission performance.
Under the situation that signal meets the demands, begin to test the UCPS agreement, the fixing vision signal that DVD is sent out shows on DTV.Fig. 8 is the image of not deciphering after process UCPS encrypts, and Fig. 9 is through deciphering the image that restores after the UCPS encryption again.Contrast this 2 width of cloth image as can be known, only through encrypting not the image of deciphering be rambling, can't discern at all, Fig. 9 is then very clear, has reduced the DVD image.
Test result shows that the verification system based on the UCPS agreement of the present invention can correctly realize the UCPS protocol algorithm, for realizing that chip-scale provides good Front-end Design, for the development of homemade Digital Television industry plays an important role, also possess good market prospects simultaneously.
Below in conjunction with specific embodiments the present invention is had been described in detail, these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should belong to protection scope of the present invention.
Claims (9)
1. the verification system based on the UCPS agreement is characterized in that, comprising:
One fpga chip becomes algorithmic system by the programmable hardware circuit of FPGA with the software ARM set of systems that operates in FPGA inside, is used to realize the various algorithms of UCPS agreement;
One HDMI receiving chip and connected HDMI interface, the HDMI receiving chip is connected with fpga chip, is used to receive the digital video-audio signal, and sends it to fpga chip;
One HDMI sends chip and connected HDMI interface, and HDMI sends chip and is connected with fpga chip, and the digital video-audio signal after the deciphering that fpga chip is sent is sent to the DTV demonstration through the HDMI interface;
One SRAM module is connected with fpga chip, is used for the data buffer area of buffer memory ARM application program and enciphering and deciphering algorithm;
One EEPROM module is connected with fpga chip, is used to store the HDMI configuration parameter;
One MCU configuration module sends chip by bus with HDMI chip, fpga chip and HDMI and is connected, and is used to dispose the state information of initialization HDMI receiving chip, HDMI transmission chip and fpga chip;
One the 2nd EEPROM module sends chip by bus with HDMI chip, fpga chip and HDMI and is connected, and is used to deposit the expanded display recognition data of key and equipment;
Power module is for each module of described verification system provides power supply.
2. the verification system based on the UCPS agreement as claimed in claim 1 is characterized in that: described power supply comprises: 5V, 3.3V, 2.5V, 1.8V, 1.2V; Wherein the 5V power supply is the input power supply of system, and remaining power supply is all produced by the 5V power supply; 3.3V power supply is the power supply of I/O interface power supply and other chips, 1.2V is the core power of FPGA.
3. the verification system based on the UCPS agreement as claimed in claim 1 is characterized in that: be provided with 8 LED lamps and 30 signal testing points in the described verification system; 8 LED lamps are used to verify whether operate as normal of FPGA in the debug phase, are used for the state of indication mechanism operation in the verification system normal work period; Described LED lamp and signal testing point all are connected on the I/O interface of FPGA or draw from the FPGAI/O interface.
4. the verification system based on the UCPS agreement as claimed in claim 1 is characterized in that: described HDMI receiving chip and HDMI send chip and have 4 pairs of differential signal lines respectively, and the transfer impedance of this differential signal line is 50 ohm.
5. the verification system based on the UCPS agreement as claimed in claim 1 is characterized in that: signal source end termination 22～56 Ohmic resistances of described verification system.
6. the verification system based on the UCPS agreement as claimed in claim 1 is characterized in that: every kind of power supply of powering for FPGA is provided with 0.1 μ F, 10 μ F and three kinds of filter capacitors of 47 μ F, and the power pin of each chip all disposes one 0.1 μ F filter capacitor.
7. the verification system based on the UCPS agreement as claimed in claim 1 is characterized in that:
Described software ARM system is the scheduling controller of described algorithmic system as the top layer of algorithmic system, finishes the cooperation and the scheduling of all hardware algorithm; Hardware circuit is as the bottom of algorithmic system; Carry out communication by 32 bit data bus and 32 bit address buses between the two;
The algorithm of being realized by software ARM system comprises: HMAC-256 hash algorithm, ECVP digital verification and ECSP digital signature and SHA-1 algorithm; In the HMAC-256 hash algorithm, comprised the SHA-256 algorithm of realizing by software; In software ARM system, each algorithm is dispatched by the C code;
The algorithm of being realized by programmable hardware circuit has: big digital-to-analogue multiplication algorithm, mould algorithm for inversion function, random number produce algorithm, AES and stream cipher algorithm;
Based on the scalar multiplication of ECC by software ARM system and programmable hardware circuit in conjunction with realization;
The register tables of programmable hardware circuit is revised by 32 bus read-write modes by software ARM system, calls algorithm and carries out.
8. as claim 1 or 7 described verification systems, it is characterized in that based on the UCPS agreement:
Described programmable hardware circuit comprises:
One Register File chip by bus and software ARM system communication, is taken advantage of function module, mould inverse function module, random number generation function module, safe transmission module to call big digital-to-analogue;
Big digital-to-analogue is taken advantage of function module, is connected with Register File chip, realizes big digital-to-analogue multiplication algorithm;
Mould inverse function module is connected with Register File chip, realizes the mould algorithm for inversion;
Random number generation function module is connected with Register File chip, realizes that random number produces algorithm;
The safe transmission module is connected with Register File chip, realizes AES and stream cipher algorithm; The input of described safe transmission module is connected input video, audio frequency, clock and control signal with the MDMI receiving chip, and its output sends chip with MDMI and is connected output video, audio frequency, clock and control signal.
9. the verification system based on the UCPS agreement as claimed in claim 7 is characterized in that: the detailed process of the various algorithms of control of described C code is: ARM powers on; Configuration function; Initialization; Carry out the UCPS protocol authentication; Carry out transfer of data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810208233 CN101771663B (en) | 2008-12-29 | 2008-12-29 | Verification system based on UCPS protocol |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810208233 CN101771663B (en) | 2008-12-29 | 2008-12-29 | Verification system based on UCPS protocol |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101771663A true CN101771663A (en) | 2010-07-07 |
| CN101771663B CN101771663B (en) | 2013-03-20 |
Family
ID=42504264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810208233 Expired - Fee Related CN101771663B (en) | 2008-12-29 | 2008-12-29 | Verification system based on UCPS protocol |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101771663B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102184158A (en) * | 2011-03-31 | 2011-09-14 | 杭州海康威视数字技术股份有限公司 | Daughter board with two-stage FPGA chip and collocation method of two-stage FPGA chip |
| CN102222032A (en) * | 2011-05-20 | 2011-10-19 | 哈尔滨工业大学 | Device and method for fault injection of 1394 bus |
| CN103632103A (en) * | 2013-06-07 | 2014-03-12 | 中国科学院电子学研究所 | Real-time data safety protecting device and method thereof |
| CN104050068A (en) * | 2014-05-23 | 2014-09-17 | 北京兆易创新科技股份有限公司 | Method and device for debugging FPGA (field programmable gate array) in MCU (microprogrammed control unit) chip |
| CN104184578A (en) * | 2014-07-30 | 2014-12-03 | 山东大学 | FPGA-based elliptic curve scalar multiplication accelerating circuit and algorithm thereof |
| CN105376061A (en) * | 2015-10-10 | 2016-03-02 | 广州慧睿思通信息科技有限公司 | Decryption hardware platform based on FPGA |
| CN111258511A (en) * | 2020-01-10 | 2020-06-09 | 武汉先同科技有限公司 | Implementation method based on HDMI transmission printing protocol |
| CN113010142A (en) * | 2021-03-23 | 2021-06-22 | 广州万协通信息技术有限公司 | Novel pulse node type scalar dot multiplication dual-domain implementation system and method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7562379B2 (en) * | 2003-12-22 | 2009-07-14 | Sony Corporation | Method and system for wireless digital multimedia presentation |
| CN201042042Y (en) * | 2007-03-13 | 2008-03-26 | 四川长虹电器股份有限公司 | Stb |
-
2008
- 2008-12-29 CN CN 200810208233 patent/CN101771663B/en not_active Expired - Fee Related
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102184158B (en) * | 2011-03-31 | 2014-04-23 | 杭州海康威视数字技术股份有限公司 | Daughter board with two-stage FPGA chip and collocation method of two-stage FPGA chip |
| CN102184158A (en) * | 2011-03-31 | 2011-09-14 | 杭州海康威视数字技术股份有限公司 | Daughter board with two-stage FPGA chip and collocation method of two-stage FPGA chip |
| CN102222032A (en) * | 2011-05-20 | 2011-10-19 | 哈尔滨工业大学 | Device and method for fault injection of 1394 bus |
| CN102222032B (en) * | 2011-05-20 | 2013-10-30 | 哈尔滨工业大学 | Fault injection method of fault injection device of 1394 bus |
| CN103632103B (en) * | 2013-06-07 | 2016-08-24 | 中国科学院电子学研究所 | A kind of real time data safety device and method thereof |
| CN103632103A (en) * | 2013-06-07 | 2014-03-12 | 中国科学院电子学研究所 | Real-time data safety protecting device and method thereof |
| CN104050068A (en) * | 2014-05-23 | 2014-09-17 | 北京兆易创新科技股份有限公司 | Method and device for debugging FPGA (field programmable gate array) in MCU (microprogrammed control unit) chip |
| CN104050068B (en) * | 2014-05-23 | 2016-06-15 | 北京兆易创新科技股份有限公司 | The method of FPGA Debugging and device in MCU chip |
| CN104184578A (en) * | 2014-07-30 | 2014-12-03 | 山东大学 | FPGA-based elliptic curve scalar multiplication accelerating circuit and algorithm thereof |
| CN104184578B (en) * | 2014-07-30 | 2017-07-07 | 山东大学 | A kind of Elliptic Curve Scalar Multiplication method accelerating circuit and its algorithm based on FPGA |
| CN105376061A (en) * | 2015-10-10 | 2016-03-02 | 广州慧睿思通信息科技有限公司 | Decryption hardware platform based on FPGA |
| CN105376061B (en) * | 2015-10-10 | 2019-02-01 | 广州慧睿思通信息科技有限公司 | A kind of decryption hardware platform based on FPGA |
| CN111258511A (en) * | 2020-01-10 | 2020-06-09 | 武汉先同科技有限公司 | Implementation method based on HDMI transmission printing protocol |
| CN111258511B (en) * | 2020-01-10 | 2023-05-05 | 武汉先同科技有限公司 | HDMI transmission printing protocol-based implementation method |
| CN113010142A (en) * | 2021-03-23 | 2021-06-22 | 广州万协通信息技术有限公司 | Novel pulse node type scalar dot multiplication dual-domain implementation system and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101771663B (en) | 2013-03-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101771663B (en) | Verification system based on UCPS protocol | |
| US9465961B2 (en) | Methods and circuits for securing proprietary memory transactions | |
| US8195843B2 (en) | HDMI controller circuit for transmitting digital data to compatible audio device using address decoder where values are written to registers of sub-circuits | |
| TWI645292B (en) | Human interface device switch with security function | |
| USRE47119E1 (en) | Enabling/disabling display data channel access to enable/disable high-bandwidth digital content protection | |
| CN103026728A (en) | Mechanism for internal processing of content through partial authentication on secondary channel | |
| DE102018123493A1 (en) | Semiconductor memory device and memory module with the same | |
| US20190361836A1 (en) | Advanced peripheral bus based serial peripheral interface communication device | |
| CN104378649A (en) | Method and system for encrypting video streams in real time through SM1 cryptographic algorithm | |
| US20190362107A1 (en) | Advanced peripheral bus based inter-integrated circuit communication device | |
| CN111770341A (en) | Safe transmission system based on HDMI data line | |
| CN106303298A (en) | A kind of video signal output circuit structure, electronic equipment, terminal and system | |
| CN103702164A (en) | UHD (Ultra High Definition) signal transferring device and network STB (Set Top Box) | |
| US8903086B2 (en) | Enabling/disabling display data channel access to enable/disable high-bandwidth digital content protection | |
| CN206505415U (en) | A kind of encryption authentication device based on PCIE | |
| US10469900B2 (en) | Display apparatus configuring a multi display system and control method thereof | |
| CN107396003A (en) | A kind of DP signal distributors and DP system for delivering | |
| CN203457237U (en) | HDMI-based signal distributor | |
| CN107817477B (en) | A kind of signal source system and implementation method of Radar Displaying Console System | |
| CN103440451A (en) | Electronic system authentication chip based on DES (data encryption standard) | |
| CN103065068B (en) | A kind of encryption method of imprinting file and device | |
| CN106953616A (en) | A kind of digital signal generator | |
| CN102118628B (en) | Compatibility test system for UCPS (unified content protection system) protocol | |
| TWI634775B (en) | Apparatus, system and method for providing clock and data signaling | |
| CN202395895U (en) | Intelligent terminal with digital intelligent interface |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130320 Termination date: 20191229 |