CN1284681A - Method and system for programming of FPGA on PC card without additional ardware - Google Patents

Method and system for programming of FPGA on PC card without additional ardware Download PDF

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CN1284681A
CN1284681A CN 00122754 CN00122754A CN1284681A CN 1284681 A CN1284681 A CN 1284681A CN 00122754 CN00122754 CN 00122754 CN 00122754 A CN00122754 A CN 00122754A CN 1284681 A CN1284681 A CN 1284681A
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fpga
device
eeprom
programming
mux
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CN 00122754
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Chinese (zh)
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CN1203434C (en )
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H·贝尔
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国际商业机器公司
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/5054Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]

Abstract

本发明的概念包括无需对电话进行手动操作而对硬件电子电路进行编程和更新的方法和电路。 Concept of the present invention comprises a phone without the need for manual operation of the electronic circuit programming and hardware updating methods and circuits. 本发明的硬件电路包括一个EEPROM设备(12)和一个FPGA设备(16),该设备可通过一个计算机总线系统和一个连接在所述设备之间的MUX元件(14)而被访问。 The hardware circuit of the present invention comprises an EEPROM device (12) and a FPGA device (16), the device can be connected to a MUX element (14) between the device to be accessed by a computer and a bus system.

Description

无需附加硬件即可对PC卡上的FPGA编程的方法和系统 No additional hardware to program the FPGA on the PC card method and system

本发明涉及对现场可编程门阵列进行编程的领域。 The present invention relates to the field of field programmable gate array programming. 特别涉及在终端用户使用过程中和在所述现场可编程阵列上开发用以实现一些新功能的电路的过程中改进其用途。 Particularly to their use in improving the end user during use and development of new circuits for implementing functions on the field programmable gate array process.

在此缩写为FPGA的现场可编程阵列一般用于实现某些计算功能,这些计算功能运行基本的硬件相关功能,用以控制诸如视屏、打印机、网络卡之类的计算机外设的基本功能。 Abbreviated herein as field programmable gate arrays FPGA's typically used to implement some functions of calculating, computing functions of these basic hardware operation-related functions, to control the basic functions of the computer peripherals such as a video screen, a printer, a network card.

它们还用于需要大量基本算术计算的应用程序中,例如在图形处理应用程序中需要快速执行的乘法和加法操作。 They also require a large number of applications in basic arithmetic, multiplication and addition, for example, in a graphics processing application need to quickly perform the operation.

FPGA被用于实现在大量(达到1百万)内接电路中所实现的计算功能性。 FPGA was used to implement the functionality circuits, connected computing achieved in a large number (up to 1 million). 这么多电路的设计和实现需要一个专用硬件的帮助,例如用Byte BlasterMV硬件设备,它依次与工作站的串联或并联的端口之一相连接,该工作站依次用作具有专用软件工具的开发平台。 Design and implementation of so many circuit requires a dedicated hardware assistance, such as with Byte BlasterMV hardware, which in turn is connected to one of the workstation ports series or in parallel, which in turn is used as a development platform workstation with dedicated software tools.

这如图2所示,其中一个PCI卡18与一个位于PC机外部的外部硬件32相连接。 This is shown in Figure 2, wherein a PCI card 1832 is connected to a unit located outside of the PC external hardware. 一个逻辑电路34用为开发FPGA的配置数据来控制和编程FPGA16,并向FPGA传送在系统启动时总线系统检测PCI卡所需的配置数据。 34 is a logic circuit FPGA configuration data to develop control and programming FPGA16, FPGA transfer bus and the PCI card detection system required configuration data at system startup. 这种现有技术的开发环境需要附加的硬件或被称为PROM的可编程只读存储器设备。 Programmable development environments such prior art requires additional hardware or a read-only memory devices called PROM. 包含新功能的开发模式被传送给位于包括了FPGA的已被开发的PC卡之上的PROM。 Development model includes new features include a PROM located transferred to the top of the PC card has been developed FPGA. 在开发人员的工作站通电之后,PROM控制和执行FPGA的配置。 After the developer workstation power, control and execution configuration PROM FPGA. 然后,在操作的过程中检测FPGA的功能。 Then, the detection function of the FPGA during operation. 如果模式需要进一步更新,则必须使用一个新的PROM,因为用过的PROM不能重写。 If you need further update mode, you must use a new PROM, PROM can not be used because the rewrite.

另外,还可以用缩写为EEPROM的电可擦PROM来代替PROM。 Further, abbreviations may be an electrically erasable PROM EEPROM may be replaced PROM. 它们在进行更新时能够进行重写,但是为了控制对EEPROM的写进程,仍然需要外部硬件。 They can be rewritten while the update, but in order to control the writing process to the EEPROM, still need external hardware.

在开发FPGA功能的过程中,或在一个终端用户由于更新或扩展该卡的功能性而想更换一个包含所述FPGA的PC卡18时,由于任一更新或变换的功能已编入卡中需要进行与该卡有关的手动接入以在后一种情况下用另一个卡来替换这个卡或者在由一个FPGA开发商情况下来至少替换所用的PROM以对FPGA编程。 In the development process of the function FPGA, or an end user since the update or extend the functionality of the card and would like to replace the FPGA 18 comprises a PC card, since any one or updated conversion function is incorporated into the card takes manual access associated with the card in the latter case the card is replaced with another card or down to the FPGA programmed by the developer case where a FPGA with the at least replacing the PROM.

基本上,任何取代更新的新功能在一个FPGA上实现的方式是相同的。 Basically, any means updates and new functionality implemented in a FPGA is the same.

但是,任何对PC卡的手动操作都会引起额外的工作并具有例如由于带给任何敏感区域的静电而毁坏计算机内相连的其它硬件的危险性。 However, any manual operation of the PC card will cause extra work and has, for example due to the electrostatic bring any sensitive area and the risk of destroying other hardware connected to a computer.

因此,本发明的一个目的是提供一种方法和电路,以在终端用户的使用过程中和能够实现所述FPGA的某些新功能的电路的开发过程中改进FPGA的使用。 It is therefore an object of the present invention is to provide a method and circuit to circuit development process some of the new features of the end user during use and can be realized to improve the use of the FPGA in the FPGA.

本发明的这些目的是通过独立权利要求中所述的特征来实现的。 These objects of the present invention is achieved by the independent claims characteristics.

本发明的概念包括无需对电路进行手动操作而对硬件电子电路进行编程和更新的方法和系统。 Concept of the present invention comprises a circuit without a manual operation of programming and updating method and system hardware of an electronic circuit.

依据本发明的基本概念,提出了首先物理连接相关卡上的一个PROM或一个EEPROM设备。 According to the basic concept of the invention, first proposed a PROM or an EEPROM device connected to the relevant physical card. 这个设备被串行访问并向FPGA输入一个串行数据流,当这在FPGA将被通知给计算机的总线系统,例如一条PCI总线和为了能够通过一个常规的设备驱动器而访问该卡的时候这是非常有必要。 This device is accessed serially and FPGA inputs a serial data stream, when this will be notified to the FPGA bus system of a computer, for example, a PCI bus, and the card can be accessed through a conventional device driver, when it is very necessary. 如上所述,FPGA在计算机下一次通电时由PROM自动配置,它表示对将由计算机上的BIOS正确检测的PCI卡的一个请求。 As described above, FPGA when power is automatically configured by a PROM in the computer, it indicates a request for a PCI card by the BIOS on the computer correctly detected.

本发明的硬件电路配置包括一个EEPROM设备和一个FPGA设备,该设备可通过一个计算机总线系统和一个连接在所述设备之间的MUX元件而可被访问。 The hardware circuit configuration of the present invention comprises an EEPROM device and an FPGA device, the device can be a MUX connection between the device and the element may be accessed by a computer and a bus system.

在该电路配置中,所述PROM设备配置来包括用于由所述总线系统正确识别FPGA的控制数据和一个用于通过一个象联合检验活动组(JTAP)那样的EEPROM-FPGA接口对所述EEPROM设备进行编程的逻辑有效电路。 In this circuit configuration, the PROM includes a device configured to identify the control data from the FPGA to the bus system by a correct and for a joint inspection activities through a group such as (JTAP) as the interface to the FPGA-EEPROM EEPROM device programming logic circuit effective. 依据本发明,为了将所述FPGA正确连接到所述总线系统和初始化包括所述EEPROM在内的所述FPGA配置,可控制上述MUX元件来选择所述PROM设备或所述EEPROM设备或所述FPGA设备来从所述设备中读取数据。 According to the invention, for the FPGA properly connected to the system bus and comprises initializing the FPGA configuration including the EEPROM, may be controlling the MUX to select the PROM element device or the FPGA or the EEPROM device device to read data from the device.

上述电路可被用于执行各种FPGA的内容更新,而无需对卡进行物理访问。 The circuit may be used to perform the various updates the FPGA, without requiring physical access to the card. 这是通过如下操作实现的:在第一步,如上所述FPGA以从磁盘接收的模式对EEPROM编程。 This is achieved through the following operation: in a first step, as described above to receive from FPGA disk EEPROM programming mode. 然后,MUX被切换到能够从EEPROM读取数据并按照预定方式将经过编程的开发模式传送给FPGA。 Then, MUX is switched to the data can be read from the EEPROM and be transmitted to a programmed FPGA development model in a predetermined manner. PROM只用于将信息传递给在第一次启动时由BIOS识别PC卡所需的FPGA。 PROM is only used to pass information to the first time required to start recognition by the BIOS PC card FPGA. 因此,本发明的特征在于以双重方式配置FPGA设备,第一种方式用于对所需的磁盘通信进行初始化,而第二种方式用于根据EEPROM的内容进行重新配置。 Accordingly, the present invention is arranged in a double FPGA device, a first embodiment for communication required to initialize the disk, and the second mode for reconfiguration based on the content of the EEPROM.

与现有技术中所拟订的方法相比,依据本发明的方法和电路具有无须对包括FPGA的卡进行物理访问即可对FPGA编程的优点。 Compared with the prior art methods are developed, and a circuit having a method according to the present invention need not to include the advantages of the FPGA programmed FPGA physical access card. 因此,减少了平均的开发时间,降低了成本。 Therefore, reducing the average development time and reduce costs.

而且不需要计算机之外的额外硬件。 And does not require additional hardware other than the computer.

而且,构造一个能够容易地被重新编程以执行一个与以前相比较有扩展功能的通用PC卡是可能的。 Moreover, a structure can easily be re-programmed to perform a phase comparison with previous extensions have general-purpose PC card is possible. 或者说只要需要就可执行一个完全不同的功能是可能的。 Or it can as long as necessary to perform a completely different function is possible. 因此,本发明增加了FPGA硬件的灵活性而不仅限于一个单独的目的。 Accordingly, the present invention increases the flexibility of the FPGA hardware and is not limited to a single purpose.

本发明以实施例的形式进行说明,并且不受限于下述附图,其中:图1是示出了依据本发明最佳实施例的电路的基本元件的结构简图,图2是示出了依据现有技术的电路的基本元件的结构简图,图3是示出了依据本发明第一和第二方面的方法的基本步骤的方框图。 In the form of embodiment of the present invention will be described, and is not limited to the following figures, wherein: FIG. 1 is a schematic diagram illustrating a configuration based on the basic circuit elements of the preferred embodiment of the present invention, FIG 2 is a diagram illustrating based on the basic element structure diagram of the prior art circuit, FIG. 3 is a diagram illustrating the basic steps of the method according to the present invention, the first and second aspects of the block diagram.

下面参照附图,特别是图1,对依据本发明的电路的基本元件进行描述。 Referring to the drawings, in particular FIG. 1, the basic circuit element according to the present invention will be described.

一个PROM10和一个EEPROM12通过一个多路转接器14与位于依据本发明而生成的通用PC卡上的一个FPGA相连。 A PROM10 a EEPROM12 14 and connected to one FPGA according to the invention located on a generic PC card generated by a multiplexer. 图1中用虚线包括的以标记18表示的区域即为该PC卡。 1 by a dotted line in FIG. 18 included in the mark region to the PC card that is indicated. FPGA右侧的40条线作为输入/输出线,表示与计算机PCI总线系统的连接。 FPGA right line 40 as an input / output line, and the PCI bus connected to the computer system.

PROM10和EEPROM12都有一条时钟线和一条数据线分别连接到各自在MUX14的入口。 PROM10 EEPROM12 and has a clock line and a data line connected to a respective inlet of MUX14. 从MUX有一对时钟线和数据线输出到各自在FPGA16的入口。 From MUX has a pair of clock and data lines to the respective outputs of the entrance FPGA16.

可通过一条MUX CTL线来控制MUX元件14,以便在所述线为无效时从PROM10读取数据或在所述线被切换到有效时从EEPROM12中读取数据。 MUX element 14 may be controlled by a line of the CTL MUX to read the data in the line is invalid or read data PROM10 is switched to active in the line from the from EEPROM12.

参照上述所引用的现有技术,为了从FPGA对EEPROM编程,在FPGA16和EEPROM12之间还具有四个连接元件TCK,TDI,TMS和TDO。 Prior art reference cited above, in order for EEPROM programming from the FPGA, and EEPROM12 between FPGA16 further having four connecting elements TCK, TDI, TMS and TDO.

从FPGA16的一个输出到EEPROM12的一个输入还有一条信号线INIT_CONFIG,其操作将在后面予以详述。 EEPROM12 an output to an input of a signal line INIT_CONFIG FPGA16 there from, its operation will be described in detail later.

为了便于作为一个PCI总线合作设备的BIOS在计算机启动时识别FPGA和通过一个设备驱动器访问FPGA,PROM10包括FPGA配置所需的所有配置数据。 To facilitate cooperation as a PCI bus FPGA devices recognized by the BIOS when the computer starts and access FPGA via a device driver, PROM10 FPGA configuration includes all the configuration data needed. 而且,它还包括通过上述JTAG接口对EEPROM12进行编程所需的所有逻辑电路。 Also, it includes all the logic necessary to EEPROM12 programmed via the JTAG interface.

下面将参照图3详细说明对EEPROM和FPGA编程的基本步骤。 3 will now be described in detail with reference to the basic steps of the FPGA programming EEPROM and FIG.

在步骤110进行通电之后,在步骤120利用PROM的内容自动配置FPGA16。 After the step 110 is energized, the use of automatic configuration FPGA16 contents of PROM 120 step. 在BIOS提示之后,FPGA发送表示其存在的信号。 After the prompt BIOS, FPGA transmits a signal indicating its presence. FPGA具有PCI目标设备功能,从而能够与一个设备驱动器进行通信。 FPGA PCI target device having a function to enable communication with a device driver.

在本发明方法的第一方面,将通过上述被重新更新的FPGA开发模式对用于对FPGA编程的EEPROM进行编程,此过程对应于判断130的YES分支。 In a first aspect of the method of the present invention, will be re-updated via the FPGA development mode for FPGA programming EEPROM programming, this process corresponds to the determination YES branch 130. 在步骤140,由任一种现有的设备驱动器从例如一个磁盘中读取该模式,即配置数据,其中模式开发工具对该磁盘进行写操作,在步骤150,通过上述在FPGA中可实现的专用功能,将这些数据编程到EEPROM12中。 In step 140, any of the conventional example, a device driver in the pattern read from the disk, i.e. the configuration data, wherein the pattern development tools disk write operation, at step 150, the above can be implemented in FPGA dedicated function, the data to be programmed in the EEPROM12.

特别是,象现有技术一样,如图1所示使用专门的JTAG信号时钟(TCK),数据输入(TDI),模式选择(TMS)和数据输出(TDO)。 In particular, as in the prior art, as shown in Figure 1 uses a dedicated JTAG clock signal (the TCK), a data input (TDI), Mode Select (TMS) and a data output (TDO). 从而完成对EEPROM的编程。 Thus completing the programming of the EEPROM.

然后通过信号线INIT_CONFIG激活所谓的Card_INIT功能,从而触发利用EEPROM12的内容对FPGA16进行配置的过程。 Called function is then activated via a signal line Card_INIT INIT_CONFIG, thus triggering the process of using the content EEPROM12 FPGA16 configuring. 通过一个在FPGA中实现的功能来控制所述的触发步骤。 Triggering said step of controlling by a function implemented in the FPGA.

特别是,在步骤160,通过MUX CTL线来切换MUX14以使EEPROM12的CLK和DATA线被传送给FPGA16。 In particular, at step 160, via MUX CTL MUX14 is switched so that the line CLK and DATA lines of EEPROM12 transmitted to FPGA16. 当在步骤170真正激活线INIT_CONFIG时,将在步骤180利用EEPROM的内容对FPGA进行配置。 When activated in step 170 the real line INIT_CONFIG, to configure the FPGA at step 180 using the contents of the EEPROM. 从而在步骤190完成FPGA的编程。 In step 190 thereby to complete the programming of the FPGA. 然后能够通过简单重复上述步骤,即可重复执行新更新的模式版本。 Can then by simply repeating the above steps repeatedly performed to update the version of the new pattern.

依据本发明方法的第二方面,EEPROM12已被重新编程。 According to a second aspect of the method of the present invention, EEPROM12 has been reprogrammed. 因此,完成一种新的FPGA配置模式已被包括。 Thus, the FPGA configuration complete, a new model has been included.

在这种情况下,图3所示的方法在步骤110进行启动之后继续在步骤120对所涉及的PROM进行操作,然后以NO分支离开判断130,并继续执行上述步骤160。 In this case, the method shown in FIG. 3, after step 110 continues to boot PROM in step 120 of their operations involved, then the NO branch out of decision 130, step 160 and continue to execute the above.

在上述说明中,已参照特定的实施例对本发明进行了描述,但显然可以在不偏离发明构思和由后面的权利要求限定的保护范围的情况下对本发明进行各种改进和变化。 In the above description, specific embodiments of the present invention has been described with reference to, but it will be apparent that various modifications and variations of the present invention without departing from the spirit and scope of the invention defined by the following claims. 因此,说明书和附图只是用于解释而不用于限定。 Accordingly, the specification and drawings are for explanation and not for limitation.

应当注意本发明的概念是独立于具有FPGA模式开发环境的PC机所利用的总线系统的。 It should be noted that the concept of the present invention is independent of the bus system having a mode FPGA development environment utilized by the PC.

Claims (4)

  1. 1. 1. 一种依据由计算机设备上的开发工具开发的模式,利用配置数据对现场可编程门阵列(FPGA)(16)进行编程的方法,其特征在于该方法包括步骤:由一个设备驱动器从所述计算机设备的一个存储设备中读取(140)所述模式,借助于能够在所述FPGA(16)中实现的专用的功能,将所述模式编程(150)到一个通过MUX元件(14)与所述FPGA(16)相连的EEPROM(12)中,为了能够从所述EEPROM(12)进行读取,将MUX元件(14)切换(160)到所述FPGA(16),以及通过将所述模式从所述EEPROM(12)传送到所述FPGA(16)而触发(170)所述FPGA(16)的配置。 One kind of tools based on the pattern developed on the computer device, with the configuration data of field programmable gate array (FPGA) (16) programming, characterized in that the method comprises the steps of: by one device driver from the computer a storage device reading (140) said pattern by means of specific functions can be implemented in the FPGA (16), the programming mode (150) through the MUX to a member (14) and the said FPGA (16) EEPROM connected (12), in order to enable the EEPROM from the (12) reads the MUX element (14) switch (160) to the FPGA (16), and by the mode transmitting from said EEPROM (12) to the FPGA (16) and the trigger arrangement (170) of the FPGA (16) of.
  2. 2. 2. 一种利用配置数据而使用FPGA(16)的方法,所述配置数据存储在一个EEPROM(12)中,所述EEPROM(12)通过一个MUX元件(14)与所述FPGA(16)相连,其特征在于所述方法包括步骤:控制所述MUX元件(14)以便能够从所述EEPROM(12)读到所述FPGA(16)中,以及通过将所述模式从所述EEPROM(12)传送到所述FPGA(16)而触发所述FPGA(16)的配置。 Utilizing the configuration data to use FPGA (16), the configuration data is stored in an EEPROM (12 is), the EEPROM is connected to the FPGA (16) (12) via a MUX element (14), which wherein said method comprises the steps of: controlling said MUX element (14) so ​​as to be read from the EEPROM (12) of the FPGA (16), and in the mode by transmitting from said EEPROM (12) to the FPGA (16) and arranged to trigger the FPGA (16) of.
  3. 3. 3. 一种硬件电路装置,包括一个PROM设备(10),一个EEPROM设备(12),一个可通过一个计算机总线系统访问的FPGA设备(16)和一个连接在所述设备之间的MUX元件(14),该电路装置的特征在于:所述配置的PROM设备(10)包括控制数据,用于由所述总线系统正确识别所述FPGA(16),和一个逻辑有效电路,用于利用一个EEPROM-FPGA接口对所述EEPROM设备(12)进行编程,为了将所述FPGA(16)正确连接到所述总线系统和初始化包括所述EEPROM(12)在内的所述FPGA(16)配置,可控制所述MUX元件(14)来选择所述PROM设备(10)或所述EEPROM设备(12)或所述FPGA设备(16),以从所述设备中读取数据。 MUX element (14) A hardware circuit arrangement, comprising a PROM device (10), an EEPROM device (12), a FPGA device (16) accessible via a computer system bus and a connection between the device characterized in that the circuit arrangement: the configuration of the PROM device (10) comprises a control data for identifying the FPGA (16) correct the said bus system, and a logic circuit effective for the use of a EEPROM-FPGA the EEPROM interface device (12) for programming the FPGA to the (16) is properly connected to the bus system and initializes the FPGA comprising said EEPROM (12) including (16) configuration, the control said element MUX (14) selecting the PROM device (10) or the EEPROM device (12) or the FPGA device (16), to read data from the device.
  4. 4. 4. 可被一个PC系统总线检测的PC卡,并包括一个依据权利要求3的电路。 PC card can be detected by a PC system bus, and comprising a circuit according to claim 3.
CN 00122754 1999-08-11 2000-08-09 Method and system for programming of FPGA on PC card without additional hardware CN1203434C (en)

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CN1203434C CN1203434C (en) 2005-05-25

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CN100588981C (en) 2007-10-12 2010-02-10 电子科技大学;成都华微电子系统有限公司 On-site programmable gate array duplex selector verification method
CN102184158A (en) * 2011-03-31 2011-09-14 杭州海康威视数字技术股份有限公司 Daughter board with two-stage FPGA chip and collocation method of two-stage FPGA chip
CN102184158B (en) 2011-03-31 2014-04-23 杭州海康威视数字技术股份有限公司 Daughter board with two-stage FPGA chip and collocation method of two-stage FPGA chip
CN103488471A (en) * 2012-06-20 2014-01-01 微软公司 Updating hardware libraries for use by applications on a computer system with an fpga coprocessor
US9298438B2 (en) 2012-06-20 2016-03-29 Microsoft Technology Licensing, Llc Profiling application code to identify code portions for FPGA implementation
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