CN102184158A - Daughter board with two-stage FPGA chip and collocation method of two-stage FPGA chip - Google Patents
Daughter board with two-stage FPGA chip and collocation method of two-stage FPGA chip Download PDFInfo
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- CN102184158A CN102184158A CN2011100816209A CN201110081620A CN102184158A CN 102184158 A CN102184158 A CN 102184158A CN 2011100816209 A CN2011100816209 A CN 2011100816209A CN 201110081620 A CN201110081620 A CN 201110081620A CN 102184158 A CN102184158 A CN 102184158A
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Abstract
The invention relates to the field of video processing, and discloses a daughter board with a two-stage FPGA chip and a collocation method of the two-stage FPGA chip. For the daughter board, during the electrifying process, the first-stage FPGA chip obtains the self configuration data from a first nonvolatile memory so as to finish configuration and initialization; each second-stage FPGA chip obtains the self configuration data from a second nonvolatile memory so as to finish configuration and initialization; and the types and configuration data of all the second-stage FPGA chips are fully the same. Since the nonvolatile memory does not need to be configured for each FPGA chip and a microprocessor does not need to be increased on the daughter board, the daughter board is low in cost and realizes the configuration management of all the FPGA chips in the daughter board conveniently for the CPU system board .
Description
Technical field
The present invention relates to field of video processing, particularly the configuring technical of the fpga chip in the Video processing.
Background technology
The large-size screen monitors control system is generally complicated multifunction system, divides according to functional module: can be divided into video input functional module (as the input of videos such as VGA, HDMI, DVI, BNC, IP network), master control function module (central processor CPU system), output function module (as the output of videos such as DVI, HDMI, VGA) substantially.In modern system design, often each functional module is gone realization with plank independently, then can be divided into tablet, master control borad, output board, can be connected between each plank on the public backboard, communicate the annexation of big each plank of screen controller as shown in Figure 1 with bus (being generally PCIE or network).CPU only is present in master control borad in big screen system, and master control borad is responsible for total system (mainly be input, output board, be referred to as daughter board) control and management, carries out interactive communication by network and remote server simultaneously.Each daughter board mainly is responsible for the processing of video image, and inside is mainly with field programmable gate array (Field Programmable Gate Array, be called for short " FPGA ") chip be responsible for the cutting apart of video image, splicing, stack, convergent-divergent and doubly hardwood handle, in this system, can only carry out data communication by bus between master control borad and each daughter board.
In large-size screen monitors application or monitoring field, because fpga chip has plurality of advantages such as be fit to Video Segmentation, splicing, stack, convergent-divergent, times frame and video output time-delay is little, time-delay consistency is good very much aspect Video processing, therefore be extensive use of in this field.
Fpga chip is when its operate as normal, the configuration data of FPGA is stored in static RAM (Static Random Access Memory, be called for short " SRAM ") in, because SRAM is a volatile memory, fpga chip configuration information after power down will be lost, all require external circuit that configuration data is loaded among the SRAM in the sheet again when so just requiring to power on, FPGA could operate as normal after internal register and I/O initialization were finished at every turn.At present as follows to the allocation plan of FPGA:
A kind of scheme is to join special-purpose nonvolatile memory to every fpga chip, this moment FPGA (Master) equipment of deciding, as long as the configure dedicated pin of FPGA is linked to each other with nonvolatile memory, FPGA can produce the configuration data of configuration sequential reading non-volatile storage automatically to on-chip SRAM when powering on, finish configuration and initialization procedure, usually nonvolatile memory mainly comprises FLASH and EEPROM (Electrically Erasable Programmable Read Only Memo) (Electrically Erasable Programmable ROM is called for short " EEPROM ").
Another kind of scheme is used in containing the system of microprocessor, the FLASH (or EEPROM) of storage FPGA configuration data is generally arranged in this system equally, and directly link to each other with microprocessor.This moment, FPGA did the equipment from (Slave), and microprocessor (Master) equipment of deciding, microprocessor read the FPGA configuration data of FLASH (or EEPROM) and produces the configuration sequential finishes configuration to FPGA.
Yet, the present inventor finds, owing to use the difference of processing capacity and the restriction of cost, the fpga chip that two or more types are often arranged in the daughter board, a kind of is high-end fpga chip, supporting bus directly links to each other with master control borad, and another kind of fpga chip not supporting bus directly links to each other with master control borad.If adopt first kind of allocation plan, need to give each sheet fpga chip all to join a slice nonvolatile memory, cost is higher.Because the configuration data of each fpga chip is stored in separately independently in the nonvolatile memory, master control borad can't carry out unified management and configuration to it, can't carry out remote maintenance.If adopt second kind of allocation plan, need to give every input, output board to increase microprocessor, the configuration management of the fpga chip that goes to realize that all fpga chips or those directly do not link to each other with master control borad with microprocessor then, this microprocessor must support PCIE or network service could realize communicating by letter with master control borad, and this class processor price is generally all very high.
Summary of the invention
The object of the present invention is to provide a kind of with the daughter board of two-stage fpga chip and the collocation method of two-stage fpga chip, with low-cost and realize of the configuration management of cpu system plate easily to all FPGA in the daughter board.
For solving the problems of the technologies described above, embodiments of the present invention provide a kind of daughter board with the two-stage fpga chip, comprise: first nonvolatile memory, second nonvolatile memory, the first order on-site programmable gate array FPGA chip that links to each other with master control borad by bus, the second level fpga chip that at least one does not link to each other with master control borad by bus, the model and the configuration data of each second level fpga chip are identical;
First nonvolatile memory is connected with first order fpga chip, is used to store the configuration data of first order fpga chip;
Second nonvolatile memory is connected with each second level fpga chip, is used to store the configuration data of second level fpga chip;
First order fpga chip is used for when powering on obtaining from first nonvolatile memory configuration data of self, finishes configuration and initialization;
Each second level fpga chip is used for when powering on obtaining from second nonvolatile memory configuration data of self, finishes configuration and initialization.
Embodiments of the present invention also provide a kind of collocation method of two-stage fpga chip, comprise following steps:
When powering on, the first order on-site programmable gate array FPGA chip that links to each other with master control borad by bus, from first nonvolatile memory that this first order fpga chip is connected obtain self configuration data, finish configuration and initialization;
Not each second level fpga chip that links to each other with master control borad by bus from second nonvolatile memory that each second level fpga chip is connected obtain self configuration data, finish configuration and initialization;
Wherein, the model of each second level fpga chip and configuration data are identical.。
Embodiment of the present invention compared with prior art, the key distinction and effect thereof are:
The first order fpga chip that links to each other with master control borad by bus is connected with first nonvolatile memory, each second level fpga chip that links to each other with master control borad by bus is not connected with second nonvolatile memory, and the model and the configuration data of each second level fpga chip are identical.First order fpga chip obtains the configuration data of self from first nonvolatile memory when powering on, and finishes configuration and initialization; Each second level fpga chip obtains the configuration data of self from second nonvolatile memory, finish configuration and initialization.Because all second level fpga chips all are same types, configuration data is also identical, therefore only need to finish the data configuration of all second level fpga chips when powering on smoothly by one second nonvolatile memory, do not need to be equipped with a nonvolatile memory separately for each fpga chip, and need on daughter board, not increase microprocessor, low-cost and realized of the configuration management of cpu system plate easily to all FPGA in the daughter board.
Further, the daughter board of band two-stage fpga chip also comprises the output enable control circuit, first order fpga chip links to each other with the input end of output enable control circuit, and the output terminal of output enable control circuit links to each other with each second level fpga chip with second nonvolatile memory; The output terminal of output enable control circuit is defaulted as high-impedance state.First order fpga chip also is used in the time need upgrading to the configuration data of second level fpga chip, the output of control output enable control circuit is effective, be communicated with second nonvolatile memory, and the configuration data of the second level fpga chip stored in second nonvolatile memory upgraded, after finishing upgrading, first order fpga chip is controlled to be original state (output terminal that is about to the output enable control circuit is controlled to be high-impedance state) with the output terminal of output enable control circuit.By of the control of first order fpga chip to the output channel of output enable control circuit, make first order fpga chip can read and write and wipe the configuration data of second nonvolatile memory, finish the upgrading of the configuration data of second level fpga chip.Owing to can go second level fpga chip is configured data management by first order fpga chip, realized configuration management and the data upgrading of master control borad to all FPGA in the daughter board, therefore all FPGA configuration informations can carry out the network remote renewal by server, and needn't go to the scene to carry out burning or tear chip open, made things convenient for the follow-up maintenance of product.And, take all less, simple and convenient to the logical resource and the I/O mouth of first order fpga chip.
Further, first order fpga chip is after the upgrading of the configuration data of finishing second level fpga chip, can indicate each second level fpga chip to reload configuration data by the dedicated data line that links to each other with each second level fpga chip, thereby realize the online upgrading of fpga chip.
Further, first order fpga chip both can directly link to each other with master control borad by bus, also can link to each other with master control borad through backboard by bus, made the present invention not be subject to the annexation of daughter board and master control borad, possessed application scenarios widely.。
Description of drawings
Fig. 1 is the synoptic diagram according to each plank annexation of big screen controller of the prior art;
Fig. 2 is the structural representation according to the daughter board of the band two-stage fpga chip of first embodiment of the invention;
Fig. 3 is the structural representation according to the daughter board of the band two-stage fpga chip of second embodiment of the invention;
Fig. 4 is the collocation method process flow diagram according to the two-stage fpga chip of third embodiment of the invention.
Embodiment
In the following description, in order to make the reader understand the application better many ins and outs have been proposed.But, persons of ordinary skill in the art may appreciate that even without these ins and outs with based on the many variations and the modification of following each embodiment, also can realize each claim of the application technical scheme required for protection.
For making the purpose, technical solutions and advantages of the present invention clearer, embodiments of the present invention are described in further detail below in conjunction with accompanying drawing.
First embodiment of the invention relates to a kind of daughter board with the two-stage fpga chip.In the present embodiment, cpu system plate (being master control borad) directly links to each other with daughter board by bus, and as shown in Figure 2, bus can be but be not limited to pciE or network-bus.Two kinds of dissimilar fpga chips are arranged in the daughter board: by bus first order fpga chip (being the FPGA0 among Fig. 2) that links to each other with master control borad and the second level fpga chip that does not link to each other with master control borad by bus (being the FPGA1-FPGAn among Fig. 2), the model and the configuration data of each second level fpga chip are identical.Also comprise first nonvolatile memory (being the nonvolatile memory 1 among Fig. 2), second nonvolatile memory (being the nonvolatile memory 2 among Fig. 2) and output enable control circuit in the daughter board.
Wherein, master control borad links to each other with FPGA0 by bus, and FPGA0 is connected with nonvolatile memory 1, and nonvolatile memory 2 is connected with FPGA1-FPGAn.FPGA0 links to each other with the input end of output enable control circuit, and the output terminal of output enable control circuit links to each other with the FPGA1-FPGAn chip with nonvolatile memory 2.The output terminal of output enable control circuit is defaulted as high-impedance state.FPGA0 can be by to the control of output enable control circuit, is communicated with the output channel of self and nonvolatile memory 2, as shown in Figure 2.That is to say, under default situations, the output terminal of output enable control circuit is high-impedance state (it is invalid promptly to export), between FPGA0 and the nonvolatile memory 2 with respect to open circuit, but when needs, it is effective that FPGA0 can control the output of output terminal of output enable control circuit, is communicated with nonvolatile memory 2, and nonvolatile memory 2 is wiped and read-write operation.
Nonvolatile memory 1 is used to store the configuration data of FPGA0 chip.When powering on FPGA0 initiatively the configuration data of reading non-volatile storage 1 in self SRAM, finish configuration and initialization.Nonvolatile memory 2 is used to store the configuration data of FPGA1-FPGAn chip.Because the model and the configuration data of FPGA1-FPGAn chip are identical, so configuration data that is actually a kind of fpga chip of storage in the nonvolatile memory 2, FPGA1-FPGAn obtains the configuration data of self when powering on from nonvolatile memory 2, finishes configuration and initialization.Specifically, in the FPGA1-FPGAn chip, choose one (as the FPGA1 chip) in advance, with the FPGA1 chip configuration is that aggressive mode (Master) all the other (FPGA2-FPGAn chips) all is configured to from pattern (Slave), the FPGA1 chip of aggressive mode provides configurable clock generator to nonvolatile memory 2 and all the other all fpga chips from pattern (FPGA2-FPGAn chip) when powering on, and to nonvolatile memory 2 transmission instruction and FPGA1-FPGAn configuration data address stored in nonvolatile memory 2, nonvolatile memory 2 is after receiving this instruction, according to the address of receiving the FPGA1-FPGAn configuration data is exported, FPGA1-FPGAn receives data by the data line that links to each other with nonvolatile memory 2, get access to the configuration data of self, finish configuration and initialization.Owing to powering on or during operate as normal, the output terminal of output enable control circuit is a high-impedance state, be that FPGA0 and nonvolatile memory 2 paths are for disconnecting, therefore nonvolatile memory 2 can only receive the trigger pip of second level fpga chip, makes second level fpga chip can carry out data configuration smoothly.
In the present embodiment, the first order fpga chip configuration data that also is used for first order fpga chip that first nonvolatile memory is stored is upgraded.That is to say that FPGA0 can receive the instruction read-write non-volatile memory 1 from master control borad during operate as normal, finish the upgrade maintenance of cpu system self configuration data.If desired the configuration data of second level fpga chip is upgraded, it is effective that then first order fpga chip also is used to control the output of output enable control circuit, be communicated with second nonvolatile memory, and the configuration data of the second level fpga chip stored in second nonvolatile memory upgraded, after finishing upgrading, the output terminal of output enable control circuit is controlled to be original state.That is to say, the relevant configuration pin I/O mouth that FPGA0-FPGAn links to each other with the output enable control circuit when operate as normal need be configured to high-impedance state, but FPGA0 can control the output enable circuit when needed and make its output effectively, this moment, FPGA0 just can read and write the configuration data with erasable nonvolatile memory 2, finish the configuration data upgrading of FPGA0-FPGAn, and control output enable circuit makes its output invalid after finishing the data upgrading.When powered on next time, FPGA0-FPGAn can reconfigure according to new configuration data in the nonvolatile memory 2.
Be not difficult to find, in the present embodiment, because all second level fpga chips all are same types, configuration data is also identical, therefore only need to finish the data configuration of all second level fpga chips when powering on smoothly by one second nonvolatile memory, do not need to be that each fpga chip is equipped with a nonvolatile memory separately, and need on daughter board, not increase microprocessor, low-cost and realized of the configuration management of cpu system plate easily to all FPGA in the daughter board.
And, by of the control of first order fpga chip, make first order fpga chip can read and write and wipe the configuration data of second nonvolatile memory to the output channel of output enable control circuit, finish the upgrading of the configuration data of second level fpga chip.Owing to can go second level fpga chip is configured data management by first order fpga chip, realized configuration management and the data upgrading of master control borad to all FPGA in the daughter board, therefore all FPGA configuration informations can carry out the network remote renewal by server, and needn't go to the scene to carry out burning or tear chip open, made things convenient for the follow-up maintenance of product.And, the logical resource of first order fpga chip and I/O mouth are taken all less, if not volatile memory 2 is SPI FLASH (serial communication bus FLASH), the inner SPI controller of configuration that only needs of FPA0, simple and convenient.Because FPGA0-FPGAn adopts Ganged Serial Configuration pattern in the present embodiment, require FPGA1-FPGAn to be necessary for the chip of same model, and duty must be configured to just the same.In order to guarantee correct configuration, the configurable clock generator frequency suitably should be reduced.
In addition, be appreciated that in the present embodiment that first order fpga chip has only one, i.e. FPGA0 chip, but in actual applications, first order fpga chip also can have a plurality of, for each first order fpga chip disposes a nonvolatile memory separately.Any one first order fpga chip wherein as the FPGA0 chip in the present embodiment, is connected the input end that enables control circuit.
Second embodiment of the invention relates to a kind of daughter board with the two-stage fpga chip.Second embodiment and first embodiment are basic identical, and difference mainly is:
In the first embodiment, first order fpga chip directly links to each other with master control borad by bus; And in the present embodiment, first order fpga chip links to each other with master control borad through backboard by bus, as shown in Figure 3.It will be understood by those skilled in the art that backboard is the transmission channel of data, so the function and first embodiment of the annexation of two-stage fpga chip and realization is identical in the present embodiment, does not repeat them here.
Because first order fpga chip both can directly link to each other with master control borad by bus, also can link to each other with master control borad through backboard by bus, made the present invention not be subject to the annexation of daughter board and master control borad, possessed application scenarios widely.
In addition, what deserves to be mentioned is, in the present embodiment, between first order fpga chip and each second level fpga chip, also be provided with dedicated data line, first order fpga chip can be by the dedicated data line that links to each other with each second level fpga chip after the upgrading of the configuration data of finishing second level fpga chip, indicate each second level fpga chip to reload configuration data, thereby realize the online upgrading of fpga chip.
Third embodiment of the invention relates to a kind of collocation method of two-stage fpga chip, and idiographic flow as shown in Figure 4.
In step 410, when powering on, the first order fpga chip that links to each other with master control borad by bus, from first nonvolatile memory that this first order fpga chip is connected obtain self configuration data, finish configuration and initialization.Not each second level fpga chip that links to each other with master control borad by bus from second nonvolatile memory that each second level fpga chip is connected obtain self configuration data, finish configuration and initialization.Wherein, the model of each second level fpga chip and configuration data are identical.
Each second level fpga chip obtains self the mode of configuration data from second nonvolatile memory specific as follows:
In each second level fpga chip, select one in advance, the second level fpga chip of selecting is configured to aggressive mode, non-selected all the other second level fpga chips are configured to from pattern.When powering on, the second level fpga chip of aggressive mode provides configurable clock generator to second nonvolatile memory with respectively from the second level fpga chip of pattern when powering on, and to second nonvolatile memory transmission instruction and second level fpga chip configuration data address stored in second nonvolatile memory, second nonvolatile memory is after receiving this instruction, according to the address of receiving second level fpga chip configuration data is exported, second level fpga chip receives data by the data line that links to each other with second nonvolatile memory, get access to the configuration data of self, finish configuration and initialization.
After first order fpga chip and second level fpga chip are finished configuration and initialization, enter normal operating conditions, enter step 420.
In step 420, in normal operation, first order fpga chip judges whether and need upgrade to configuration data.If first order fpga chip gets access to the instruction that will upgrade to configuration data from the needs of master control borad by bus, then enter step 430; Otherwise return this step.
In step 430, first order fpga chip judges whether the configuration data that need upgrade is the configuration data of first order fpga chip, if, then enter step 440, first order fpga chip is upgraded to the configuration data of the first order fpga chip stored in first nonvolatile memory.If first order fpga chip judges that the configuration data that need upgrade is not the configuration data of first order fpga chip, promptly the configuration data of second level fpga chip need be upgraded, and then enters step 450.
In step 450, first order fpga chip is upgraded to the configuration data of the second level fpga chip stored in second nonvolatile memory.
Specifically, the output of first order fpga chip control output enable control circuit is effective, the input end of this output enable control circuit links to each other with this first order fpga chip, output terminal links to each other with each second level fpga chip with second nonvolatile memory, and output terminal is defaulted as the control circuit of high-impedance state.First order fpga chip is effective by the output of control output enable control circuit, be communicated with second nonvolatile memory, and the configuration data of the second level fpga chip stored in second nonvolatile memory upgraded, after finishing upgrading, first order fpga chip is controlled to be original state with the output terminal of output enable control circuit.When powered on next time, second level fpga chip can reconfigure according to configuration data new in second nonvolatile memory.
Be not difficult to find that present embodiment is and the corresponding method embodiment of first embodiment, present embodiment can with the enforcement of working in coordination of first embodiment.The correlation technique details of mentioning in first embodiment is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in the present embodiment also can be applicable in first embodiment.
Four embodiment of the invention relates to a kind of collocation method of two-stage fpga chip.The 4th embodiment and the 3rd embodiment are basic identical, and difference mainly is:
In the 3rd embodiment, after the configuration data upgrading of finishing second level fpga chip, second level fpga chip is when power on next time, reconfigures according to configuration data new in second nonvolatile memory.
And in the present embodiment, after the configuration data upgrading of finishing second level fpga chip, first order fpga chip also can indicate each second level fpga chip to reload configuration data by the dedicated data line that links to each other with each second level fpga chip, to realize online upgrading.
Be not difficult to find that present embodiment is and the corresponding method embodiment of second embodiment, present embodiment can with the enforcement of working in coordination of second embodiment.The correlation technique details of mentioning in second embodiment is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in the present embodiment also can be applicable in second embodiment.
Need to prove that each method embodiment of the present invention all can be realized in modes such as software, hardware, firmwares.No matter the present invention be with software, hardware, or the firmware mode realize, instruction code can be stored in the storer of computer-accessible of any kind (for example permanent or revisable, volatibility or non-volatile, solid-state or non-solid-state, fixing or removable medium or the like).Equally, storer can for example be programmable logic array (Programmable Array Logic, be called for short " PAL "), random access memory (Random Access Memory, be called for short " RAM "), programmable read only memory (Programmable Read Only Memory, be called for short " PROM "), ROM (read-only memory) (Read-Only Memory, be called for short " ROM "), Electrically Erasable Read Only Memory (Electrically Erasable Programmable ROM, be called for short " EEPROM "), disk, CD, digital versatile disc (Digital Versatile Disc is called for short " DVD ") or the like.
Though by with reference to some preferred embodiment of the present invention, the present invention is illustrated and describes, those of ordinary skill in the art should be understood that and can do various changes to it in the form and details, and without departing from the spirit and scope of the present invention.
Claims (11)
1. daughter board with the two-stage fpga chip, it is characterized in that, comprise: first nonvolatile memory, second nonvolatile memory, the first order on-site programmable gate array FPGA chip that links to each other with master control borad by bus, the second level fpga chip that at least one does not link to each other with master control borad by bus, the model and the configuration data of each described second level fpga chip are identical;
Described first nonvolatile memory is connected with described first order fpga chip, is used to store the configuration data of described first order fpga chip;
Described second nonvolatile memory is connected with each described second level fpga chip, is used to store the configuration data of described second level fpga chip;
Described first order fpga chip is used for obtaining the configuration data of self from described first nonvolatile memory when powering on, and finishes configuration and initialization;
Each described second level fpga chip is used for obtaining the configuration data of self from described second nonvolatile memory when powering on, and finishes configuration and initialization.
2. the daughter board of band two-stage fpga chip according to claim 1, it is characterized in that, the daughter board of described band two-stage fpga chip also comprises the output enable control circuit, described first order fpga chip links to each other with the input end of described output enable control circuit, and the output terminal of described output enable control circuit links to each other with each described second level fpga chip with described second nonvolatile memory; The output terminal of described output enable control circuit is defaulted as high-impedance state;
Described first order fpga chip also is used in the time need upgrading to the configuration data of described second level fpga chip, the output of controlling described output enable control circuit is effective, be communicated with described second nonvolatile memory, and the configuration data of the described second level fpga chip stored in described second nonvolatile memory upgraded, after finishing described upgrading, the output terminal of described output enable control circuit is controlled to be original state.
3. the daughter board of band two-stage fpga chip according to claim 2, it is characterized in that, described first order fpga chip also is used for after the upgrading of the configuration data of finishing described second level fpga chip, by the dedicated data line that links to each other with each described second level fpga chip, indicate each described second level fpga chip to reload configuration data.
4. the daughter board of band two-stage fpga chip according to claim 1 is characterized in that, the described second level fpga chip that the daughter board of described band two-stage fpga chip comprises is greater than one, and one of them second level fpga chip is configured to aggressive mode; All the other second level fpga chips are configured to from pattern;
The second level fpga chip of described aggressive mode is used for providing when powering on configurable clock generator to described second nonvolatile memory and described respectively from the second level fpga chip of pattern.
5. the daughter board of band two-stage fpga chip according to claim 1 is characterized in that, described first order fpga chip also is used for the configuration data of described first order fpga chip that described first nonvolatile memory is stored and upgrades.
6. the daughter board of band two-stage fpga chip according to claim 1 is characterized in that, described first order fpga chip directly links to each other with described master control borad by bus, and perhaps, described first order fpga chip links to each other with described master control borad through backboard by bus.
7. the collocation method of a two-stage fpga chip is characterized in that, comprises following steps:
When powering on, the first order on-site programmable gate array FPGA chip that links to each other with master control borad by bus, from first nonvolatile memory that this first order fpga chip is connected obtain self configuration data, finish configuration and initialization;
Not each second level fpga chip that links to each other with master control borad by bus from second nonvolatile memory that each described second level fpga chip is connected obtain self configuration data, finish configuration and initialization;
Wherein, the model and the configuration data of each described second level fpga chip are identical.
8. the collocation method of two-stage fpga chip according to claim 7 is characterized in that, also comprises following steps:
In the time need upgrading to the configuration data of described second level fpga chip, the output of described first order fpga chip control output enable control circuit is effective, the input end of described output enable control circuit links to each other with this first order fpga chip, output terminal links to each other with each described second level fpga chip with described second nonvolatile memory, and output terminal is defaulted as the control circuit of high-impedance state;
Described first order fpga chip is effective by the output of the described output enable control circuit of control, be communicated with described second nonvolatile memory, and the configuration data of the described second level fpga chip stored in described second nonvolatile memory upgraded, after finishing described upgrading, described first order fpga chip is controlled to be original state with the output terminal of described output enable control circuit.
9. the collocation method of two-stage fpga chip according to claim 8 is characterized in that, described first order fpga chip is also carried out following steps after the upgrading of the configuration data of finishing described second level fpga chip:
By the dedicated data line that links to each other with each described second level fpga chip, indicate each described second level fpga chip to reload configuration data.
10. the collocation method of two-stage fpga chip according to claim 7 is characterized in that, also comprises following steps:
In each described second level fpga chip, select one in advance, the second level fpga chip of selecting is configured to aggressive mode, non-selected all the other second level fpga chips are configured to from pattern;
Described each second level fpga chip obtains the step of configuration data of self from second nonvolatile memory before, also comprise following steps:
The second level fpga chip of described aggressive mode provides configurable clock generator to described second nonvolatile memory and described respectively from the second level fpga chip of pattern when powering on.
11. the collocation method of two-stage fpga chip according to claim 7 is characterized in that, also comprises following steps:
In the time need upgrading to the configuration data of described first order fpga chip, described first order fpga chip is upgraded to the configuration data of the described first order fpga chip stored in described first nonvolatile memory.
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| CN105808290A (en) * | 2016-03-02 | 2016-07-27 | 中国科学院自动化研究所 | Remote dynamic updating system and method for multi-FPGA complete machine systems |
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