CN1622155A - Method for controlling multiple resolution plasma display screen driver - Google Patents
Method for controlling multiple resolution plasma display screen driver Download PDFInfo
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- CN1622155A CN1622155A CNA2004100931438A CN200410093143A CN1622155A CN 1622155 A CN1622155 A CN 1622155A CN A2004100931438 A CNA2004100931438 A CN A2004100931438A CN 200410093143 A CN200410093143 A CN 200410093143A CN 1622155 A CN1622155 A CN 1622155A
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Abstract
The method of controlling multiple resolution ACPDP display screen driver belongs to the field of ACPDP display screen driver controlling technology. The control circuit consists of monochip computer, thumbwheel switch, Flash EEPROM, FPGA control circuit, the first SDRAM and the second SDRAM. The method includes the following operation steps: initializing the monochip computer, reading the set state of the thumbwheel switch and selecting the FPGA configuring logic data stored in the Flash EEPROM; selecting the thumbwheel switch set FPGA configuring logic datan of address section and reading the FPGA configuring logic data; configuring the FPGA control circuit based on the standard FPGA configuration time sequence; and stopping the monochip computer, outputting digital logic control signal from the FPGA control circuit to control the ACPDP display screen driver while writing and displaying two SDRAM's alternately.
Description
Technical field
The present invention relates to a kind of multiple resolution plasma panel of control that is applicable to, it is the method for ACPDP display driver, especially refer to a kind of method that is applicable to the multiple resolution A CPDP driver of control, belong to the technical field of ACPDP display driver control method based on the FPGA technology.
Background technology
The ACPDP display screen is as follow-on large screen flat plate display, have that screen is big, in light weight, body is thin, volume is little, brightness is high, the life-span is long, flicker free, the visual angle is big, response is fast, undistorted, information capacity is big, sharpness is high, the nonlinear compensation ability by force, have memory function and physical strength advantages of higher, performance that it is superior and feasibility to obtain the generally acknowledged of industry.The structure of ACPDP display screen and luminescence mechanism are open in European patent EP 0762373A2, just no longer repeat here.
ACPDP display screen Circuits System mainly comprises following three parts:
1. interface circuit
Interface circuit is used for to various signal sources provide the interface, the VGA signal of signal source index standard, NTSC, the TV signal of standards such as PAL, S-Video signal etc.It mainly comprises: wideband amplification circuit, A/D translation circuit, standard transformation circuit.Interface circuit can become to be suitable for the digital signal that ACPDP display screen Circuits System is used with various conversion of signals, as the data rgb signal of 8bit*3, control signal: Dot Clock (DCLK), vertical synchronization (VSYNC), horizontal synchronization (HSYNC), blanking (BLANK).
2. driver control circuit
Driver control circuit is used for the required data of processes and displays, the function complexity, and interface is numerous, and circuit scale is big, is the core of whole ACPDP display screen Circuits System.The needed control signal of whole ACPDP display driver all produces thus.In the product of existing ACPDP display screen Circuits System, driver control circuit includes the special IC (ASIC) the MB87E701 of the PD4801A of multi-disc such as Pioneer Electronic Corp. and Fuji Tsu.
3.ACPDP display driver
The ACPDP display driver can become the data-switching of Transistor-Transistor Logic level high-tension output signal, and provides pulse voltage timing, periodic and electric current to colored ACPDP display.High-voltage drive has two groups: first group is the addressing driver of processes and displays data, its main effect is to receive the viewdata signal of being sent here by driver control circuit in address period, be transformed into suitable voltage signal, being added to addressing electrode line by line gets on, discharge with the scanning negative pulse acting in conjunction of Y electrode, form the wall electric charge, finish the addressing process; Second group is the line driver of being responsible for writing fashionable scanning and keeping discharge.
Background technology has following shortcoming because of adopting special IC to cause: because of the restriction that is subjected to the special IC source with can not substitute with discrete component, the maintenance of ACPDP display screen Circuits System product is very difficult; One group of special IC can only with a kind of ACPDP display drive circuit coupling of resolution specification, even the ACPDP display screen of the same type of same company, as long as the resolution difference, the special IC of use is just different, versatility is poor; The present output of ACPDP display screen is little, causes the production cost of special IC high.
Summary of the invention
The technical problem to be solved in the present invention is to propose a kind of method that is applicable to the multiple resolution A CPDP display driver of control.This method has highly versatile, and is applied widely, helps standardization, is convenient to advantages such as product maintenance detection.
This method needs to work in following ACPDP display driver control circuit.This control circuit can be controlled the ACPDP display driver of four kinds of resolution, comprise single-chip microcomputer 1, toggle switch 2, FLASH EEPROM 3, FPGA control circuit 4, the one SDRAM 5 and the 2nd SDRAM 6, single-chip microcomputer 1 is for there being 8 single-chip microcomputers of online download function, toggle switch 2 is the selector switch of four condition, resolution selection mode according to the ACPDP display screen of coupling, 00,01,10 and 11 respectively with resolution 640 * 480,852 * 480,1280 * 768 and 1920 * 1080 correspondences, FLASH EEPROM 3 is a high-capacity flash memory, FLASH EEPROM 3 internal memories contain the required configuration logic data of FPGA control circuit 4, FPGA control circuit 4 is field programmable logic integrated circuit, the one SDRAM 5 and the 2nd SDRAM 6 are the synchronous dynamic random access memories that can store a frame picture data respectively, circuit connects, toggle switch 2 is connected with single-chip microcomputer 1 by data line, FLASH EEPROM 3 passes through data line, address wire, control line is connected with single-chip microcomputer 1, single-chip microcomputer 1 passes through data line, address wire, control line is connected with FPGA control circuit 4, and a SDRAM 5 and the 2nd SDRAM 6 pass through data line respectively, address wire, control line is connected with FPGA control circuit 4.This control circuit is connected with interface circuit 8 with data line by the input end of FPGA control circuit 4; This control circuit is connected with ACPDP display driver 7 with data line, control line by the output terminal of FPGA control circuit 4.External image signal interface circuit 8 is sent to the input end of FPGA control circuit 4, and the control signal of FPGA control circuit 4 outputs is sent to ACPDP display driver 7 through the output terminal of FPGA control circuit 4.
Now be described with reference to the accompanying drawings technical scheme of the present invention.A kind of method that is applicable to the multiple resolution plasma display screen driver of control is characterized in that, comprises following operation steps:
First step toggle switch 2 pushes the position of corresponding resolution, single-chip microcomputer 1 initialization according to the specification of the ACPDP exploration on display resolution ratio of coupling;
The second step single-chip microcomputer 1 reads the state that is provided with of toggle switch 2, according to read the pairing resolution of state select to be stored in corresponding FPGA configuration logic data among the FLASH EEPROM 3;
Store four sections different FPGA configuration logic data among the 3rd step FLASH EEPROM 3, be stored in four different address sections, single-chip microcomputer 1 is chosen the FPGA configuration logic data of the address section of toggle switch 2 settings, and reads this FPGA configuration logic data;
Ordered pair FPGA control circuit 4 was configured when the 4th step, single-chip microcomputer 1 was according to the configuration of FPGA standard;
The 5th step single-chip microcomputer 1 is stopped running, be configured according to the resource of the FPGA configuration logic data that write by FPGA control circuit 4 its inside, output Digital Logic control signal, control ACPDP display driver 7, meanwhile, the one SDRAM 5 and the 2nd SDRAM 6 work in an alternating manner: when the data of external image signal write a SDRAM 5, another frame image data that writes on the 2nd SDRAM 6 then is processed into the ACPDP display screen by FPGA control circuit 4 and shows required data, send into the ACPDP display drive circuit, on the ACPDP display screen, show corresponding image, then, the data of external image signal write the 2nd SDRAM 6, show the frame image data of a SDRAM 5 on the ACPDP display screen.
The principle of work of the inventive method is as follows:
Use 1 pair of FPGA control circuit 4 of single-chip microcomputer to be configured, make it to control the ACPDP display driver 7 of multiple resolution.Because the control signal difference that the ACPDP display driver 7 of different resolution is required, thereby to make same FPGA integrated circuit be applicable to the ACPDP display driver 7 of multiple resolution, just must change the configuration logic data of FPGA control circuit 7, to produce different driver control signals.Method of the present invention in high-capacity FLASH EEPROM 3 flash memories, is selected corresponding configuration logic data by single-chip microcomputer 1 according to the resolution that toggle switch 2 is provided with different configuration logic data storage.For the ACPDP display driver 7 of certain resolution, this FPGA integrated circuit just can be according to the control signal of corresponding configuration logic data output corresponding to this resolution A CPDP display driver 7.
Compare with background technology, the invention has the beneficial effects as follows:
1. the polylith special IC is substituted by a programmable integrated circuit, single-chip microcomputer, toggle switch, a FLASHEEPROM and two synchronous dynamic random access memories, because above-mentioned components and parts are the universal product, be easy to obtain, simplified circuit structure, reduced production cost, be convenient to the maintenance of ACPDP display screen Circuits System product and replace, removed the narrow restriction of special IC range of application.
2. only need be provided with simply, just can realize ACPDP display driver, expand the versatility of general-purpose device greatly, reach the effect that an integrated circuit is used more with same programmable integrated circuit control different resolution by toggle switch.
Description of drawings
Fig. 1 is the structured flowchart of ACPDP display screen Circuits System.
Fig. 2 is that wherein 1 is single-chip microcomputer by the structured flowchart of the ACPDP display driver control circuit of method work of the present invention, the 2nd, and toggle switch, the 3rd, FLASH EEPROM, the 4th, the FPGA control circuit, 5 is SDRAM, 6 is the 2nd SDRAM, the 7th, and ACPDP display driver, the 8th, interface circuit.
Fig. 3 is the workflow diagram of single-chip microcomputer 1.
Embodiment
Embodiment 1
Present embodiment will be that 852 * 480 ACPDP display screen is that example further specifies method of the present invention with resolution.
By the used device of the control circuit of method work of the present invention: the model of FPGA control circuit 4 is the Virtex-II of XILINX company series of X C2V3000; The one SDRAM 5 and the 2nd SDRAM 6 are that two identical, memory capacity are the synchronous dynamic random access memory of 128Mbit, and their model is HY57V283220T; The model of single-chip microcomputer 1 is the 89LV51RD2 of PHILIPS company; FLASH EEPROM 3 is high-capacity flash memories, and its capacity and model are respectively 16Mbit and SST39VF016.
The course of work of present embodiment:
First step toggle switch 2 pushes 00 position, single-chip microcomputer 1 (89LV51RD2) initialization according to the specification 852 * 480 of the ACPDP exploration on display resolution ratio of coupling;
The state that is provided with 00 of second toggle switch 2 that read of step single-chip microcomputer 1 (89LV51RD2), according to read state 00 pairing resolution 852 * 480 select to be stored in the FPGA configuration logic data of 00000H-7FFFFH address section among the FLASH EEPROM 3 (SST39VF016);
The 3rd step single-chip microcomputer 1 (89LV51RD2) reads the FPGA configuration logic data of 00000H-7FFFFH address section among the FLASH EEPROM 3 (SST39VF016);
The 4th step single-chip microcomputer 1 (89LV51RD2) during according to the configuration of FPGA standard ordered pair FPGA control circuit 4 (XC2V3000) be configured;
The 5th step single-chip microcomputer 1 (89LV51RD2) is stopped running, be configured according to the resource of the FPGA configuration logic data that write by FPGA control circuit 4 (XC2V3000) its inside, output Digital Logic control signal, control ACPDP display driver 7, meanwhile, the one SDRAM 5 (HY57V283220T) and the 2nd SDRAM6 (HY57V283220T) alternation in the following manner: when the data of external image signal write a SDRAM5 (HY57V283220T), another frame picture data that writes on the 2nd SDRAM6 (HY57V283220T) then is processed into the ACPDP display screen by FPGA control circuit 4 (XC2V3000) and shows required data, send into the ACPDP display drive circuit, on the ACPDP display screen, show corresponding image, then, the data of external image signal write the 2nd SDRAM6 (HY57V283220T), show the frame picture data of a SDRAM5 (HY57V283220T) on the ACPDP display screen.
Embodiment 2
Present embodiment will be that 640 * 480 ACPDP display screen is that example further specifies method of the present invention with resolution.
The used device of control circuit by method work of the present invention: identical with the appropriate section of embodiment 1.
The course of work of present embodiment:
First step toggle switch 2 pushes 01 position, single-chip microcomputer 1 (89LV51RD2) initialization according to the specification 640 * 480 of the ACPDP exploration on display resolution ratio of coupling;
The state that is provided with 01 of second toggle switch 2 that read of step single-chip microcomputer 1 (89LV51RD2), according to read state 01 pairing resolution 640 * 480 select to be stored in the FPGA configuration logic data of 80000H-FFFFFH address section among the FLASH EEPROM 3 (SST39VF016);
The 3rd step single-chip microcomputer 1 (89LV51RD2) reads the FPGA configuration logic data of 80000H-FFFFFH address section among the FLASH EEPROM 3 (SST39VF016);
Fourth, fifth step is identical with fourth, fifth step of embodiment 1.
Embodiment 3
Present embodiment will be that 1280 * 768 ACPDP display screen is that example further specifies method of the present invention with resolution.
The used device of control circuit by method work of the present invention: identical with the appropriate section of embodiment 1.
The course of work of present embodiment:
First step toggle switch 2 pushes 10 position, single-chip microcomputer 1 (89LV51RD2) initialization according to the specification 1280 * 768 of the ACPDP exploration on display resolution ratio of coupling;
The state that is provided with 10 of second toggle switch 2 that read of step single-chip microcomputer 1 (89LV51RD2), according to read state 10 pairing resolution 1280 * 768 select to be stored in the FPGA configuration logic data of 100000H-17FFFH address section among the FLASH EEPROM 3 (SST39VF016);
The 3rd step single-chip microcomputer 1 (89LV51RD2) reads the FPGA configuration logic data of 100000H-17FFFH address section among the FLASH EEPROM 3 (SST39VF016);
Fourth, fifth step is identical with fourth, fifth step of embodiment 1.
Embodiment 4
Present embodiment will be that 1920 * 1080 ACPDP display screen is that example further specifies method of the present invention with resolution.
The used device of control circuit by method work of the present invention: identical with the appropriate section of embodiment 1.
The course of work of present embodiment:
First step toggle switch 2 pushes 11 position, single-chip microcomputer 1 (89LV51RD2) initialization according to the specification 1920 * 1080 of the ACPDP exploration on display resolution ratio of coupling;
The state that is provided with 11 of second toggle switch 2 that read of step single-chip microcomputer 1 (89LV51RD2), according to read state 11 pairing resolution 1920 * 1080 select to be stored in the FPGA configuration logic data of 180000H-1FFFFFH address section among the FLASH EEPROM 3 (SST39VF016);
The 3rd step single-chip microcomputer 1 (89LV51RD2) reads the FPGA configuration logic data of 180000H-1FFFFFH address section among the FLASH EEPROM 3 (SST39VF016);
Fourth, fifth step is identical with fourth, fifth step of embodiment 1.
Claims (1)
1. a method that is applicable to the multiple resolution plasma display screen driver of control is characterized in that, comprises following operation steps:
First step toggle switch 2 pushes the position of corresponding resolution, single-chip microcomputer 1 initialization according to the specification of the ACPDP exploration on display resolution ratio of coupling;
The state that is provided with of the second step toggle switch 2 that read of single-chip microcomputer 1, according to read the pairing resolution of state select to be stored in corresponding FPGA configuration logic data among the FLASH EEPROM 3;
Store four sections different FPGA configuration logic data among the 3rd step FLASH EEPROM 3, be stored in four different address sections, single-chip microcomputer 1 is chosen the FPGA configuration logic data of the address section of toggle switch 2 settings, and reads this FPGA configuration logic data;
Ordered pair FPGA control circuit 4 was configured when the 4th step, single-chip microcomputer 1 was according to the configuration of FPGA standard;
The 5th step single-chip microcomputer 1 is stopped running, be configured according to the resource of the FPGA configuration logic data that write by FPGA control circuit 4 its inside, output Digital Logic control signal, control ACPDP display driver 7, meanwhile, the one SDRAM 5 and the 2nd SDRAM 6 work in an alternating manner: when the data of external image signal write a SDRAM 5, another frame image data that writes on the 2nd SDRAM6 then is processed into the ACPDP display screen by FPGA control circuit 4 and shows required data, send into the ACPDP display drive circuit, on the ACPDP display screen, show corresponding image, then, the data of external image signal write the 2nd SDRAM 6, show the frame image data of a SDRAM 5 on the ACPDP display screen.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100931438A CN100356426C (en) | 2004-12-17 | 2004-12-17 | Method for controlling multiple resolution plasma display screen driver |
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| CNB2004100931438A CN100356426C (en) | 2004-12-17 | 2004-12-17 | Method for controlling multiple resolution plasma display screen driver |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101079100B (en) * | 2006-12-14 | 2010-05-12 | 华东师范大学 | Hardware circuit for implementing image smoothing process in fingerprint identification system |
| CN101329842B (en) * | 2007-06-22 | 2011-06-15 | 深圳创维－Rgb电子有限公司 | Liquid crystal display capable of correcting GAMA of display screen and method for making the same |
| CN102110423A (en) * | 2009-12-28 | 2011-06-29 | 乐金显示有限公司 | Liquid crystal display and method for initializing field programmable gate array |
| CN102184158A (en) * | 2011-03-31 | 2011-09-14 | 杭州海康威视数字技术股份有限公司 | Daughter board with two-stage FPGA chip and collocation method of two-stage FPGA chip |
| CN105242749A (en) * | 2015-09-07 | 2016-01-13 | 深圳微步信息股份有限公司 | Mainboard of all-in-one computer, all-in-one computer, and resolution adjustment method |
| CN113012631A (en) * | 2021-01-12 | 2021-06-22 | 深圳市思坦科技有限公司 | Control system and method for Micro-LED |
| CN113781944A (en) * | 2021-08-19 | 2021-12-10 | 瑞芯微电子股份有限公司 | Method and device for supporting different display screens by same hardware display interface |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN2208249Y (en) * | 1994-09-08 | 1995-09-20 | 沈新 | VAT calculater |
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2004
- 2004-12-17 CN CNB2004100931438A patent/CN100356426C/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101079100B (en) * | 2006-12-14 | 2010-05-12 | 华东师范大学 | Hardware circuit for implementing image smoothing process in fingerprint identification system |
| CN101329842B (en) * | 2007-06-22 | 2011-06-15 | 深圳创维－Rgb电子有限公司 | Liquid crystal display capable of correcting GAMA of display screen and method for making the same |
| CN102110423A (en) * | 2009-12-28 | 2011-06-29 | 乐金显示有限公司 | Liquid crystal display and method for initializing field programmable gate array |
| CN102110423B (en) * | 2009-12-28 | 2013-02-13 | 乐金显示有限公司 | Liquid crystal display and method for initializing field programmable gate array |
| CN102184158A (en) * | 2011-03-31 | 2011-09-14 | 杭州海康威视数字技术股份有限公司 | Daughter board with two-stage FPGA chip and collocation method of two-stage FPGA chip |
| CN102184158B (en) * | 2011-03-31 | 2014-04-23 | 杭州海康威视数字技术股份有限公司 | Daughter board with two-stage FPGA chip and collocation method of two-stage FPGA chip |
| CN105242749A (en) * | 2015-09-07 | 2016-01-13 | 深圳微步信息股份有限公司 | Mainboard of all-in-one computer, all-in-one computer, and resolution adjustment method |
| CN113012631A (en) * | 2021-01-12 | 2021-06-22 | 深圳市思坦科技有限公司 | Control system and method for Micro-LED |
| CN113012631B (en) * | 2021-01-12 | 2023-08-18 | 深圳市思坦科技有限公司 | Control system and method for Micro-LED |
| CN113781944A (en) * | 2021-08-19 | 2021-12-10 | 瑞芯微电子股份有限公司 | Method and device for supporting different display screens by same hardware display interface |
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| CN100356426C (en) | 2007-12-19 |
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