JPH10240678A - Extension input/output bus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To select the optimum number of registers in accordance with the operation speed of a processor and to efficiently operate a system by selecting one of outputs from a configuration signal generation part and supplying it to a field programmable gate array(FPGA). SOLUTION: A selector 6 and a configuration ROM 7 are connected to a FPGA 3. The selector 6 is controlled by a signal which a selection control part 8 outputs. The FPGA 3 operates as a first-in first-out memory constituted of N-pieces of registers 5 which a configuration signal D designates. The output signal of the selection control part 8 decides the output of the configuration signal D for designating the number of the registers. The selection control part 8 is constituted of a decoder for receiving the operation speed P of the processor and changing the signal into the control signal of the selector 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an extended input / output bus widely used in personal computers and the like.

[0002]

2. Description of the Related Art A personal computer has a general-purpose extended input / output bus in order to provide expandability. In order to realize a function desired by the user, original hardware is connected to the extended input / output bus. The configuration of such an extended input / output bus differs depending on the design of the personal computer, and the hardware connected to the extended input / output bus is selected according to the design of the personal computer. The extended input / output bus includes an I / O register system, a shared memory system, and a FIFO (first-in first-out memory) system.

[0003] The I / O register system is a system for transmitting and receiving data using a register of an interface, and is realized with the most basic configuration. However, since data is accessed in units of one word and transmission / reception is performed while handshaking between a master processor and a slave processor which transmit / receive data via the input / output bus, the processor having a low operating speed may be used. Affected,
It degrades the performance of fast processors.

In the shared memory system, a master processor and a slave processor read and write a shared memory at a unique timing. Therefore, they can operate independently of each other, and there is an effect that a fast CPU is not affected by a slow CPU. However, a personal computer having an architecture capable of taking a large address space is sufficient, but there are many personal computers which cannot have a wide address space because of the extended input / output bus, and there is no versatility. In addition, depending on the operating system, there are many restrictions on the address space, and it is sometimes difficult to employ the address space.

[0005] In the FIFO system, data is exchanged using a first-in first-out memory, and the master processor and the slave processor can operate independently, as in the shared memory system. Also, similar to the I / O register method,
The address space may be small, and there is an advantage that a large amount of data can be transmitted regardless of the hardware connected to the extended input / output bus. In view of the above, the FIFO method has conventionally been widely used as an extended input / output bus of a personal computer.

[0006]

However, the above-mentioned conventional extended input / output bus has the following problems to be solved. However, if the extended I / O bus is formed of a first-in first-out memory having a large number of registers, when a relatively small amount of data is written at the entrance, it takes a long time to read the first data from the exit.
That is, when the operation speed of the processor that reads data is low, the data access speed is low.

On the other hand, if the extended input / output bus is constituted by a first-in first-out memory having a small number of registers, when the speed of a processor that writes data to a register is lower than the speed of a processor that reads data, the processor on the reading side waits, and the performance is reduced. Is reduced. The number of registers may be selected by carefully considering the number of registers in consideration of the speed of the processor, but that is not versatile. Conversely, in order to provide versatility, it is conceivable to prepare a board on which both a first-in first-out memory having a large number of registers and a small first-in-first-out memory are mounted. However, this has a problem that the cost increases because the board size and the number of components increase.

[0008]

The present invention employs the following structure to solve the above problems. <Structure 1> A first-in first-out memory for temporarily storing transfer data among a plurality of processors, wherein the first-in first-out memory has an arbitrary number specified by a configuration signal supplied from the outside. A plurality of configuration signal generators, each of which is constituted by a field programmable gate array that operates by forming a circuit in which the registers are connected to each other, and specifies that a different number of registers are to be connected, and outputs of these configuration signal generators A selector for selecting any one of the above and supplying the selector to the field programmable gate array.

<Structure 2> In structure 1, the selector includes:
An extended input / output bus characterized in that a selection operation is controlled by a control signal corresponding to an operation speed of a processor connected via a first-in first-out memory.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below using specific examples. FIG. 1 is a block diagram of an extended input / output bus according to the present invention. In the figure, a master processor 1 is connected to an internal bus 2. The internal bus 2 has an FPG
The slave processor 4 is connected via A (field programmable gate array). This FPGA
The extended input / output bus of the present invention is configured including the peripheral circuit 3 and peripheral circuits for controlling the same. A selector 6 and a configuration ROM 7 are connected to the FPGA 3. Further, the selector 6 is configured to be controlled by a signal output from the selection control unit 8.

The FPGA 3 can be operated as various circuits by supplying a configuration signal D from the outside, as is well known in the art. This is constituted by an LSI (high density integrated circuit) or the like. Here, a plurality of configuration signals are output so that several types of configuration signals can be output.
An OM (read only memory) 7 is provided.
All of these outputs are input to the selector 6, and the selector 6 outputs any of the configuration ROs.
The output of M7 is supplied to FPGA3. The operation of the FIFO I / O bus will be described with reference to FIG.

FIG. 2 is an explanatory diagram of a FIFO I / O bus. As shown in the figure, a master processor 1 is connected to an internal bus 2, and a slave processor 4 is connected to the internal bus 2 via a FIFO 9. In such a conventional general I / O bus, the slave processor 4
When data is written to FO9, master processor 1
Reading is performed in order from the data written first, and the data is processed. The FIFO 9 is configured by connecting a plurality of registers 5. When the slave processor 4 writes data, it follows the instruction of the write pointer of the FIFO 9, and when the master processor 1 reads data, it follows the instruction of the read pointer. In such an operation, assuming that the slave processor 4 has written one piece of data, the master processor 1 sequentially increments the read pointer and retrieves the data until new data is found in order to read the data. Therefore, if the number of registers is very large, there is a possibility that the time until the master processor 1 retrieves data becomes long. When the operation speed of the master processor 1 is low, the number of registers cannot be set too large.

On the other hand, the slave processor 4
If the number of registers is too small when data is written to the memory, the data is immediately full. Therefore, the slave processor 4 waits for data writing until the master processor 1 reads data. Conversely, when the data writing speed of the slave processor 4 is low, the master processor 1 waits for reading until data is written. That is, if the number of registers is small, FI
The buffer effect of the FO 9 is reduced. From such a relationship, it is the extended input / output bus of the present invention shown in FIG. 1 that allows the number of registers to be freely set in consideration of the operation speed and the like of the master processor.

The FPGA 3 of FIG. 1 operates as a first-in first-out memory composed of N registers 5 specified by the configuration signal D. The output of the selection control unit 8 determines the configuration signal for specifying the number of registers. For example, the selection control unit 8 is configured by a decoder or the like that receives the operation speed P of the processor and changes the signal into a control signal of the selector 6. Further, the selection control section 8 is constituted by a dip switch or the like, and can select an appropriate number of registers manually. Further, it may be configured by a register or the like that receives an appropriate selection control signal from the master CPU or the like and supplies the signal to the selector 6.

The extended input / output bus of the present invention having the above configuration is used as follows. FIG. 3 is a diagram for explaining the operation of the extended input / output bus of the present invention. (A), (b),
(C) shows a state in which configuration signals D1, D2, and D3 having different contents are supplied to the FPGA 3 shown in FIG. (A) is a case where the configuration signal D1 is supplied, and operates as a FIFO consisting of 32 registers. (B) shows that F is supplied by supplying the configuration signal D2.
PGA3 operates as a FIFO consisting of 64 registers. (C) shows the configuration signal D3
Is supplied, the FPGA 3 operates as a FIFO composed of 256 registers. As described above, if the configuration signal is selected in consideration of the operation speed of the processor and the like, the FPGA 3 can be freely switched to a FIFO having a different number of registers.

Note that the timing of such switching may be any time after the power of the apparatus is turned on. Various circuits are reset when the power is turned on. In this operation, the number of registers may be determined.

[0017]

The extended input / output bus of the present invention described above enables the FPGA to operate as a first-in first-out memory having various numbers of registers in response to requests. The number can be selected to operate the system efficiently. Also,
Since the number of registers can be freely changed by a control signal, the versatility is high. Moreover, F with different numbers of registers
As compared with the case where several types of IFOs are mounted on a board, the number of parts can be reduced as a whole and the board size can be reduced. Therefore, a sufficiently low-cost extended input / output register can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of an extended input / output bus of the present invention.

FIG. 2 is an explanatory diagram of a FIFO I / O bus.

FIG. 3 is an operation explanatory diagram of the present invention.

[Explanation of symbols]

Reference Signs List 1 master processor 2 internal bus 3 FPGA (field programmable gate array) 4 slave processor 5 register 6 selector 7 configuration ROM (configuration signal generation unit) 8 selection control unit D configuration signal

Claims (2)

[Claims] 1. A first-in, first-out memory for temporarily holding transfer data between a plurality of processors, wherein the first-in, first-out memory is an arbitrary one specified by an externally supplied configuration signal. A plurality of configuration signal generators, each of which is constituted by a field programmable gate array that operates by forming a circuit in which a number of registers are connected, and specifies a plurality of registers to be connected, respectively; A selector for selecting one of the outputs and supplying the selected output to the field programmable gate array. 2. The extended input / output bus according to claim 1, wherein the selector is controlled in selection operation by a control signal corresponding to an operation speed of a processor connected via a first-in first-out memory.