CN204028891U - A kind of dsp chip reads the circuit of two panels A/D chip data continuously - Google Patents
A kind of dsp chip reads the circuit of two panels A/D chip data continuously Download PDFInfo
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- CN204028891U CN204028891U CN201420429052.6U CN201420429052U CN204028891U CN 204028891 U CN204028891 U CN 204028891U CN 201420429052 U CN201420429052 U CN 201420429052U CN 204028891 U CN204028891 U CN 204028891U
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Abstract
The utility model discloses the circuit that a kind of dsp chip reads two panels A/D chip data continuously, comprise CPU, described CPU is connected with dsp chip, and described dsp chip is connected with the first A/D converter and the second A/D converter; Also comprise chip selection signal automatic switching circuit.The utility model is realized when dsp chip reads two panels A/D chip data continuously by the hardware circuit based on counter, complete the automatic replacing of two panels A/D chip chip selection signal, therefore the utility model no longer needs CPU to participate in changing the chip chip selection signal read when carrying out AD reading, by dMAX technology, can process again after the enough data of disposable reading, drastically increase the utilization factor of CPU and the work efficiency of complete machine.The utility model can be widely used in the circuit field that dsp chip reads two panels A/D chip data continuously.
Description
Technical field
The utility model relates to the technology that dsp chip reads A/D chip data, particularly relates to the circuit that a kind of dsp chip reads two panels A/D chip data continuously.
Background technology
Present dsp chip especially TI produce TMS320C672x series, all there is special data-moving controller, carrying out internal data space, between peripheral hardware, when carrying out exchanges data between peripheral hardware and internal memory, do not need the participation of CPU.During two panels A/D chip external for dsp chip (as AD7606), just need take two addresses or adopt two chip selection signals, after the reading and writing data of a chip, just need to change the chip chip selection signal read, TMS320C672x asynchronous read and write address space is very limited, only has 12 bit address lines, if during external jumbo SRAM, when reading the data of AD7606 again, chip selection signal can only be expanded with GPIO interface.When carrying out timing sampling, in Interruption, the configuration that AD data will revise GPIO port register is read in circulation, need the participation of CPU, waste the time of CPU, for high-speed AD, this mode is flagrant, and the efficiency of dsp chip computing also can be caused greatly to reduce, and can not play its track performance better.
TMS320C672x chip has dMAX(Dual Data Movement Accelerator, Double Data moves accelerator), internal storage can be realized by dMAX, peripheral hardware, data-moving between external memory storage, the concurrence performance of two passages, by dMAX controller, cross exchange matrix completes automatically, substantially increases the efficiency of reading and writing data.Therefore a efficient circuit of necessary design, the result of disposable reading AD conversion, and data conversion storage in internal memory, when data reach the capacity of needs, then transfer to the CPU of dsp chip to process, accelerate the speed of dsp chip process.
Utility model content
In order to solve the problems of the technologies described above, the purpose of this utility model is to provide and a kind ofly realizes the circuit that dsp chip reads two panels A/D chip data continuously.
The technical scheme that the utility model adopts is:
Dsp chip reads a circuit for two panels A/D chip data continuously, comprises CPU, and described CPU is connected with dsp chip, and described dsp chip is connected with the first A/D converter and the second A/D converter;
Also comprise chip selection signal automatic switching circuit;
Described chip selection signal automatic switching circuit comprises first or door, second or door, not gate, counter, non-inverting buffer and resistance;
First or the output terminal of door be connected to the chip selection signal input pin of the first A/D converter;
Second or the output terminal of door be connected to the chip selection signal input pin of the second A/D converter;
First or an input end of door be connected with the output terminal of counter, first or another input end of door be connected with the A/D converter chip selection signal output pin of CPU;
The output terminal of counter connects an input end of second or door by not gate, second or another input end of door be connected with the A/D converter chip selection signal output pin of CPU;
The conversion starting signal input pin of the clear input of counter, the first A/D converter and the second A/D converter is all connected with the A/D converter sampled signal output terminal of dsp chip;
The read signal input pin of the input end of non-inverting buffer, the first A/D converter and the second A/D converter is all connected with the A/D converter read signal output terminal of dsp chip;
The output enable control end of non-inverting buffer connects the A/D converter chip selection signal output pin of CPU;
The input end of clock of the output terminal linkage counter of non-inverting buffer;
The output terminal of non-inverting buffer is connected with power supply by resistance.
Further, this circuit also comprises bus transceiver, described first A/D converter is connected the data input pin of bus transceiver with the data output of the second A/D converter, the data output end of described bus transceiver connects dsp chip, and the Enable Pin of described bus transceiver connects the output terminal of non-inverting buffer.
Further, counter is 7,4HC,393 tetra-digit counter.
Further, the first A/D converter is AD7606.
Further, the second A/D converter is AD7606.
Further, non-inverting buffer is 74VHC125 No. tetra-impact damper.
Further, bus transceiver is 74LVC16245.
The beneficial effects of the utility model are: a kind of dsp chip of the present utility model reads the circuit of two panels A/D chip data continuously, realized when dsp chip reads two panels A/D chip data continuously by the hardware circuit based on counter, complete the automatic replacing of two panels A/D chip chip selection signal, therefore the utility model no longer needs CPU to participate in changing the chip chip selection signal read when carrying out AD reading, by dMAX technology, can process again after the enough data of disposable reading, drastically increase the utilization factor of CPU and the work efficiency of complete machine.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, embodiment of the present utility model is described further:
Fig. 1 is the circuit embodiments structured flowchart that a kind of dsp chip of the utility model reads two panels A/D chip data continuously;
Fig. 2 is the working timing figure of four digit counter 74HC393.
In accompanying drawing, the list of parts representated by each label is as follows:
1, chip selection signal automatic switching circuit, D1, first or door, D2, second or door, D3, not gate, T1, counter, T2, non-inverting buffer, R, resistance, T3, bus transceiver, U1, the first A/D converter, U2, the first A/D converter.
Embodiment
Be described principle of the present utility model and feature below in conjunction with accompanying drawing, example, only for explaining the utility model, is not intended to limit scope of the present utility model.
Dsp chip reads a circuit for two panels A/D chip data continuously, comprises CPU, and CPU is connected with dsp chip, and dsp chip is connected with the first A/D converter and the second A/D converter, also comprises chip selection signal automatic switching circuit and bus transceiver.
Fig. 1 is the circuit embodiments structured flowchart that a kind of dsp chip of the utility model reads two panels A/D chip data continuously; As shown in Figure 1: chip selection signal automatic switching circuit 1 comprises first or door D1, second or door D2, not gate D3, counter T1, non-inverting buffer T2; The present embodiment Counter T1 adopts 7,4HC,393 tetra-digit counter, and the first A/D converter U1 and the second AD converter U2 all adopts AD7606 chip, and non-inverting buffer T2 adopts 74VHC125 No. tetra-impact damper, and bus transceiver T3 adopts 74LVC16245.
In chip selection signal automatic switching circuit 1 first or the input end of door D1 be connected with the output terminal of counter T1, another input end is connected with the A/D converter chip selection signal output pin of CPU, first or the output terminal of door D1 be connected to the chip selection signal input pin of the first A/D converter U1, for the first A/D converter U1 provides chip selection signal nCS1.The output terminal of counter T1 connects an input end of second or door D2 by a not gate D3, second or another input end of door D2 be connected with the A/D converter chip selection signal output pin of CPU, second or the output terminal of door D2 be connected to the chip selection signal input pin of the second A/D converter U2, for the second A/D converter U2 provides chip selection signal nCS2.The conversion starting signal input pin of the clear input CLR of counter T1, the first A/D converter and the second A/D converter is all connected with the A/D converter sampled signal output terminal of dsp chip; The input end of non-inverting buffer T2, the read signal input pin of the first A/D converter U1 and the second A/D converter U2 are all connected respectively with the A/D converter read signal output terminal of dsp chip; The output enable control end of non-inverting buffer T2 connects the A/D converter chip selection signal output pin of CPU; The input end of clock CLK of the output terminal linkage counter T1 of non-inverting buffer T2; The output terminal of non-inverting buffer T2 is connected with power supply by resistance R; First A/D converter U1 is connected the input data terminal of bus transceiver T3 with the data output of the second A/D converter U2, and the data output end of bus transceiver T3 connects dsp chip, and the Enable Pin of bus transceiver T3 connects the output terminal of non-inverting buffer T2.
AD7606 is the modulus data acquisition chip that Analog Device company produces, 74HC393 is two 4 binary counters, for the course of work of the present utility model is described, first brief introduction is carried out to the work schedule of A/D converter AD7606 part signal and 74HC393 below.
CONVST (A, B) signal of AD7606: each AD7606 chip has two to change startup pin, and for receiving two-way CONVST signal (CONVST A, CONVST B), during this two pin short circuits, 8 passages of AD7606 are changed simultaneously.NCS signal: AD7606 sheet selects the signal on pin, Low level effective; NRD signal: the signal on AD7606 read signal pin, Low level effective; NRD signal is exported by the A/D converter read signal output terminal of dsp chip; When nCS and nRD is low simultaneously, can enable parallel data bus line, transformation result appears on D0-D15 data line.NBUSY signal: after CONVST signal arrives rising edge, it is high that nBUSY pin becomes logic, represents that transfer process starts, and remains height, until all passages all convert; The negative edge of nBUSY represents that data are just latching to output register, waits to be output.Because other signals of AD7606 are not in this discussion scope, ignore.
Fig. 2 is the working timing figure of four digit counter 74HC393, as shown in Figure 2, when the CLK clock count value of 74HC393 is less than 8, and Q
dexport as low, after continuous counter 8 data, Q
dreversion becomes high level.
Below the course of work of the present utility model is described.
CONVST signal i.e. sampled signal, CONVST signal is exported by the A/D converter sampled signal output terminal of dsp chip, be sent to A/D converter conversion and start pin, can timing sampling, also can synchronized sampling, be the square wave of one-period, choose the synchronous sampling signal of method as two panels AD of 20.48KHZ in the present embodiment.CONVST rising edge, starts sampling.Because AD is by having sampled conversion, namely maximumly only have 4.15uS switching time (i.e. nBUSY, is uprised by low, then step-down, namely switching time), therefore, the sampling rate of 20.48KHZ, when CONVST negative edge, has converted certainly.
CONVST signal, as the input signal of the clear terminal CLR of four digit counters, when CONVST is in high level, when being namely in conversion, resets counter 74HC393, the Q of U1
a-Q
dexport as low; If when now CPU reads AD continuously by IO mode, then the IO address decoding of CPU generates nCS, the A/D converter chip selection signal output pin of CPU exports nCS signal, nCS signal, as the input signal of the output enable control end of non-inverting buffer, only has when nCS signal is low, and the nRD signal being connected to the input end of non-inverting buffer just can put on the CLK pin of 74HC393, often read a nRD, then 74HC393 counting adds 1, when first AD7606 is run through 8 data, and Q
dexport high level, through anti-phase, with nCS phase or, then can choose second AD7606.
Convert the event trigger pin that signal sends to dsp chip, cause dMAX operation, so just pass through the I/O interface of CPU to the disposable reading of two A/D chip.Especially by the dsp chip (TMS320C674x series) of EDMA type, or by dMAX (TMS320C6720x), by peripheral manager, automatically form data-moving, and do not need CPU to participate in, drastically increase the work efficiency of complete machine.
The utility model improvement is on the basis of available circuit, add newly-designed chip selection signal automatic switching circuit, is realized the automatic replacing of two panels A/D chip chip selection signal, do not relate to the improvement of software or method by hardware circuit.
Adopting circuit described in the utility model no longer to need the participation of CPU when carrying out AD reading, by dMAX technology, can process again after the enough data of disposable reading, drastically increasing the utilization factor of CPU.
More than that better enforcement of the present utility model is illustrated, but the utility model is created and is not limited to described embodiment, those of ordinary skill in the art also can make all equivalent variations or replacement under the prerequisite without prejudice to the utility model spirit, and these equivalent distortion or replacement are all included in the application's claim limited range.
Claims (7)
1. dsp chip reads a circuit for two panels A/D chip data continuously, comprises CPU, and described CPU is connected with dsp chip, and described dsp chip is connected with the first A/D converter (U1) and the second A/D converter (U2); It is characterized in that:
Also comprise chip selection signal automatic switching circuit (1);
Described chip selection signal automatic switching circuit (1) comprises first or door (D1), second or door (D2), not gate (D3), counter (T1), non-inverting buffer (T2) and resistance (R);
First or the output terminal of door (D1) be connected to the chip selection signal input pin of the first A/D converter (U1);
Second or the output terminal of door (D2) be connected to the chip selection signal input pin of the second A/D converter (U2);
First or an input end of door (D1) be connected with the output terminal of counter (T1), first or another input end of door (D1) be connected with the A/D converter chip selection signal output pin of CPU;
The output terminal of counter (T1) connects an input end of second or door (D2) by not gate (D3), second or another input end of door (D2) be connected with the A/D converter chip selection signal output pin of CPU;
The conversion starting signal input pin of the clear input of counter (T1), the first A/D converter (U1) and the second A/D converter (U2) is all connected with the A/D converter sampled signal output terminal of dsp chip;
The read signal input pin of the input end of non-inverting buffer (T2), the first A/D converter (U1) and the second A/D converter (U2) is all connected with the A/D converter read signal output terminal of dsp chip;
The output enable control end of non-inverting buffer (T2) connects the A/D converter chip selection signal output pin of CPU;
The input end of clock of the output terminal linkage counter (T1) of non-inverting buffer (T2);
The output terminal of non-inverting buffer (T2) is connected with power supply by resistance (R).
2. a kind of dsp chip reads the circuit of two panels A/D chip data continuously according to claim 1, it is characterized in that: this circuit also comprises bus transceiver (T3), described first A/D converter (U1) is connected the data input pin of bus transceiver (T3) with the data output of the second A/D converter (U2), the data output end of described bus transceiver (T3) connects dsp chip, and the Enable Pin of described bus transceiver (T3) connects the output terminal of non-inverting buffer (T2).
3. a kind of dsp chip reads the circuit of two panels A/D chip data continuously according to claim 1, it is characterized in that: described counter (T1) is 7,4HC,393 tetra-digit counter.
4. according to claim 1 or 2, a kind of dsp chip reads the circuit of two panels A/D chip data continuously, it is characterized in that: described first A/D converter (U1) is AD7606.
5. according to claim 1 or 2, a kind of dsp chip reads the circuit of two panels A/D chip data continuously, it is characterized in that: described second A/D converter (U2) is AD7606.
6. a kind of dsp chip reads the circuit of two panels A/D chip data continuously according to claim 1, it is characterized in that: described non-inverting buffer (T2) is 74VHC125 No. tetra-impact damper.
7. a kind of dsp chip reads the circuit of two panels A/D chip data continuously according to claim 2, it is characterized in that: described bus transceiver (T3) is 74LVC16245.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420429052.6U CN204028891U (en) | 2014-07-31 | 2014-07-31 | A kind of dsp chip reads the circuit of two panels A/D chip data continuously |
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| CN201420429052.6U CN204028891U (en) | 2014-07-31 | 2014-07-31 | A kind of dsp chip reads the circuit of two panels A/D chip data continuously |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106254061A (en) * | 2016-08-14 | 2016-12-21 | 北京数盾信息科技有限公司 | A kind of express network storage encipher-decipher method |
| CN111562899A (en) * | 2020-06-23 | 2020-08-21 | 福州大学 | Circuit of novel division method |
-
2014
- 2014-07-31 CN CN201420429052.6U patent/CN204028891U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106254061A (en) * | 2016-08-14 | 2016-12-21 | 北京数盾信息科技有限公司 | A kind of express network storage encipher-decipher method |
| CN106254061B (en) * | 2016-08-14 | 2019-08-23 | 北京数盾信息科技有限公司 | A kind of high speed network storage encipher-decipher method |
| CN111562899A (en) * | 2020-06-23 | 2020-08-21 | 福州大学 | Circuit of novel division method |
| CN111562899B (en) * | 2020-06-23 | 2024-06-04 | 福州大学 | Novel division circuit |
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Granted publication date: 20141217 Termination date: 20180731 |
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| CF01 | Termination of patent right due to non-payment of annual fee |