Utility model content
The purpose of this utility model is to provide a kind of microcontroller and its low-power consumption EEPROM interface circuit, with solution
State the problem of being proposed in background technology.
To achieve the above object, the utility model provides following technical scheme：
A kind of microcontroller and its low-power consumption EEPROM interface circuit, including clock module, eeprom memory, EEPROM
Interface control module, code options module and microcontroller core, the microcontroller core connect respectively clock module and
Eeprom memory, clock module are also connected with eeprom memory, and eeprom memory is also respectively connected with memory and code choosing
As further scheme of the present utility model：The EEPROM interface control module include 3 delays time to control units,
Two phase inverters and two and door.
Compared with prior art, the beneficial effects of the utility model are：The utility model manages mould by EEPROM interface
Block carries out the reading SECO of low-power consumption to eeprom memory, the power consumption of eeprom memory can be saved, so that micro-control
Device chip processed is applied to low-power consumption application requirement.The utility model can also be by changing delays time to control list in microcontroller chip
The delays time to control information of member, scheme is applied to the EEPROM of different type and different performance design object, have suitable
With property it is wide, it is practical the advantages of.
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the embodiment of the utility model is carried out
Clearly and completely describing, it is clear that described embodiment is only the utility model part of the embodiment, rather than whole
Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not under the premise of creative work is made
The every other embodiment obtained, belong to the scope of the utility model protection.
Referring to Fig. 1-2, the utility model describes a kind of microcontroller and its low-power consumption EEPROM interface circuit, including when
Clock module, eeprom memory, EEPROM interface control module, code options module and microcontroller core, the microcontroller
Device kernel connects clock module and eeprom memory respectively, and clock module is also connected with eeprom memory, eeprom memory
It is also respectively connected with memory and code options module.
EEPROM interface control module includes 3 delays time to control units, two phase inverters and two and door.
The operation principle of this programme:As shown in Figure 1.Microcontroller includes clock module (CLOCK), EEPROM is stored
Device, EEPROM interface control module (EEPROM_INTF), code options module (OPTION), microcontroller core (MCU_
CORE).Clock module (CLOCK) is responsible for producing the work clock required for chip operation.When microcontroller core asks to read
It is stored in EEPROM corresponding to a certain address during content, the effective EEPROM that reads of microcontroller core (MCU_CORE) output please
Signal (e2c_rd) is sought, while exports corresponding reading address signal (e2c_adr).When EEPROM interface control modules
(EEPROM_INTF) when detecting effective reading EEPROM request signals (e2c_rd), will produce needed for EEPROM memories
Low-power consumption interface sequence, the value of appropriate address unit is read back from EEPROM, and the value read back (e2c_din) is conveyed
To microcontroller core (MCU_CORE).Code options module (OPTION) is responsible for configuration of overall importance to chip and is controlled.
In the design, these configuration control information of overall importance include being used for each delay control in control chip in EEPROM interface modules
The delays time to control information (dly_ctrl1, dly_ctrl2, dly_ctrl3) of unit processed.
When EEPROM interface control module (EEPROM_INTF) is responsible for the interface needed for regulation management reading eeprom memory
Sequence.The temporal model that EEPROM interface control module reads EEPROM is as shown in Figure 2.E2c_cs is the gating of eeprom memory
Signal；E2c_rd is EEPROM read request pulse signals；E2c_adr is EEPROM read request address signals；E2c_dout is
EEPROM reads return data signal.When reading EEPROM, interface sequence has to the gating signal (e2c_ for meeting eeprom memory
Cs) relative to EEPROM read requests pulse signal (e2c_rd) settling time requirement, while also to meet EEPROM store
The gating signal (e2c_cs) of device relative to the retention time of EEPROM read requests pulse signal (e2c_rd) timing requirements.Read
Eeprom memory operation is related to three kinds of power consumption modes of EEPROM storages.When the gating signal of eeprom memory is low electricity
During level state (e2c_cs=0), eeprom memory is in standby patterns.When the gating signal of eeprom memory is height
Effective status (e2c_cs=1) and when EEPROM read requests pulse signal is low level state (e2c_rd=1), EEPROM is deposited
Reservoir is in read patterns.When the gating signal of eeprom memory is read to ask for high effective status (e2c_cs=1) and EEPROM
When to seek pulse signal be low level state (e2c_rd=0), eeprom memory is in static patterns.Different IP providers
The eeprom memory of offer has difference in power consumption, performance.When EEPROM is in standby patterns, power consumption is minimum.
The power consumption of static patterns is bigger than standby pattern, smaller than read mode power consumption.In microcontroller chip design, in order to
Be advantageous to the design of Digital Logic in chip, the dutycycle of microcontroller core work clock (clk_core) is generally 50%.
, can be by the gating of eeprom memory when microcontroller is in running status in the design of in general microcontroller chip
Signal always remains as high effective status, while uses microcontroller core work clock (clk_core) to read to ask as EEPROM
Seek pulse signal (e2c_rd).In this design, when microcontroller is in running status, eeprom memory alternating
The read pattern higher in power consumption and static patterns.
The design principle of EEPROM interface control module is as shown in Figure 2.EEPROM interface management module is according to code options
Delays time to control information (dly_ctrl1, dly_ctrl2, the dly_ for the delays time to control unit that module (OPTION) transmits
Ctrl3) the output delay to delay unit in EEPROM interface control module (EEPROM_INTF) is controlled.Microcontroller
Core clock clk_core exports a time delayed signal clk_core_ after delays time to control unit 1 (DELAY_CELL_1)
Dly1, a time delayed signal clk_core_dly1 are dly1 relative to microcontroller core clock clk_core delay time,
Can be that dly1 regulates and controls to delay time by delays time to control information (dly_ctrl1).Time delayed signal clk_core_
Dly1 exports secondary delay signal clk_core_dly2, secondary delay after delays time to control unit 2 (DELAY_CELL_2)
Delay times of the signal clk_core_dly2 with respect to a time delayed signal clk_core_dly1 is dly2, can be controlled by being delayed
Information (dly_ctrl2) processed is that dly2 regulates and controls to delay time.Secondary delay signal clk_core_dly2 is controlled by delay
After unit 3 (DELAY_CELL_3) processed, time delayed signal clk_core_dly3 three times is exported, three times time delayed signal clk_core_
Delay times of the dly3 with respect to secondary delay signal clk_core_dly2 is dly3, can pass through delays time to control information (DELAY_
CELL_3 it is) that dly3 regulates and controls to delay time.As shown in Fig. 2 secondary delay signal clk_core_dly2 passes through phase inverter
After negating, the input of two inputs and door, the output signal with door are connected to together with microcontroller core clock clk_core
Eeprom memory interface is driven as the read request pulse signal (e2c_rd) for reading eeprom memory.Time delayed signal three times
Clk_core_dly3 is connected to two inputs and door after phase inverter negates together with microcontroller core clock clk_core
Input, drive eeprom memory to connect as the gating signal (e2c_cs) of eeprom memory with the output signal of door
Mouthful.By changing delays time to control information (dly_ctrl1, dly_ctrl2, dly_ctrl3) to EEPROM interface control module
(EEPROM_INTF) the output delay of delay unit is controlled in, and read request pulse signal (e2c_rd) can be made to meet arteries and veins
It is wider than the requirement of minimum pulse width duration, while it is smaller its pulsewidth is tried one's best, and can make during eeprom memory is read,
Eeprom memory is only in the read power consumption modes that power consumption is of a relatively high in the relatively short time.Also, by reading
After taking the data of EEPROM memories successfully to return, the gating signal (e2c_cs) of eeprom memory is closed, so that
EEPROM memories are only in the of a relatively high static power consumption modes of power consumption in the relatively short time, in remaining time,
EEPROM memories can substantially reduce the work(of microcontroller all in the relatively low standby power consumption modes of power consumption