CN1971543A - Method and device to realize data read-write control in burst mechanism - Google Patents

Method and device to realize data read-write control in burst mechanism Download PDF

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CN1971543A
CN1971543A CN 200610162318 CN200610162318A CN1971543A CN 1971543 A CN1971543 A CN 1971543A CN 200610162318 CN200610162318 CN 200610162318 CN 200610162318 A CN200610162318 A CN 200610162318A CN 1971543 A CN1971543 A CN 1971543A
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write
read
data
address pointer
module
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CN100524269C (en
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吕品
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Wuxi Vimicro Corp
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Vimicro Corp
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Abstract

The invention provides a data read-write control method under the burst mechanism, the method includes following steps: A. reading or writing FIFO module according to the obtained read-write address pointers of the BURST length allocation; B. reading or writing FIFO module according to the reading address pointers, the writing address pointers to generate the data reading spacing signal, reading or writing FIFO module according to the reading address pointers, the writing address pointers, the length of BURST, and the data full signal generated by the reading writing FIFO depth. The invention also provides a data read-write control device under the burst mechanism, the invention adopts the FIFO model to guarantee the real time of the data transmission, and the read-write FIFO module control the reading and writing of the data under the BURST transmission mechanism.

Description

A kind of burst mechanism is realized the method and apparatus of data read-write control down
Technical field
The present invention relates to the data read-write control technology, particularly a kind of burst mechanism is realized the method and apparatus of data read-write control down.
Background technology
In direct memory access (DMA) controller, functional module, for example, safe digital card (SD) controller etc. and DMA control module according to reading or writing reading sky or writing full signal of first-in first-out (FIFO) module generation, are carried out data read-write operation to this module.
Fig. 1 is the structural representation based on the dma controller of AMBA bus, and as shown in Figure 1, this controller comprises: DMA control module 100, write FIFO or BUFFER module 111, read FIFO or BUFFER module 112 and functional module 120.Wherein, the data transmission between DMA control module 100 and the functional module has two kinds of transmission modes, i.e. fifo mode and BUFFER pattern, and the user therefrom selects a kind of transmission mode according to actual needs.
As shown in Figure 1, under fifo mode, when writing fifo module during 111 non-expiring, functional module 120 writes data to this module, and when writing fifo module 111 non-NULLs, DMA control module 100 is reading of data from this module.When reading fifo module during 112 non-expiring, DMA control module 100 writes the input data in this module, and when reading fifo module 112 non-NULLs, functional module 120 is reading of data from this module.
Under the FIFO mode of operation, write fifo module 111 and read fifo module 112 and produces respectively and read spacing wave and write full signal, control the data read-write operation of DMA control module 100 and functional module 120, concrete operations are as follows:
DMA control module 100 is 1 to carry out reading and writing data with length, promptly Ci Shi DMA control module 100 is in normal read-write mechanism, when last data in writing fifo module 111 are read away, write fifo module 111 generations and read spacing wave, notice DMA control module 100 is reading of data from write fifo module 111 again, in other words, as long as write data non-NULL in the fifo module 111, DMA control module 100 just can be from write fifo module 111 sense data.When writing data, make that read fifo module 112 is write when full, read fifo module 112 generations and write full signal, notice DMA control module 100 can not be again toward reading to write data in the fifo module 112, in other words, as long as the data of writing in the fifo module 111 are non-full, DMA control module 100 just can be write fifo module 111 in the past and write data.Write fifo module 111 and the data read-write operation control method of reading 112 pairs of functional modules 120 of fifo module, basic identical with data read-write operation control method to DMA control module 100, different is: when functional module 120 writes data to writing fifo module 111, when making that writing fifo module 111 becomes full, write fifo module 111 generation data and write full signal, informing function module 120 can not be again toward self writing data; Read data and make and to read fifo module 112 when empty from reading fifo module 112 when functional module 120, read fifo module 112 and produce and read spacing wave, informing function module 120 can not be again from self sense data.
Under the BUFFER mode of operation, the burst of DMA control module 100 (BURST) length is configurable, when DMA control module 100 write onces were completely read BUFFER module 112, reading BUFFER mould 112 generation interrupting information notice DMA control modules 100 can not be again toward reading to write data in the BUFFER module 112.Equally, have only when DMA control module 100 is disposable when reading sky and writing BUFFER module 111, write BUFFER module 111 and could produce interrupting information, notice DMA control module 100 is sense data from write BUFFER module 111 again.Equally, write BUFFER module 111 and the data read-write operation control method of reading 112 pairs of functional modules 120 of BUFFER module, basic identical with data read-write operation control method to DMA control module 100, difference is, when functional module 120 write onces are completely write BUFFER module 111, write BUFFER module 111 and could produce interrupting information, informing function module 120 can not write data toward writing in the BUFFER module 111 again; When functional module 120 is disposable when reading sky and reading BUFFER module 112, to read BUFFER module 112 and can produce interrupting information, informing function module 120 is sense data from read BUFFER module 112 again.
What more than provide is the scheme of normal read-write mechanism under fifo mode and the BUFFER pattern, also has data write control problem under the burst mechanism in the practical application, but fifo module can not carry out data write control according to BURST length under BURST mechanism.Be 2 with BURST length below n(n 〉=1, and n is integer, for example, n=3) is example is introduced and is read or write fifo module in the prior art and can not carry out the reason of data read-write control under the burst mechanism according to this BURST length.
With existing fifo mode is example, during 8 of data deficiencies in writing fifo module 111, DMA control module 100 can not be finished the BURST data reading operation one time, write fifo module 111 and should produce and read spacing wave this moment, but under existing fifo mode, when having only last data in writing fifo module 111 to be read away, write fifo module 111 and could produce and read spacing wave by DMA control module 100.Equally, also can there be such problem for reading fifo module 112, when 8 of the remaining data insufficient spaces of reading fifo module 112, DMA control module 100 can not be finished the BURST data write operation one time, reading fifo module 112 this moment should produce data and write full signal, but under existing fifo mode, have only when writing data and make that reading fifo module 112 becomes completely, read fifo module 112 and could produce and write full signal.So fifo module can not carry out data read-write control to DMA control module 100 under burst mechanism.
Equally, under the FIFO mode of operation, when functional module 120 is in BURST read-write mechanism, when fifo module is carried out read-write operation, also can there be described DMA control module 100 existing problems, difference is, when 8 of the remaining data insufficient spaces of writing fifo module 111, functional module 120 can not be finished the BURST data write operation one time, write fifo module 111 and should produce and write full signal this moment, but under existing fifo mode, have only when functional module 120 writes data and makes that writing fifo module 111 becomes full, write fifo module 111 and could produce and write full signal.During 8 of data deficiencies in reading fifo module 112, functional module 120 can not be finished the BURST data reading operation one time, reading fifo module 112 this moment should produce data and read spacing wave, but under existing fifo mode, when having only last data in reading fifo module 112 to be read away, read fifo module 112 and could produce data and read spacing wave by functional module 120.As can be seen, fifo module can not carry out data read-write control to functional module 120 under burst mechanism.
As seen, during normal mechanism, the DMA control module is operated under the fifo mode, can with read or write fifo module and carry out the real time data read-write operation.Because reading or writing fifo module can not carry out read-write operation to data according to BURST length, and produce data and read empty and write full signal according to reading or writing fifo module, therefore read or write fifo module and can not under burst mechanism, produce the read-write operation that the data read-write control signal is controlled the DMA control module.And be operated in BUFFER pattern following time when the DMA control module, and read or write the BURST length that the BUFFER module can dispose the DMA control module, still, the DMA control module can not be carried out the real time data read-write operation.
Summary of the invention
In view of this, the object of the present invention is to provide the method that realizes data read-write control under a kind of burst mechanism, use this method to guarantee to read or write fifo module and under burst transfer mechanism, can carry out data read-write control, improve the transfer efficiency of DMA control module.
Another object of the present invention is to provide the device of realizing data read-write control under a kind of burst mechanism, use this device to guarantee to read or write fifo module under burst transfer mechanism, can carry out data read-write control, improve the transfer efficiency of DMA control module.
In order to achieve the above object, the invention provides the method that realizes data read-write control under a kind of burst mechanism, it is characterized in that this method may further comprise the steps:
A, read or write fifo module according to the BURST length obtained configuration read/write address pointer;
B, read or write fifo module and produce data and read spacing wave, read or write fifo module and produce data and write full signal according to reading address pointer, write address pointer, BURST length and the read-write FIFO degree of depth according to reading address pointer, write address pointer.
In the described steps A: read or write fifo module according to the control information that receives, obtain BURST length.
In described steps A, the length of described BURST is 2 n, n is the integer more than or equal to 1.
In described steps A, the described fifo module that reads or writes comprises according to the step that the BURST length of obtaining disposes the read/write address pointer:
The described fifo module that reads or writes is got the high N-n position that address pointer is read in the N position under the normal read WriteMode; Describedly read or write the high N-n position that fifo module is got the N position write address pointer under the normal read WriteMode.
The described fifo module that reads or writes according to the described step of obtaining of reading address pointer of BURST length configuration is:
The described fifo module that reads or writes is read the address pointer n position that moves to right with the N position under the normal read WriteMode, to the high n position zero padding of reading address pointer after moving to right;
The described fifo module that reads or writes is according to the described BURST length of obtaining, the step that disposes described write address pointer is: the described fifo module that reads or writes is with the n position that moves to right of the N position write address pointer under the normal read WriteMode, to the high n position zero padding of the write address pointer after moving to right.
Described step B specifically comprises: when reading address pointer and equal write address pointer, read or write fifo module and produce data and read spacing wave;
When write address pointer with read the product of difference and the BURST length of address pointer, when equaling the described FIFO degree of depth, read or write fifo module generation data and write full signal.
Further comprise behind the described step B: when writing fifo module and producing data and read spacing wave, described signal is sent to direct memory access DMA control module when described, notify the described DMA control module can not be again from self reading of data;
When reading fifo module and producing data and read spacing wave, described signal is sent to functional module when described, notify the described functional module can not be again from self reading of data;
When writing fifo module and producing data and write full signal, described signal is sent to functional module when described, notify described functional module not write data to self again;
When reading fifo module and producing data and write full signal, described signal is sent to the DMA control module when described, notify described DMA control module not write data to self again.
In order to reach another object of the present invention, the invention provides the device of realizing data read-write control under a kind of burst mechanism, this device is for reading or writing fifo module, comprise: dual-ported memory, according to write address pointer and read address pointer, carry out data storage operations, this device further comprises:
Reading or writing the address produces logic and reads sky or write full signal generation logic;
The described address that reads or writes produces logic, be used to obtain BURST length, read address pointer and write address pointer according to the described BURST length configuration of obtaining, read address pointer and the write address pointer of configuration sent to and read sky or write full signal to produce logic and described dual-ported memory;
Describedly read sky or write full signal to produce logic, be used to receive described address pointer and the write address pointer read, produce data and read spacing wave according to reading address pointer, write address pointer, described data are read spacing wave to send, write full signal according to reading address pointer, write address pointer, BURST length and read-write FIFO degree of depth generation data, described data are write full signal send.
This device further comprises: BURST length configuration register is used for the length of BURST is configured to 2 n, n is the integer more than or equal to 1, the length of described BURST of configuration is sent to the described address that reads or writes produce logic.
This device further comprises: DMA control module and functional module,
Described DMA control module, when receive described write in the fifo module read sky or write full signal to produce data that logic sends and read spacing wave the time, no longer write the fifo module reading of data from this; When receive described read in the fifo module read sky or write full signal to produce data that logic sends and write full signal the time, no longer read to write in the fifo module data to this;
Described functional module, when receive described write in the fifo module read sky or write full signal to produce data that logic sends and write full signal the time, no longer write fifo module and write data to this; When receive described read in the fifo module read sky or write full signal to produce data that logic sends and read spacing wave the time, no longer read the fifo module reading of data from this.
By such scheme as can be seen, a kind of burst mechanism provided by the invention is realized the method and apparatus of data read-write control down, reads or writes fifo module according to the BURST length configuration read/write address pointer that obtains; Read or write fifo module and produce data and read spacing wave, read or write fifo module and produce data and write full signal according to reading address pointer, write address pointer and the read-write FIFO degree of depth according to reading address pointer, write address pointer.Use technical scheme provided by the present invention, can realize reading or writing fifo module under the BURST transmission mechanism, read spacing wave according to comparing read/write address pointer generation data, or produce data according to the relation of the product of the difference of read/write address pointer relatively and BURST length and the read-write FIFO degree of depth and write full signal, thereby realize reading or writing the data read-write control of fifo module under the BURST transmission mechanism.
In the present invention, read or write fifo module and can dispose BURST length neatly, BURST length can be configured to 2 n, wherein n is the integer more than or equal to 1.Read or write fifo module according to BURST length, produce data and read sky or write full signal, DMA control module and functional module are according to reading sky or writing full signal, with 2 nFor unit carries out data read-write operation.This programme can also solve in the prior art, and DMA control module and functional module are unit when reading and writing data with 1, take the problem that advanced microcontroller bus architecture (AMBA) bus influences other module work for a long time.In addition, also can solve the DMA control module because of constantly sending read-write application, the problem that the system power dissipation that causes increases.
Description of drawings
Fig. 1 is the structural representation based on the dma controller of AMBA bus;
Fig. 2 is fifo module is realized the method for data read-write control under burst transfer mechanism the process flow diagram that reads or writes of the present invention;
Fig. 3 writes fifo module to produce the schematic flow sheet that data are read the spacing wave method under BURST mechanism;
Fig. 4 reads fifo module to produce the schematic flow sheet that data are write full signal method under BURST mechanism;
Fig. 5 is a structural representation of realizing the device of data read-write control under burst mechanism;
Fig. 6 is the structural representation of first preferred embodiment of the device of realization data read-write control under burst mechanism.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
Core concept of the present invention is: under the FIFO mode of operation, when guaranteeing the real-time transmission, read or write fifo module according to the BURST length configuration read/write address pointer that obtains, read or write fifo module and produce data and read spacing wave, read or write fifo module and produce data according to the read-write FIFO degree of depth of reading address pointer, write address pointer, BURST length and configuration and write full signal according to reading address pointer, write address pointer.Therefore, fifo module read-write control to DMA control module and functional module under BURST mechanism can be realized reading or writing, the transfer efficiency of DMA control module can be improved simultaneously.
Fig. 2 is the process flow diagram of realization fifo module of the present invention data read-write control method under burst transfer mechanism.These method concrete steps are as follows:
Step 201: read or write fifo module according to the BURST length configuration read/write address pointer that obtains.
Step 202: read or write fifo module and produce data and read spacing wave, read or write fifo module and produce data and write full signal according to reading address pointer, write address pointer, BURST length and the read-write FIFO degree of depth according to reading address pointer, write address pointer.
The concrete operations of this step are: read or write fifo module and at first compare write address pointer and read address pointer, when both are equal, think that reading or writing fifo module is read sky, then produce and read spacing wave.Read address pointer when write address pointer deducts, when the product of both differences and BURST length equals to read and write the FIFO degree of depth, think that reading or writing fifo module has been write completely, then read or write fifo module generation data and write full signal.
In embodiment illustrated in fig. 2, fifo module can be configured to 2 with the length of BURST n, wherein, the integer of n 〉=1, the degree of depth of the described FIFO of reading or writing is 2 m, wherein, m is the integer more than or equal to n.Be 8 to be example with the length of BURST below, introduce when the DMA control module is carried out read or write to reading or writing fifo module, write fifo module and how to read spacing wave by comparing the generation of read/write address pointer, how read FIFO according to the read/write address pointer, and the relation between the read-write FIFO degree of depth produces the operation of writing full signal.
In the prior art, read or write fifo module the read/write address pointer be configured to respectively: rd_addr[N-1:0] and wr_addr[N-1:0], wherein, N is the total bit of address.Rd_addr[N-1:0] expression N position scale-of-two reads address pointer, uses the 0th to carry out read operation to the N-1 position, whenever carries out a read operation, and this is read address pointer and adds 1.Wr_addr[N-1:0] expression N position binary write address pointer, N is the total bit of write address pointer, uses the 0th to carry out read operation to the N-1 position, whenever carries out this write address pointer of write operation and adds 1.Read or write relatively read/write address pointer of fifo module, as rd_addr[N-1:0]=wr_addr[N-1:0] time, produce and read spacing wave.As wr_addr[N-1:0]-rd_addr[N-1:0] the value and the product of BURST length when equaling to read and write the FIFO degree of depth, produce data and write full signal.In the embodiment shown in Figure 2, reading or writing FIFO comprises according to the concrete steps that the BURST length of obtaining disposes the read/write address pointer: when BURST length is 2 nThe time, get and read address pointer rd_addr[N-1:0 under the normal read WriteMode] high n position, the address pointer of reading after the configuration is: rd_addr[N-1:n], read or write fifo module and use high N-n position after the configuration to read address pointer to carry out read operation, here N-n is the poor of N and n.Get the write address pointer wr_addr[N-1:0 under the normal read WriteMode] high n position, write address pointer after the configuration is: wr_addr[N-1:n], read or write fifo module and use the high N-n position write address pointer after disposing to carry out write operation, N is the total bit of address, and n is the integer more than or equal to 1.The FIFO degree of depth is 2 m, wherein, 2 mGreater than 2 n
Technical scheme of the present invention can be used in the dma controller, reads or writes FIFO generation data and reads sky or write full signal, and DMA control module and functional module are carried out data read-write control.In Fig. 3 and embodiment shown in Figure 4, introduce respectively and write fifo module and produce data and read spacing wave and read fifo module to produce data and write full signal, the DMA control module is carried out the specific operation process of data read-write control.In the embodiment shown in fig. 3, provide and write FIFO and produce the specific operation process that data are read spacing wave by read/write address pointer relatively.In the embodiment shown in fig. 4, provide and read FIFO by relatively read/write address pointer, BURST length and read or write relation between the FIFO degree of depth, the generation data are write the concrete implementation step of full control signal.
Fig. 3 writes fifo module to produce the method flow synoptic diagram of reading spacing wave under BURST mechanism; As shown in Figure 3, concrete steps are as follows:
Step 301: write fifo module and obtain BURST length.
In this step, write fifo module from the control information that the register of being responsible for configuration BURST length sends, getting access to BURST length is 8.
Step 302: write fifo module according to the BURST length of obtaining, configuration read/write address pointer.
In this step, writing the concrete steps that fifo module obtains BURST length configuration read/write address pointer comprises: for example, writing fifo module is 8 according to BURST length, to read address pointer and be configured to rd_addr[5:3], write address pointer is configured to wr_addr[5:3], N is the address total bit, N is taken as 6 here.
Step 303: write fifo module by relatively reading address pointer and write address pointer, judge whether both equate, if both equate that then execution in step 304; Otherwise, execution in step 305.
In this step, get access to BURST length according to control information and be configured to 8, so the DMA control module is that unit carries out data reading operation with 8; When DMA whenever carries out a read operation to writing FIFO, read address pointer and add 1, same, when functional module was whenever carried out a write operation to writing FIFO, write address pointer added 1.When the described write address pointer of writing fifo module when reading address pointer, represent in this module in addition the data that can read for the DMA control module; When reading address pointer and equaling write address pointer, expression is write fifo module and is read sky, then produces data and reads spacing wave when described.
Step 304: write fifo module generation data and read spacing wave.
Step 305: write fifo module and do not produce data and read spacing wave, process ends.
Below in conjunction with a concrete example, introduce the fifo module of writing in prior art and the step 303 respectively, how to read spacing wave according to comparing read/write address pointer generation data.For example, the total length of read/write address is 6, and under prior art normal read WriteMode, the initial address of reading address pointer and write address pointer is configured to respectively: rd_addr[000000] and wr_addr[000000].Whenever carry out write operation one time to writing fifo module, described write address pointer adds 1, when to described write fifo module and carry out 32 write operations after, write address pointer becomes: wr_addr[100000].Equally, whenever carry out a read operation to writing fifo module, the described address pointer of reading adds 1, when to after writing fifo module and carrying out 32 read operations, reading address pointer becomes: rd_addr[100000], and equal write address pointer wr_addr[100000], the data that expression is write in the fifo module are read sky, and the described fifo module generation data of writing are read spacing wave.According to technical scheme provided by the invention, if BURST length is configured to 8, the initial address of reading address pointer and write address pointer is respectively: rd_addr[000000] and wr_addr[000000].If the described fifo module of writing is written into 32 data, the method that is configured to described write address pointer is: with the write address pointer wr_addr[100000 under the normal mode] move to right 3, and high 3 zero paddings of the write address pointer after will moving to right, the write address pointer under the BURST mechanism becomes: wr_addr[000100].Carry out read operation with BURST=8 to writing fifo module, whenever read 8 data, the described address pointer of reading adds 1, when to described write fifo module and carry out 4 read operations after, the address pointer of reading of this moment becomes: rd_addr[000100], and equal write address pointer wr_addr[000100], the data that expression is write in the fifo module are read sky, then write fifo module generation data and read spacing wave.
Fig. 4 reads fifo module to produce the method flow synoptic diagram that data are write full signal under BURST mechanism.As shown in Figure 4, concrete steps are as follows:
Step 401: read fifo module according to the BURST length configuration read/write address pointer that obtains.
In this step, reading fifo module according to the method that the BURST length of obtaining disposes the read/write address pointer is: for example, reading fifo module is 8 according to BURST length, to read address pointer and be configured to rd_addr[5:3], write address pointer is configured to wr_addr[5:3], N is the total length of address pointer, N is taken as 6 here, and getting the read-write FIFO degree of depth is 32.
Step 402:FIFO module is calculated write address pointer and is read the poor of address pointer, the product and read-write FIFO self degree of depth of both differences and BURST length compared, if equal then execution in step 403, otherwise execution in step 404.
In this step, fifo module deducts with write address pointer and reads address pointer, if the product of both differences and BURST length equals 32 then execution in step 403, otherwise execution in step 404.
In this step, the method for operating of described read/write address pointer is with step 303, and promptly when DMA whenever carried out a write operation to reading FIFO, write address pointer added 1.Equally, when functional module is whenever carried out a read operation to reading fifo module, read address pointer and add 1.
Step 403: read fifo module generation data and write full signal.
Step 404: read fifo module and do not produce data and write full signal, and process ends.
Below in conjunction with a concrete example, introduce the fifo module of reading in prior art and the step 402 respectively, how according to relatively read-write ground pointer, BURST length and read-write FIFO degree of depth generation data are write full signal.For example, the total length of read/write address is 6, and the read-write FIFO degree of depth is 32.Under prior art normal read WriteMode, the initial value of reading address pointer and write address pointer is respectively: rd_addr[000000] and wr_addr[000000].Whenever carry out write operation one time to reading fifo module, described write address pointer adds 1, when the DMA control module to after reading fifo module and carrying out 32 write operations, write address pointer becomes: wr_addr[100000].Wr_addr[100000]-rd_addr[000000] equal to read and write the FIFO degree of depth 32, expression is read fifo module and is write completely, and the described fifo module generation data of reading are write full signal.According to technical scheme provided by the invention, for example, BURST length is configured to 8, and the initial value of reading address pointer and write address pointer is respectively: rd_addr[000000] and wr_addr[000000].Collocation method to the write address pointer under the BURST mechanism is: with the write address pointer wr_addr[000000 under the normal mode] move to right 3, and high 3 zero paddings of the write address pointer after will moving to right.The DMA control module is carried out write operation with the length of BURST=8 to reading fifo module, whenever write 8 data, described write address pointer adds 1, when to described read fifo module and carry out 4 write operations after, write address pointer becomes: wr_addr[000100], at this moment, the value of (wr_addr[000100]-rd_addr[000000]) * 8 equals to read and write the FIFO degree of depth 32, expression is read fifo module and is write completely, then reads fifo module generation data and writes full signal.Carrying out under the situation of read-write operation simultaneously to reading fifo module, the described fifo module of reading still is configured the read/write address pointer according to said method, and writes full signal according to the relation generation data of described read/write address pointer, BURST length and the read-write FIFO degree of depth.
In Fig. 3 and embodiment shown in Figure 4, introduced the method that the read/write address pointer is configured under the BURST mechanism: at first will read address pointer rd_addr[N-1:0 under the normal read WriteMode] and write address pointer wr_addr[N-1:0] the n position all moves to right, with the high n position zero padding of reading address pointer and write address pointer after moving to right, reading address pointer is configured to: rd_addr[N-1:n], write address pointer is configured to: wr_addr[N-1:n].Fig. 3 and embodiment shown in Figure 4 are most preferred embodiment of the present invention; it is not limitation of the invention; other are any will read address pointer rd_addr[N-1:0 under the normal read WriteMode] and write address pointer wr_addr[N-1:0]; be configured to rd_addr[N-1:n respectively] and wr_addr[N-1:n] method, still within protection scope of the present invention.
Among Fig. 3 and the embodiment shown in Figure 4, equaling 8 with BURST length respectively is example, introduced when the DMA control module is carried out read or write to reading or writing fifo module, read or write fifo module and how to read spacing wave according to reading address pointer and write address pointer generation data, write full signal according to reading address pointer, write address pointer, BURST length and read-write FIFO degree of depth generation data, satisfying BURST length for other is 2 n, n 〉=1, and n is the situation of integer, said method also is suitable for.Equally, when functional module is carried out read or write to reading or writing fifo module, its method of operating is basic identical, difference is: read in the fifo module in that Fig. 4 is described, according to the described method of Fig. 3, when described read/write address pointer equated, the described fifo module generation data of reading were read spacing wave, and the informing function module can not be again from self reading of data; Otherwise the described fifo module of reading does not produce and reads spacing wave and process ends.Write in the fifo module in that Fig. 4 is described, according to the described method of Fig. 3, when write address pointer equals to read and write the FIFO degree of depth with the product of reading address pointer difference and BURST length, to write the fifo module generation and write full signal, the informing function module can not be again toward self writing data; Otherwise the described fifo module of writing does not produce and writes full signal, and process ends.
Be presented in the device of realizing data read-write control under the burst mechanism below, in the present invention, this device is for reading or writing fifo module.
Fig. 5 is a structural representation of realizing the device of data read-write control under burst mechanism; As shown in Figure 5, this device comprises for reading or writing fifo module 500: read or write the address and produce logic 501, read sky or write full signal generation logic 502 and dual-ported memory 503;
Read or write the address and produce logic 501, be used to obtain BURST length, and according to the BURST length obtained address pointer and write address pointer are read in configuration, read address pointer and the write address pointer of configuration sent to and reads sky or write full signal to produce logic 502 and dual-ported memory 503.
Read sky or write full signal to produce logic 502, reception reads or writes that the address produces that logic sends reads address pointer and write address pointer, produce data and read spacing wave according to reading address pointer, write address pointer, produce data and write full signal according to reading address pointer, write address pointer, BURST length and the read-write FIFO degree of depth.
Dual-ported memory 503 is used for receiving and reads or writes the address and produce logic 501 and send and read address pointer and write address pointer, carries out the storage operation of data according to described pointer.
Fig. 6 is the structural representation of first preferred embodiment of the device of realization data read-write control under burst mechanism; As shown in Figure 6, this device comprises: functional module 610, DMA control module 620 and BURST length configuration register 630, write fifo module 640 and read fifo module 650.
BURST length configuration register 630 is used to dispose BURST length, described BURST length is sent to read or write address generation logic 641, for example, BURST length can be configured to 8.
Read or write the address and produce logic 641, be used to receive the BURST length that BURST length configuration register 630 sends, according to this length configuration read/write address pointer.In the present embodiment, read address pointer and write address pointer is configured to respectively: rd_addr[5:3 with described] and wr_addr[5:3].Wherein, the 6th, the total length of address, the degree of depth of writing fifo module 640 is 32.
Read sky or write full signal to produce logic 642, be used to receive the read/write address pointer that reads or writes 641 transmissions of address generation logic.More described read/write address pointer is as rd_addr[5:3]=wr_addr[5:3] time, read sky or write full signal to produce logic 642 and produce data and read spacing wave and send to described DMA control module 620, notify it can not be again from self sense data.Read sky or write full signal produce logic 642 relatively (wr_addr[5:3]-rd_addr[5:3]) * 8 value and write the value of the FIFO degree of depth, when (wr_addr[6:3]-rd_addr[6:3]) * 8=32, read sky or write full signal to produce logic 642 and produce data and write full signal, send to functional module 610 and notify it not write data to self again.
Functional module 610 writes data to dual-ported memory 643, reads sky or write full signal to produce the data that logic 642 sends and write full signal if functional module 610 is received, and no longer writes data in dual-ported memory 643.
DMA control module 620 from dual-ported memory 643 reading of data, is read sky or writes full signal to produce the data that logic 642 sends and read spacing wave if DMA control module 620 is received, no longer reading of data from dual-ported memory 643.
Functional module 610, DMA control module 620 and read the method for read-write operation between the fifo module 650 are with above-mentioned functions module 610, DMA control module 620 with to write between the fifo module 640 read-write operation method identical.Functional module 610 is just read sky or writes full signal to produce the data that logic 652 sends and read under the situation of spacing wave receiving, no longer from dual-ported memory 653 reading of data.Described DMA control module 620 is read sky or writes full signal to produce the data that logic 652 sends and write under the situation of full signal receiving, and no longer writes data to dual-ported memory 653.
In the above-described embodiments, introduced DMA control module and functional module, how read empty and write full signal and carry out data read-write operation according to reading or writing data that fifo module produces.Other and the present invention have the apparatus and method of same principle, also within protection scope of the present invention.
In sum, more than be preferred embodiment of the present invention only, be not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (10)

1, a kind of burst mechanism is realized the method for data read-write control down, it is characterized in that this method may further comprise the steps:
A, read or write fifo module according to the BURST length obtained configuration read/write address pointer;
B, read or write fifo module and produce data and read spacing wave, read or write fifo module and produce data and write full signal according to reading address pointer, write address pointer, BURST length and the read-write FIFO degree of depth according to reading address pointer, write address pointer.
2, method according to claim 1 is characterized in that, in the described steps A:
Read or write fifo module according to the control information that receives, obtain BURST length.
3, method according to claim 1 and 2 is characterized in that, in described steps A, the length of described BURST is 2 n, n is the integer more than or equal to 1.
4, method according to claim 3 is characterized in that, in described steps A, the described fifo module that reads or writes comprises according to the step that the BURST length of obtaining disposes the read/write address pointer:
The described fifo module that reads or writes is got the high N-n position that address pointer is read in the N position under the normal read WriteMode; Describedly read or write the high N-n position that fifo module is got the N position write address pointer under the normal read WriteMode.
5, method according to claim 3 is characterized in that,
The described fifo module that reads or writes according to the described step of reading address pointer of the BURST length obtained configuration is: the described fifo module that reads or writes is read the address pointer n position that moves to right with the N position under the normal read WriteMode, to the high n position zero padding of reading address pointer after moving to right;
The described fifo module that reads or writes is according to the described BURST length of obtaining, the step that disposes described write address pointer is: the described fifo module that reads or writes is with the n position that moves to right of the N position write address pointer under the normal read WriteMode, to the high n position zero padding of the write address pointer after moving to right.
6, method according to claim 1 is characterized in that, described step B specifically comprises:
When reading address pointer and equal write address pointer, read or write fifo module and produce data and read spacing wave;
When write address pointer with read the product of difference and the BURST length of address pointer, when equaling the described FIFO degree of depth, read or write fifo module generation data and write full signal.
7, method according to claim 6 is characterized in that, further comprises behind the described step B:
When writing fifo module and producing data and read spacing wave, described signal is sent to direct memory access DMA control module when described, notify the described DMA control module can not be again from self reading of data;
When reading fifo module and producing data and read spacing wave, described signal is sent to functional module when described, notify the described functional module can not be again from self reading of data;
When writing fifo module and producing data and write full signal, described signal is sent to functional module when described, notify described functional module not write data to self again;
, described data are write full signal send to the DMA control module when reading fifo module and producing data and write full signal when described, notify described DMA control module not write data to self again.
8, a kind of burst mechanism is realized down the device of data read-write control, and this device comprises for reading or writing fifo module: dual-ported memory, be used for according to write address pointer with read address pointer, carry out data storage operations;
It is characterized in that this device further comprises:
Reading or writing the address produces logic and reads sky or write full signal generation logic;
The described address that reads or writes produces logic, be used to obtain BURST length, read address pointer and write address pointer according to the described BURST length configuration of obtaining, read address pointer and the write address pointer of configuration sent to and read sky or write full signal to produce logic and described dual-ported memory;
Describedly read sky or write full signal to produce logic, be used to receive described address pointer and the write address pointer read, according to read address pointer, write address pointer produces data and reads spacing wave, described data are read spacing wave send; Write full signal according to reading address pointer, write address pointer, BURST length and read-write FIFO degree of depth generation data, described data are write full signal send.
9, device according to claim 8 is characterized in that, this device further comprises: BURST length configuration register is used for the length of BURST is configured to 2 n, n is the integer more than or equal to 1, the length of described BURST of configuration is sent to the described address that reads or writes produce logic.
10, device according to claim 8 is characterized in that, this device further comprises: DMA control module and functional module,
Described DMA control module, when receive described write in the fifo module read sky or write full signal to produce data that logic sends and read spacing wave the time, no longer write the fifo module reading of data from this; When receive described read in the fifo module read sky or write full signal to produce data that logic sends and write full signal the time, no longer read to write in the fifo module data to this;
Described functional module, when receive described write in the fifo module read sky or write full signal to produce data that logic sends and write full signal the time, no longer write fifo module and write data to this; When receive described read in the fifo module read sky or write full signal to produce data that logic sends and read spacing wave the time, no longer read the fifo module reading of data from this.
CNB2006101623185A 2006-12-11 2006-12-11 Method and device to realize data read-write control in burst mechanism Expired - Fee Related CN100524269C (en)

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