CN103377029B - parameterized universal FIFO control method - Google Patents

Abstract

The present invention relates to a kind of parameterized Universal FIFO control method, the method comprises the following steps: 1) Universal FIFO control circuit is inputted to static input parameter; 2) shine upon the required built-in variable of accomplished fifo control circuit according to static input parameter; 3) according to step 2) FIFO that produces controls required inside circuit variable and realizes required Universal FIFO control circuit. The invention provides a kind of by the precompile means of parameter preset, can be multiplexing in all designs that need to use FIFO, avoid repeatedly designing, use " section Gray code " simultaneously, to reading, writing address, unification adds a fixed increment value, make its binary system Gray code that transforms to a maximum and minimum of a value only have a different numerical value section, then carry out Gray code conversion and go to use, thereby make the degree of depth can be the parametrization Universal FIFO control method of any even number.

Description

Parameterized Universal FIFO control method

Technical field

The invention belongs to computer hardware technology field, relate to a kind of circuit control method, relate in particular to a kind of parametrizationUniversal FIFO control method.

Background technology

FIFO (First-In, First-out), i.e. push-up storage, is divided into synchronization fifo and asynchronous FIFO, is oneKind be usually used in the circuit devcie of data buffer storage, can be applicable to comprise high-speed data acquisition, multiprocessor interface and communicate by letter in heightThe various fields such as speed buffering. With the difference of applied environment, FIFO may have the different degree of depth, different data bit according to demandWide, different read-write timing relationships, the full indicating mode of different skies etc., need to repeatedly design respectively by demand conventionally, and differentStep FIFO generally uses Gray code to read and write address comparison, is not 2 power if this just causes the FIFO degree of depth, reading and writing groundWhen 0 value is got back to by maximum (degree of depth-1) in location, be 1 because peaked binary system Gray code has multidigit, while becoming full 0 again, can occurMultidigit, by 1 to 0 saltus step, only has the advantage of a saltus step thereby lose the adjacent code value of Gray code, brings metastable state hidden danger, thereforeThe asynchronous FIFO degree of depth is confined to 2 power conventionally, causes the wasting of resources, uses also very inconvenient.

Summary of the invention

In order to solve the above-mentioned technical problem existing in background technology, the invention provides a kind of the pre-of parameter preset that pass throughCompiling means, can be multiplexing in all designs that need to use FIFO, avoids repeatedly designing, use " section Gray code " simultaneously,To reading, writing address, unification adds a fixed increment value, makes it transform to the binary system Gray of a maximum and minimum of a valueCode only has a different numerical value section, then carries out Gray code conversion and go to use, thereby makes the degree of depth can be the parameter of any even numberChange Universal FIFO control method.

Technical solution of the present invention is: the invention provides a kind of parameterized Universal FIFO control method, its spyDifferent part is: described parameterized Universal FIFO control method comprises the following steps:

1) Universal FIFO control circuit is inputted to static input parameter;

2) shine upon the required built-in variable of accomplished fifo control circuit according to static input parameter;

3) according to step 2) FIFO that produces controls required inside circuit variable and realizes required Universal FIFO control circuit,Wherein address comparison circuit adopts " section Gray code " to realize.

Above-mentioned static input parameter comprises FIFO depth D EPTH, the full threshold value PROG_FULL_THRESH of programming and dataPre-read model selection FIRST_WORD_FT;

Described FIFO depth D EPTH realizes resource to allow any even number in limit;

The setting value of the full threshold value PROG_FULL_THRESH of described programming is the positive integer that is less than FIFO depth D EPTH;

The setting value of described data pre-head model selection FIRST_WORD_FT is 1 or 0; Described data pre-head model selectionThe setting value of FIRST_WORD_FT is 1 o'clock, represents to select pre-reading mode, on data fifo output bus DOUT, always pre-reads FIFOCurrent first data in going out; The setting value of described data pre-head model selection FIRST_WORD_FT is 0 o'clock, represents to select non-Pre-reading mode, only have when read enable signal RD_EN effective after, on data-out bus DOUT, just export current first data.

Above-mentioned fifo control circuit built-in variable comprises dual-port bank-address width ADDR_WIDTH, data writing meterNumber device bit wide WR_DATA_COUNT_WIDTH, readable data counter bit wide RD_DATA_COUNT_WIDTH, read/write address latticeThunder code conversion section increment SECTION_INC and section Gray code data bit width GRAY_WIDTH;

Described dual-port bank-address width ADDR_WIDTH is integer value, and what about beam control circuit generated reads addressThe bus bit wide of read_addr, write address write_addr; Generation realizes the necessary dual-port storage of complete fifo circuitWhen body, also for determining its size;

Said write data counter bit wide WR_DATA_COUNT_WIDTH is integer value, about beam control circuit outputThe bit wide of data writing number count value;

Described readable data counter bit wide RD_DATA_COUNT_WIDTH is integer value, about beam control circuit outputThe bit wide of readable data number count value;

Described read/write address Gray code conversion section increment SECTION_INC is integer value, enters for retraining read/write addressThe starting point of selected numerical value section when row Gray code conversion;

Described section Gray code data bit width GRAY_WIDTH is integer value, for retraining the data bit width of section Gray codeDegree.

Above-mentioned steps 2) mapping relations be:

The specific implementation of described dual-port bank-address width ADDR_WIDTH show that mode is:

ADDR_WIDTH=clogb2 (DEPTH); Wherein: clogb2 is function name, described clogb2 is according in bracketInput value, calculates and return function result of calculation; Described DEPTH is FIFO depth D EPTH;

Said write data counter bit wide WR_DATA_COUNT_WIDTH and readable data counter bit wide RD_DATA_COUNT_WIDTH meets following condition:

WR_DATA_COUNT_WIDTH＝RD_DATA_COUNT_WIDTH＝ADDR_WIDTH；

Described reading, writing address Gray code conversion section increment SECTION_INC and section Gray code bit wide GRAY_The mode that specifically draws of WIDTH is:

A) SECTION_INC=0; Compose initial value to SECTION_INC, wait for later step calculating;

b)Temp_0＝bin_to_gray(SECTIONINC)；Temp_1＝bin_to_gray(SECTION_INC+DEPTH); Described Temp_0 and Temp_1 are the temporary variable of definition, and bin_to_gray is function name, described bin_to_grayAccording to the binary code of the input value in bracket, be converted to Gray's agate and return;

C) GRAY_WIDTH=clogb2 (Temp_1); Compose initial value to GRAY_WIDTH, wait for later step calculating; InstituteStating clogb2 is function name, and described clogb2, according to the input value in bracket, calculates and return function result of calculation;

D) compare by turn Temp_0 and Temp_1 and record its unequal figure place, if unequal bits number is 1,Arrive now SECTION_INC and GRAY_WIDTH value, and finish; Otherwise SECTION_INC=SECTION_INC+1, returns to stepRapid b), and repeating step is b) to steps d).

Above-mentioned function clogb2 (input) is the bit wide of calculating and export input value input, and its specific implementation is:

A) result=0; Tmp=input; Tmp is the inner temporary variable of function for this reason, and result is result of calculation;

b)tmp＝tmp＞＞1；

c)result＝result+1；

If d) tmp is greater than 0, returns to step b) and repeat b) to steps d); Otherwise the value of output result, finishes;

Input value is converted into Gray code output by described function bin_to_gray (bin), and specific implementation is:

A) N=clogb2 (bin); N is the inner temporary variable of function for this reason;

B) gray[k]=bin[k] ^bin[k+1], k=0,1 ... N-2, described ^ is xor operation; Gray[N-1]=bin[N-1]

C) value of output gray.

Above-mentioned Universal FIFO control circuit comprises writing makes energy control module, write address generation module, write address section GrayCode modular converter, full signal generates and data writing counter module, read to make energy control module, read address generating module, read groundLocation section Gray code conversion module, spacing wave generate and readable data counter module.

To writing the specific implementation that makes energy control module implement to control be: writing and making the function of energy control module is that output is twoWriting of port memory bank enables control signal write_en; This signal high level is effective, uses Combinational logic output, when FIFO controlThe writing of circuit processed enables input signal wr_en to be high level and to come that self-satisfied signal generates and the expiring of data writing counter moduleSignal full, write_en output high level, otherwise output low level;

The specific implementation that write address generation module is implemented to control is: the function of write address generation module is to generate alsoOutput to the address bus signal write_addr[ADDR_WIDTH-1:0 of dual-port memory bank write port]; Described write address is rawBecoming module is to work in the synchronous circuit of writing under clock wr_clk, and reset signal is wr_rst; Write_addr is registerOutput, reset values is 0; When the rising edge of wr_clk occur and reset signal invalid, now:

If a) fifo control circuit input write that to enable wr_en be high level, carry out self-satisfied signal generates and data writing meterThe full signal full of number device module is low level, go to step b), otherwise write_addr keeps initial value;

If b) write_addr equals DEPTH-1, write_addr output 0, otherwise write_addr is from increasing 1 output;

The specific implementation that write address section Gray code conversion module is implemented to control is: write address section Gray code turnsThe function of die change piece is by write address write_addr[ADDR_WIDTH-1:0] turn after adding upper curtate increment size SECTION_INCBe changed to Gray code wr_addr_gra[GRAY_WIDTH-1:0] and output; Described SECTION_INC is the section increment calculatingParameter;

Write address section Gray code conversion module is to work in the synchronous circuit of writing under clock wr_clk, Gray code wr_Addr_gra[GRAY_WIDTH-1:0] be register output, reset values is SECTION_INC; Be described below:

wr_addr_gra[k]＝(write_addr+SECTION_INC)[k]^(write_addr+SECTION_INC)[k+1], k=0,1 ... GRAY_WIDTH-2, described ^ is xor operation;

wr_addr_gra[GRAY_WIDTH-1]＝(write_addr+SECTION_INC)[GRAY_WIDTH-1]；

To the specific implementation that full signal generates and data writing counter module is implemented to control be: full signal generate andThe function of data writing counter module is the full index signal full of output FIFO, the full signal prog_full of programming and writesData counts value wr_data_count[ADDR_WIDTH-1:0]; This module is to work in the synchronous electric of writing under clock wr_clkRoad, above-mentioned each signal is register output, and reset values is 0;

Described full signal generates and the vectorial cntw_size_var_int[ADDR_ of the interior definition of data writing counter moduleWIDTH:0], its value:

If a) (write_addr+SECTION_INC) be greater than rd_addr_bin, cntw_size_var_int=(write_addr+SECTION_INC)-rd_addr_bin；

B) otherwise (write_addr+SECTION_INC) equal rd_addr_bin if, if full is low level,Cntw_size_var_int=0; If full is high level, cntw_size_var_int=DEPTH;

C) otherwise, cntw_size_var_int=(DEPTH+ (write_addr+SECTION_INC))-rd_addr_bin；

Wherein, rd_addr_bin[GRAYWIDTH-1:0] for reading ground from what read address section Gray code conversion moduleLocation section gray code signal is synchronized to after wr_clk clock zone through this module inter-sync circuit, be converted into binary system code value toAmount signal;

The condition of the full index signal full output of FIFO high level is data with existing number cntw_size_ in current FIFOVar_int is more than or equal to DEPTH or this write operation will make data with existing number cntw_size_var_int in FIFO be greater thanOr equal DEPTH, otherwise be output low level;

The generation of the full signal prog_full of FIFO programming is also similar to the generation of full signal; The full signal prog_full of programmingThe condition of output high level is that in current FIFO, data with existing number cntw_size_var_int is more than or equal to the full threshold value of programmingParameter PROG_FULL_THRESH or this time write operation will make in FIFO data with existing number cntw_size_var_int be greater than orThe full threshold parameter PROG_FULL_THRESH that equals to programme, otherwise be output low level;

FIFO written data count value wr_data_count (write_addr+SECTION_INC) to be greater than or etc.The value of output (write_addr+SECTION_INC)-rd_addr_bin in the time of rd_addr_bin; Otherwise, output (DEPTH+(write_addr+SECTION_INC) value of)-rd_addr_bin;

Make the specific implementation that energy control module is controlled be to reading: reading to make the function of energy control module is that output is twoPort memory bank read to enable control signal read_en; This signal high level is effective, when static parameter data pre-reads model selectionFIRST_WORD_FT setting value is 1, fixing high level, i.e. Chang Youxiao of read_en output; Otherwise read_en inputs FIFORead to enable rd_en output;

To reading the specific implementation that address generation module controls be: the function of reading address generation module is to generate alsoOutput to the address bus signal read_addr[ADDR_WIDTH-1:0 of dual-port memory bank read port]; This module is workIn the synchronous circuit of reading under clock rd_clk, reset signal is rd_rst; Read_addr is register output, and reset values is0; When the rising edge of rd_clk occur and reset signal invalid, now:

Be high level, generate and readable data counter module from spacing wave if what a) FIFO inputted reads to enable rd_enSpacing wave empty be low level, go to step b), otherwise read_addr keep initial value;

If b) read_addr equals DEPTH-1, read_addr output 0, otherwise read_addr is from increasing 1 output;

To reading the specific implementation that address section Gray code conversion module controls be: read address section Gray code and turnThe function of die change piece is to read address read_addr[ADDR_WIDTH-1:0] turn after adding upper curtate increment size SECTION_INCBe changed to Gray code rd_addr_gra[GRAY_WIDTH-1:0] and output; Described SECTION_INC is the section increment calculatingParameter;

Reading address section Gray code conversion module is to work in the synchronous circuit of writing under clock rd_clk, and reset signal isRd_rst; Gray code rd_addr_gra[GRAY_WIDTH-1:0] be register output, reset values is SECTION_INC, retouchesState as follows:

rd_addr_gra[k]＝(read_addr+SECTION_INC)[k]^(read_addr+SECTION_INC)[k+1], k=0,1 ... GRAY_WIDTH-2, described ^ is xor operation;

rd_addr_gra[GRAY_WIDTH-1]＝(read_addr+SECTION_INC)[GRAY_WIDTH-1]。

Spacing wave is generated and the specific implementation controlled of readable data counter module is: spacing wave generate andThe function of readable data counter module is the empty index signal empty of output FIFO and readable data count value rd_data_Count[ADDR_WIDTH-1:0], this module is to work in the synchronous circuit of writing under clock rd_clk, reset signal is rd_Rst; Above-mentioned each signal is register output, and reset values is 0;

The vectorial cntr_size_var_int[ADDR_WIDTH:0 of definition in module], its value:

If wr_addr_bin is greater than (read_addr+SECTION_INC), cntr_size_var_int=wr_addr_bin-(read_addr+SECTION_INC)；

If otherwise wr_addr_bin equals (read_addr+SECTION_INC), if empty is high level, cntr_Size_var_int=0; If empty is low level, cntr_size_var_int=DEPTH.

Otherwise, cntr_size_var_int=(DEPTH+wr_addr_bin)-(read_addr+SECTION_INC);

Wherein, wr_addr_bin[GRAY_WIDTH-1:0] for writing ground from write address section Gray code conversion moduleLocation section gray code signal is synchronized to after rd_clk clock zone through this module inter-sync circuit, be converted into binary system code value toAmount signal;

The condition of the empty index signal empty output of FIFO high level is data with existing number cntr_ in current FIFOSize_var_int equal 0 or this time read operation will make data with existing number cntr_size_var_int in FIFO equal 0, noIt is output low level;

In FIFO, readable data count value rd_data_count is more than or equal to (read_addr+ at wr_addr_binSECTION_INC) time, export the value of wr_addr_bin-(read_addr+SECTION_INC); Otherwise, output (DEPTH+wr_Addr_bin)-value (read_addr+SECTION_INC).

Advantage of the present invention is:

Parameterized Universal FIFO control circuit disclosed by the invention and implementation method, only need to specify three static inputsParameter, just can generate required fifo control circuit, comprises writing making energy control module, write address generation module, write address districtSection Gray code conversion module, full signal generates and data writing counter module, read to make energy control module, read address generate mouldPiece, read address section Gray code conversion module, spacing wave and generate and readable data counter module. Static input parameter comprisesFIFO depth D EPTH, the full threshold value PROG_FULL_THRESH of programming, and first data pre-head model selection FIRST_WORD_FT. The present invention is parametrization, General design, by precompile means, can be applied to any needs and use synchronous, asynchronousIn ASIC, SoC chip design, checking and the FPGA product of FIFO reservoir designs, be extremely conducive to use as the soft core of IPAnd popularization, break away from the dependence to external IP kernel, improve reliability and the controllability of design.

The present invention adopts precompilation techniques, only needs to specify three static parameters, just can be according to the static parameter of inputAutomatically calculate indoor design parameter, avoid the duplication of labour, versatility, portable strong; The FIFO degree of depth is configured by static parameter, noBe confined to 2 power, can be any even number, greatly reduce circuit area and power consumption; The pre-reading mode of optional data, by static state input ginsengNumber configuration; Reading and writing control circuit is independent clock territory, individual reset design, and synchronization fifo, asynchronous FIFO use identical isolationFormula design, reliability is high; Optional FIFO readable data counting and the output of written data counting are provided, meet multiple application needAsk; Control circuit does not comprise memory bank, is not limited to the difference of data bit width, and flexibility is strong.

Brief description of the drawings

Fig. 1 is Universal FIFO control circuit and the connection diagram with dual-port memory bank thereof.

Detailed description of the invention

Parameterized Universal FIFO control circuit disclosed by the invention and implementation method, can, by precompile means, pressRealize synchronization fifo or the necessary home address product of asynchronous FIFO according to default static input parameters such as the degree of depth, the full threshold values of programmingThe control circuits such as life, the control of read-write pointer, empty full scale will, the corresponding dual-ported memory of outside connection can form functionFIFO.

This circuit structure and implementation method can be by precompile means, according to default static state such as the degree of depth, the full threshold values of programmingInput parameter realizes synchronization fifo or the necessary home address of asynchronous FIFO produces, the control of read-write pointer, empty full scale will etc. removeAll control circuits outside memory bank.

The static input parameter of parameterized Universal FIFO control circuit comprises that the FIFO degree of depth, the full threshold value of programming and data are pre-Reading mode is selected. Control circuit comprises writing makes energy control module, write address generation module, write address section Gray code conversion mouldPiece, full signal generates and data writing counter module, read to make energy control module, read address generating module, read address section latticeThunder code modular converter, spacing wave generate and readable data counter module, as shown in Figure 1.

Below the design of parametrization implementation method and each modular circuit is described in detail.

This parameterized Universal FIFO control circuit, its static input parameter comprises:

1) FIFO depth D EPTH: can be any even number of realizing in resource permission limit;

2) the full threshold value PROG_FULL_THRESH of programming: its setting value is for being less than the positive integer of DEPTH;

3) data pre-head model selection FIRST_WORD_FT, its setting value is required to be 1 or 0; Be preset as at 1 o'clock and select to pre-readPattern, on data fifo output bus, always pre-read FIFO go out in current first data; Be preset as at 0 o'clock and select non-pre-reading mode,Only have when read enable signal RD_EN effectively after, on data-out bus, just export current first data.

The each functional module that realizes control circuit, relates to some built-in variables, comprising:

1) dual-port bank-address width ADDR_WIDTH: integer value, what about beam control circuit generated reads address read_The bus bit wide of addr, write address write_addr; When generation realizes the necessary dual-port memory bank of complete fifo circuit,Also for determining its size;

2) data writing counter bit wide WR_DATA_COUNT_WIDTH and readable data counter bit wide RD_DATA_COUNT_WIDTH: integer value, respectively the data writing number count value of about beam control circuit output and readable data number countingThe bit wide of value;

3) reading, writing address Gray code conversion section increment SECTION_INC: integer value, constraint reading, writing address carries out GrayThe starting point of selected numerical value section when code conversion.

4) section Gray code data bit width GRAY_WIDTH: integer value, for retraining the data bit width of section Gray code.

Built-in variable all can be calculated by writing setup code by static input parameter, in detail computational methods asUnder.

Dual-port bank-address width: ADDR_WIDTH, its value of ADDR_WIDTH is drawn by following methods:

ADDR_WIDTH=clogb2 (DEPTH); //clogb2 is function name, and it calculates according to the input value in bracketAnd return function result of calculation.

Data writing counter bit wide WR_DATA_COUNT_WIDTH and readable data counter bit wide RD_DATA_COUNT_WIDTH, meets following condition:

WR_DATA_COUNT_WIDTH＝RD_DATA_COUNT_WIDTH＝ADDR_WIDTH。

Reading, writing address Gray code conversion section increment SECTION_INC and section Gray code bit wide GRAY_WIDTH,SECTION_INC and GRAY_WIDTH must be worth by the iteration of following steps and draw:

A) SECTION_INC=0; // compose initial value to SECTION_INC, wait for later step calculating;

b)Temp_0＝bin_to_gray(SECTION_INC)；Temp_1＝bin_to_gray(SECTION_INC+DEPTH); //Temp_0 and Temp_1 are the temporary variable of definition, and bin_to_gray is function name, its defeated according in bracketEnter the binary code of value, be converted to Gray code and return.

C) GRAY_WIDTH=clogb2 (Temp_1); // compose initial value to GRAY_WIDTH, wait for later step calculating;Clogb2 is function name, and it calculates and return function result of calculation according to the input value in bracket.

D) compare by turn Temp_0 and Temp_1 and record its unequal figure place, if unequal bits number is 1,Arrive now SECTION_INC and GRAY_WIDTH value, finish; Otherwise SECTION_INC=SECTION_INC+1, returns to stepB), and repeating step b) to steps d).

Wherein, function clogb2 (input), its function is to calculate and export the bit wide of input value input, is achieved as follows:

A) result=0; Tmp=input; //tmp is the inner temporary variable of function for this reason, and result is result of calculation;

B) tmp=tmp > > 1; (moving to right one)

c)result＝result+1；

If d) tmp is greater than 0, return to step b) and repeating step b) to steps d); Otherwise the value of output result, finishes.

Function bin_to_gray (bin), this function performance, for input value being converted into Gray code output, is achieved as follows:

A) N=clogb2 (bin); //N is the inner temporary variable of function for this reason, and clogb2 is function mentioned above;

B) gray[k]=bin[k] ^bin[k+1], k=0,1 ... N-2, " ^ " is xor operation; Gray[N-1]=bin[N-1]

C) value of output gray.

Function and the implementation method of a control circuit functional module are below described.

Write and make energy control module:

Writing and making the function of energy control module is that writing of output dual-port memory bank enables control signal write_en. This signalHigh level is effective, uses Combinational logic output, is high level and next self-satisfied signal when writing of FIFO enables input signal wr_enThe full signal full of generation and data writing counter module, write_en output high level, otherwise output low level.

Write address generation module:

The function of write address generation module is the address bus signal that generates and output to dual-port memory bank write portWrite_addr[ADDR_WIDTH-1:0]. This module is to work in the synchronous circuit of writing under clock wr_clk, and reset signal isWr_rst. Write_addr is register output, and reset values is 0. When the rising edge of wr_clk occur and reset signal invalid,Now:

If a) FIFO input write that to enable wr_en be high level, carry out self-satisfied signal generates and data writing counter moduleFull signal full be low level, go to b, otherwise write_addr keep initial value;

If b) write_addr equals DEPTH-1, write_addr output 0, otherwise write_addr is from increasing 1 output.

Write address section Gray code conversion module:

The function of write address section Gray code conversion module is by write address write_addr[ADDR_WIDTH-1:0] addAfter upper curtate increment size SECTION_INC, be converted to Gray code wr_addr_gra[GRAY_WIDTH-1:0] and output.

The realization of asynchronous FIFO such as is generally all directly carried out reading, writing address comparing after the conversion of Gray code at the computing,This has just limited the FIFO degree of depth and has been necessary for 2 power, otherwise in the time that reading, writing address is got back to 0 value by maximum (DEPTH-1), it is rightCan there is multidigit saltus step in the Gray code of answering, only have the advantage of a saltus step thereby lose the adjacent code value of Gray code, brings metastable stateHidden danger. Therefore after write address being added to upper curtate increment size SECTION_INC herein, remake conversion, make the Gray code section of write addressBecome by SECTION_INC to (SECTION_INC+DEPTH-1) from 0 to (DEPTH-1). Wherein, SECTION_INC is for calculatingThe section incrementation parameter going out. Empirical tests, in the time that DEPTH is even number, always can find the such numerical value of SECTION_INC, itsFeature is to make the lattice of the head and the tail numerical value (being SECTION_INC and SECTION_INC+DEPTH-1) of selected sectionThunder code only has 1 difference, thereby the limited problem of the degree of depth while having avoided adopting address directly to change can be arbitrarily DEPTHEven number. If the degree of depth is 10 o'clock, SECTION_INC is 3, can be by 0 (Gray code be 0000) Gray to 9 (Gray code is 1101)Code section adjusts to 3 (0010) to 12 (1010); In addition, in the time of power that depth D EPTH is 2, SECTION_INC is 0.

Write address section Gray code conversion module is to work in the synchronous circuit of writing under clock wr_clk, Gray code wr_Addr_gra[GRAY_WIDTH-1:0] be register output, reset values is SECTION_INC. Be described below:

wr_addr_gra[k]＝(write_addr+SECTION_INC)[k]^(write_addr+SECTION_INC)[k+1], k=0,1 ... GRAY_WIDTH-2, " ^ " is xor operation;

wr_addr_gra[GRAY_WIDTH-1]＝(write_addr+SECTION_INC)[GRAY_WIDTH-1]。

Full signal generates and data writing counter module:

Full signal generates and the function of data writing counter module is the full index signal full of output FIFO, the full letter of programmingNumber prog_full and data writing count value wr_data_count[ADDR_WIDTH-1:0]. When this module is write for working inSynchronous circuit under clock wr_clk, above-mentioned each signal is register output, and reset values is 0.

The vectorial cntw_size_var_int[ADDR_WIDTH:0 of definition in module], its value:

If a) (write_addr+SECTION_INC) be greater than rd_addr_bin, cntw_size_var_int=(write_addr+SECTION_INC)-rd_addr_bin；

B) otherwise (write_addr+SECTION_INC) equal rd_addr_bin if, if full is low level,Cntw_size_var_int=0; If full is high level, cntw_size_var_int=DEPTH.

C) otherwise, cntw_size_var_int=(DEPTH+ (write_addr+SECTION_INC))-rd_addr_bin；

Wherein, rd_addr_bin[GRAY_WIDTH-1:0] for reading ground from what read address section Gray code conversion moduleLocation section gray code signal is synchronized to after wr_clk clock zone through this module inter-sync circuit, be converted into binary system code value toAmount signal.

The condition of the full index signal full output of FIFO high level is data with existing number cntw_size_ in current FIFOVar_int is more than or equal to DEPTH or this write operation will make data with existing number cntw_size_var_int in FIFO be greater thanOr equal DEPTH, otherwise be output low level.

The generation of the full signal prog_full of FIFO programming is also similar to the generation of full signal. The full signal prog_full of programmingThe condition of output high level is that in current FIFO, data with existing number cntw_size_var_int is more than or equal to the full threshold value of programmingParameter PROG_FULL_THRESH or this time write operation will make in FIFO data with existing number cntw_size_var_int be greater than orThe full threshold parameter PROG_FULL_THRESH that equals to programme, otherwise be output low level.

FIFO written data count value wr_data_count (write_addr+SECTION_INC) to be greater than or etc.The value of output (write_addr+SECTION_INC)-rd_addr_bin in the time of rd_addr_bin; Otherwise, output (DEPTH+(write_addr+SECTION_INC) value of)-rd_addr_bin.

Read to make energy control module:

The function of reading to make energy control module be output dual-port memory bank read to enable control signal read_en. This signalHigh level is effective, is 1 when static parameter data pre-reads model selection FIRST_WORD_FT setting value, and read_en output is fixingHigh level, i.e. Chang Youxiao; Otherwise read_en reads to enable rd_en output by FIFO input.

Read address generation module:

The function of reading address generation module is the address bus signal that generates and output to dual-port memory bank read portRead_addr[ADDR_WIDTH-1:0]. This module is to work in the synchronous circuit of reading under clock rd_clk, and reset signal isRd_rst. Read_addr is register output, and reset values is 0. When the rising edge of rd_clk occur and reset signal invalid,Now;

Be high level, generate and readable data counter module from spacing wave if what a) FIFO inputted reads to enable rd_enSpacing wave empty be low level, go to b, otherwise read_addr keep initial value;

If b) read_addr equals DEPTH-1, read_addr output 0, otherwise read_addr is from increasing 1 output.

Read address section Gray code conversion module:

The function of degree address section Gray code conversion module is to read address read_addr[ADDR_WIDTH-1:0] addAfter section increment size SECTION_INC, be converted to Gray code rd_addr_gra[GRAY_WIDTH-1:0] and output.

The realization of asynchronous FIFO such as is generally all directly carried out reading, writing address comparing after the conversion of Gray code at the computing,This has just limited the FIFO degree of depth and has been necessary for 2 power, otherwise in the time that reading, writing address is got back to 0 value by maximum (DEPTH-1), it is rightCan there is multidigit saltus step in the Gray code of answering, only have the advantage of a saltus step thereby lose the adjacent code value of Gray code, brings metastable stateHidden danger. Therefore will read after address adds upper curtate increment size SECTION_INC to remake conversion herein, make to read the Gray code section of addressBecome by SECTION_INC to (SECTION_INC+DEPTH-1) from 0 to (DEPTH-1). Wherein, SECTION_INC is for calculatingThe section incrementation parameter going out. Empirical tests, in the time that DEPTH is even number, always can find the such numerical value of SECTION_INC, itsFeature is to make the lattice of the head and the tail numerical value (being SECTION_INC and SECTION_INC+DEPTH-1) of selected sectionThunder code only has 1 difference, thereby the limited problem of the degree of depth while having avoided adopting address directly to change can be arbitrarily DEPTHEven number. If the degree of depth is 10 o'clock, SECTION_INC is 3, can be by 0 (Gray code be 0000) Gray to 9 (Gray code is 1101)Code section adjusts to 3 (0010) to 12 (1010); In addition, in the time of power that depth D EPTH is 2, SECTION_INC is 0.

Reading address section Gray code conversion module is to work in the synchronous circuit of writing under clock rd_clk, and reset signal isRd_rst. Gray code rd_addr_gra[GRAY_WIDTH-1:0] be register output, reset values is SECTION_INC. RetouchState as follows:

rd_addr_gra[k]＝(read_addr+SECTION_INC)[k]^(read_addr+SECTION_INC)[k+1], k=0,1 ... GRAY_WIDTH-2, " ^ " is xor operation;

rd_addr_gra[GRAY_WIDTH-1]＝(read_addr+SECTION_INC)[GRAY_WIDTH-1]。

Spacing wave generates and readable data counter module:

Spacing wave generates and the function of readable data counter module is the empty index signal empty and readable of output FIFOData counts value rd_data_count[ADDR_WIDTH-1:0]. This module is to work in the synchronous electric of writing under clock rd_clkRoad, reset signal is rd_rst. Above-mentioned each signal is register output, and reset values is 0.

The vectorial cntr_size_var_int[ADDR_WIDTH:0 of definition in module], its value:

A) if wr_addr_bin is greater than (read_addr+SECTION_INC), cntr_size_var_int=wr_addr_bin-(read_addr+SECTION_INC)；

B) otherwise wr_addr_bin equals (read_addr+SECTION_INC) if, if empty is high level,Cntr_size_var_int=0; If empty is low level, cntr_size_var_int=DEPTH.

C) otherwise, cntr_size_var_int=(DEPTH+wr_addr_bin)-(read_addr+SECTION_INC)；

Wherein, wr_addr_bin[GRAY_WIDTH-1:0] for writing ground from write address section Gray code conversion moduleLocation section gray code signal is synchronized to after rd_clk clock zone through this module inter-sync circuit, be converted into binary system code value toAmount signal.

The condition of the empty index signal empty output of FIFO high level is data with existing number cntr_ in current FIFOSize_var_int equal 0 or this time read operation will make data with existing number cntr_size_var_int in FIFO equal 0, noIt is output low level.

In FIFO, readable data count value rd_data_count is more than or equal to (read_addr+ at wr_addr_binSECTION_INC) time, export the value of wr_addr_bin-(read_addr+SECTION_INC); Otherwise, output (DEPTH+wr_Addr_bin)-value (read_addr+SECTION_INC).

Claims (3)

1. a parameterized Universal FIFO control method, is characterized in that: described parameterized Universal FIFO control method bagDraw together following steps:

1) Universal FIFO control circuit is inputted to static input parameter;

2) shine upon the required built-in variable of accomplished fifo control circuit according to static input parameter;

3) according to step 2) the required built-in variable of fifo control circuit that produces realizes required Universal FIFO control circuit;

Described static input parameter comprises FIFO depth D EPTH, the full threshold value PROG_FULL_THRESH of programming and data pre-headModel selection FIRST_WORD_FT;

Described FIFO depth D EPTH realizes resource to allow any even number in limit;

The setting value of the full threshold value PROG_FULL_THRESH of described programming is the positive integer that is less than FIFO depth D EPTH;

The setting value of described data pre-head model selection FIRST_WORD_FT is 1 or 0; Described data pre-head model selectionThe setting value of FIRST_WORD_FT is 1 o'clock, represents to select pre-reading mode, on data fifo output bus DOUT, always pre-reads FIFOCurrent first data in going out; The setting value of described data pre-head model selection FIRST_WORD_FT is 0 o'clock, represents to select non-Pre-reading mode, only have when read enable signal RD_EN effective after, on data-out bus DOUT, just export current first data;

Described fifo control circuit built-in variable comprises dual-port bank-address width ADDR_WIDTH, data writing counterBit wide WR_DATA_COUNT_WIDTH, readable data counter bit wide RD_DATA_COUNT_WIDTH, read/write address Gray codeConversion section increment SECTION_INC and section Gray code data bit width GRAY_WIDTH;

Described dual-port bank-address width ADDR_WIDTH is integer value, and what about beam control circuit generated reads address read_The bus bit wide of addr, write address write_addr; When generation realizes the necessary dual-port memory bank of complete fifo circuit,Also for determining its size;

Said write data counter bit wide WR_DATA_COUNT_WIDTH is integer value, and what about beam control circuit was exported writesThe bit wide of data number count value;

Described readable data counter bit wide RD_DATA_COUNT_WIDTH is integer value, and it is readable that about beam control circuit is exportedThe bit wide of data number count value;

Described read/write address Gray code conversion section increment SECTION_INC is integer value, carries out lattice for retraining read/write addressThe starting point of selected numerical value section when the conversion of thunder code;

Described section Gray code data bit width GRAY_WIDTH is integer value, for retraining the data bit width of section Gray code;

Described step 2) mapping relations be:

The specific implementation of described dual-port bank-address width ADDR_WIDTH show that mode is:

ADDR_WIDTH=clogb2 (DEPTH); Wherein: clogb2 is function name, and described clogb2 is according to the input in bracketValue, calculates and return function result of calculation; Described DEPTH is FIFO depth D EPTH;

Said write data counter bit wide WR_DATA_COUNT_WIDTH and readable data counter bit wide RD_DATA_COUNT_WIDTH meets following condition:

WR_DATA_COUNT_WIDTH＝RD_DATA_COUNT_WIDTH＝ADDR_WIDTH；

The tool of described read/write address Gray code conversion section increment SECTION_INC and section Gray code bit wide GRAY_WIDTHBody show that mode is:

A) SECTION_INC=0; Compose initial value to SECTION_INC, wait for later step calculating;

b)Temp_0＝bin_to_gray(SECTION_INC)；Temp_1＝bin_to_gray(SECTION_INC+DEPTH); Described Temp_0 and Temp_1 are the temporary variable of definition, and bin_to_gray is function name, described bin_to_grayAccording to the binary code of the input value in bracket, be converted to Gray's agate and return;

C) GRAY_WIDTH=clogb2 (Temp_1); Compose initial value to GRAY_WIDTH, wait for later step calculating; DescribedClogb2 is function name, and described clogb2, according to the input value in bracket, calculates and return function result of calculation;

D) compare by turn Temp_0 and Temp_1 and record its unequal figure place, if unequal bits number is 1, obtaining thisTime SECTION_INC and GRAY_WIDTH value, and finish; Otherwise SECTION_INC=SECTION_INC+1, returns to stepB), and repeating step b) to steps d);

Described function clogb2 (input) is the bit wide of calculating and export input value input, and its specific implementation is:

A) result=0; Tmp=input; Tmp is the inner temporary variable of function for this reason, and result is result of calculation;

b)tmp＝tmp>>1；

c)result＝result+1；

If d) tmp is greater than 0, returns to step b) and repeat b) to steps d); Otherwise the value of output result, finishes;

Input value is converted into Gray code output by described function bin_to_gray (bin), and specific implementation is:

A) N=clogb2 (bin); N is the inner temporary variable of function for this reason;

B) gray[k]=bin[k] ^bin[k+1], k=0,1 ... N – 2, described ^ is xor operation; Gray[N-1]=bin[N-1]

C) value of output gray.

2. parameterized Universal FIFO control method according to claim 1, is characterized in that: described Universal FIFO controlCircuit comprises writing makes energy control module, write address generation module, write address section Gray code conversion module, full signal generate and writeEnter data counter module, read to make energy control module, read address generating module, read address section Gray code conversion module, empty letterNumber generate and readable data counter module.

3. parameterized Universal FIFO control method according to claim 2, is characterized in that:

To the described specific implementation that makes energy control module implement to control of writing be: writing and making the function of energy control module is that output is twoWriting of port memory bank enables control signal write_en; This signal high level is effective, uses Combinational logic output, when FIFO controlThe writing of circuit processed enables input signal wr_en to be high level and to come that self-satisfied signal generates and the expiring of data writing counter moduleSignal full, write_en output high level, otherwise output low level;

The specific implementation that write address generation module is implemented to control is: the function of write address generation module is to generate and exportTo the address bus signal write_addr[ADDR_WIDTH-1:0 of dual-port memory bank write port]; Described write address generates mouldPiece is to work in the synchronous circuit of writing under clock wr_clk, and reset signal is wr_rst; Write_addr is register output,Reset values is 0; When the rising edge of wr_clk occur and reset signal invalid, now:

If a) fifo control circuit input write that to enable wr_en be high level, carry out self-satisfied signal generates and data writing counterThe full signal full of module is low level, go to step b), otherwise write_addr keeps initial value;

If b) write_addr equals DEPTH-1, write_addr output 0, otherwise write_addr is from increasing 1 output;

The specific implementation that write address section Gray code conversion module is implemented to control is: write address section Gray code conversion mouldThe function of piece is by write address write_addr[ADDR_WIDTH-1:0] be converted to after adding upper curtate increment size SECTION_INCGray code wr_addr_gra[GRAY_WIDTH-1:0] and output; Described SECTION_INC is the section increment ginseng calculatingNumber;

Write address section Gray code conversion module is to work in the synchronous circuit of writing under clock wr_clk, Gray code wr_addr_Gra[GRAY_WIDTH-1:0] be register output, reset values is SECTION_INC; Be described below:

wr_addr_gra[k]＝(write_addr+SECTION_INC)[k]^(write_addr+SECTION_INC)[k+1], k=0,1 ... GRAY_WIDTH – 2, described ^ is xor operation;

wr_addr_gra[GRAY_WIDTH-1]＝(write_addr+SECTION_INC)[GRAY_WIDTH-1]；

To the specific implementation that full signal generates and data writing counter module is implemented to control be: full signal generates and writesThe function of data counter module is the full index signal full of output FIFO, the full signal prog_full of programming and data writingCount value wr_data_count[ADDR_WIDTH-1:0]; This module is to work in the synchronous circuit of writing under clock wr_clk, onState each signal and be register output, reset values is 0;

Described full signal generates and the vectorial cntw_size_var_int[ADDR_WIDTH of the interior definition of data writing counter module:0], its value:

If a) (write_addr+SECTION_INC) be greater than rd_addr_bin, cntw_size_var_int=(write_addr+SECTION_INC)-rd_addr_bin；

B) otherwise (write_addr+SECTION_INC) equal rd_addr_bin if, if full is low level, cntw_Size_var_int=0; If full is high level, cntw_size_var_int=DEPTH;

C) otherwise, cntw_size_var_int=(DEPTH+ (write_addr+SECTION_INC))-rd_addr_bin;

Wherein, rd_addr_bin[GRAY_WIDTH-1:0] be from the address area of reading of reading address section Gray code conversion moduleSection gray code signal is synchronized to after wr_clk clock zone through this module inter-sync circuit, is converted into the vector letter of binary system code valueNumber;

The condition of the full index signal full output of FIFO high level is data with existing number cntw_size_var_ in current FIFOInt be more than or equal to DEPTH or this time write operation will make in FIFO data with existing number cntw_size_var_int be greater than or etc.In DEPTH, otherwise it is output low level;

The generation of the full signal prog_full of FIFO programming is also similar to the generation of full signal; The full signal prog_full output of programmingThe condition of high level is that in current FIFO, data with existing number cntw_size_var_int is more than or equal to the full threshold parameter of programmingPROG_FULL_THRESH or this time write operation will make data with existing number cntw_size_var_int in FIFO be more than or equal toThe full threshold parameter PROG_FULL_THRESH of programming, otherwise be output low level;

FIFO written data count value wr_data_count at (write_addr+SECTION_INC) to being more than or equal toThe value of output (write_addr+SECTION_INC)-rd_addr_bin when rd_addr_bin; Otherwise, output (DEPTH+(write_addr+SECTION_INC) value of)-rd_addr_bin;

Make the specific implementation that energy control module is controlled be to reading: reading to make the function of energy control module is output dual-portMemory bank read to enable control signal read_en; This signal high level is effective, when static parameter data pre-reads model selectionFIRST_WORD_FT setting value is 1, fixing high level, i.e. Chang Youxiao of read_en output; Otherwise read_en inputs FIFORead to enable rd_en output;

To reading the specific implementation that address generation module controls be: the function of reading address generation module is to generate and exportTo the address bus signal read_addr[ADDR_WIDTH-1:0 of dual-port memory bank read port]; This module is read for working inSynchronous circuit under clock rd_clk, reset signal is rd_rst; Read_addr is register output, and reset values is 0; WhenRising edge generation and the reset signal of rd_clk are invalid, now:

If a) FIFO input read enable rd_en and be high level, generate and the sky of readable data counter module from spacing waveSignal empty is low level, go to step b), otherwise read_addr keeps initial value;

If b) read_addr equals DEPTH-1, read_addr output 0, otherwise read_addr is from increasing 1 output;

To reading the specific implementation that address section Gray code conversion module controls be: read address section Gray code conversion mouldThe function of piece is to read address read_addr[ADDR_WIDTH-1:0] be converted to after adding upper curtate increment size SECTION_INCGray code rd_addr_gra[GRAY_WIDTH-1:0] and output; Described SECTION_INC is the section increment ginseng calculatingNumber;

Reading address section Gray code conversion module is to work in the synchronous circuit of writing under clock rd_clk, and reset signal is rd_Rst; Gray code rd_addr_gra[GRAY_WIDTH-1:0] be register output, reset values is SECTION_INC, describesAs follows:

rd_addr_gra[k]＝(read_addr+SECTION_INC)[k]^(read_addr+SECTION_INC)[k+1]，k=0,1 ... GRAY_WIDTH – 2, described ^ is xor operation;

rd_addr_gra[GRAY_WIDTH-1]＝(read_addr+SECTION_INC)[GRAY_WIDTH-1]；

To the specific implementation that spacing wave generates and readable data counter module is controlled be: spacing wave generates and be readableThe function of data counter module is the empty index signal empty of output FIFO and readable data count value rd_data_count[ADDR_WIDTH-1:0], this module is to work in the synchronous circuit of writing under clock rd_clk, reset signal is rd_rst; Above-mentionedEach signal is register output, and reset values is 0;

The vectorial cntr_size_var_int[ADDR_WIDTH:0 of definition in module], its value:

If wr_addr_bin is greater than (read_addr+SECTION_INC), cntr_size_var_int=wr_addr_bin-(read_addr+SECTION_INC)；

If otherwise wr_addr_bin equals (read_addr+SECTION_INC), if empty is high level, cntr_size_Var_int=0; If empty is low level, cntr_size_var_int=DEPTH;

Otherwise, cntr_size_var_int=(DEPTH+wr_addr_bin)-(read_addr+SECTION_INC);

Wherein, wr_addr_bin[GRAY_WIDTH-1:0] be the write address district from write address section Gray code conversion moduleSection gray code signal is synchronized to after rd_clk clock zone through this module inter-sync circuit, is converted into the vector letter of binary system code valueNumber;

The condition of the empty index signal empty output of FIFO high level is data with existing number cntr_size_ in current FIFOVar_int equal 0 or this time read operation will make data with existing number cntr_size_var_int in FIFO equal 0, otherwise defeatedGo out low level;

In FIFO, readable data count value rd_data_count is more than or equal to (read_addr+ at wr_addr_binSECTION_INC) time, export the value of wr_addr_bin-(read_addr+SECTION_INC); Otherwise, output (DEPTH+wr_Addr_bin)-value (read_addr+SECTION_INC).