CN110888622A - Method, device, equipment and medium for realizing asynchronous FIFO (first in first out) with any depth - Google Patents
Method, device, equipment and medium for realizing asynchronous FIFO (first in first out) with any depth Download PDFInfo
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Abstract
The application discloses a method, a device, equipment and a medium for realizing asynchronous FIFO with any depth. The method at least comprises the following steps: when writing data by using the write address, the write address and the corresponding binary write pointer are respectively added with 1, the write address is wound back according to the depth N of the asynchronous FIFO, and the binary write pointer is wound according to 2nWound back, 2nAnd the N is a positive integer, a Gray code read pointer synchronized across clock domains from a read end is received, binary conversion is carried out to obtain a binary read pointer, and asynchronous FIFO fullness judgment is carried out according to the binary read pointer and the binary write pointer. According to the method and the device, the write address and the corresponding binary write pointer are wrapped back in a differentiated mode, and any depth asynchronous FIFO can be achieved.
Description
Technical Field
The present application relates to the field of chip technologies, and in particular, to a method, an apparatus, a device, and a medium for implementing any depth asynchronous First In First Out (FIFO).
Background
Asynchronous FIFOs are very common in modern Application Specific Integrated Circuit (ASIC)/System On a Chip (SOC) designs. Especially in case of more power consumption emphasis in ASIC/SOC design, different modules in the architecture need to work asynchronously. To ensure the correct function, an asynchronous FIFO needs to be added between different modules.
The asynchronous FIFO is provided with a reading end, a writing end and a storage module, the respective clock domains of the reading end and the writing end are asynchronous, the writing end writes data into the storage module in sequence in the writing clock domain, and the reading end reads the data written into the storage module in the reading clock domain according to the first-in first-out rule.
In the prior art, the ranges of write addresses and read addresses are specified according to gray code coding requirements, so that clock domain crossing address synchronization is performed based on gray codes, and further asynchronous FIFO empty-full judgment is performed.
However, since gray code encoding requires the total number of codes to be a positive integer power of 2, e.g., 2, 4, 8, 16, etc., the depth of the asynchronous FIFO that can be implemented is correspondingly limited.
Disclosure of Invention
The embodiment of the application provides a method, a device, equipment and a medium for realizing asynchronous FIFO with any depth, which are used for solving the following technical problems in the prior art: the depth of the asynchronous FIFO that can be realized today based on gray codes is limited.
The embodiment of the application adopts the following technical scheme:
a method of implementing an arbitrary depth asynchronous FIFO, comprising:
when writing data by using a write address, adding 1 to the write address and a binary write pointer corresponding to the write address respectively, wherein the write address is wound back according to the depth N of the asynchronous FIFO, and the binary write pointer is wound according to 2nWound back, 2n≥N，N is a positive integer;
receiving a Gray code reading pointer synchronized across clock domains from a reading end, and performing binary conversion to obtain a binary reading pointer;
and according to the binary read pointer and the binary write pointer, performing asynchronous FIFO fullness judgment.
Optionally, the method further comprises:
performing Gray code conversion on the binary writing pointer to obtain a Gray code writing pointer;
synchronizing the Gray code write pointer to a read end across clock domains to perform binary conversion to obtain a binary write pointer, and performing asynchronous FIFO empty judgment by the read end according to the binary write pointer and a local binary read pointer of the read end;
when a read end reads data by using a read address, the read address and the corresponding binary read pointer are respectively added with 1, the read address is wound back according to the depth N of the asynchronous FIFO, and the binary read pointer is wound according to 2nAnd the wrapped Gray code reading pointer is obtained by performing Gray code conversion on the binary system reading pointer.
Optionally, the performing asynchronous FIFO full determination according to the binary read pointer and the binary write pointer specifically includes:
and if the difference between the binary write pointer and the binary read pointer is equal to N, judging that the asynchronous FIFO is full.
Optionally, a time delay exists between the binary write pointer obtained by clock domain crossing synchronization and the local binary write pointer of the write end; and the number of the first and second groups,
compared with a local binary read pointer at a read end, the binary read pointer obtained by clock domain crossing synchronization has time delay.
Another method for implementing an arbitrary depth asynchronous FIFO, comprising:
when reading data by using a read address, adding 1 to the read address and a binary read pointer corresponding to the read address respectively, wherein the read address is wound back according to the depth N of the asynchronous FIFO, and the binary read pointer is wound according to 2nWound back, 2nMore than or equal to N, wherein N is a positive integer;
receiving a Gray code write pointer synchronized across clock domains from a write end, and performing binary conversion to obtain a binary write pointer;
and performing asynchronous FIFO empty judgment according to the binary read pointer and the binary write pointer.
Optionally, the method further comprises:
performing Gray code conversion on the binary system reading pointer to obtain a Gray code reading pointer;
synchronizing the Gray code reading pointer to a writing end across clock domains to perform binary conversion to obtain a binary reading pointer, wherein the binary reading pointer is used for the writing end to perform asynchronous FIFO fullness judgment according to the binary reading pointer and a local binary writing pointer of the writing end;
when a write end uses a write address to write data, the write address and the corresponding binary write pointer are respectively added with 1, the write address is wound back according to the depth N of the asynchronous FIFO, and the binary write pointer is wound according to 2nAnd the wrapped Gray code writing pointer is obtained by performing Gray code conversion on the binary writing pointer.
Optionally, the performing asynchronous FIFO empty determination according to the binary read pointer and the binary write pointer specifically includes:
and if the difference between the binary write pointer and the binary read pointer is equal to 0, judging that the asynchronous FIFO is empty.
Optionally, a time delay exists between the binary write pointer obtained by clock domain crossing synchronization and the local binary write pointer of the write end; and the number of the first and second groups,
compared with a local binary read pointer at a read end, the binary read pointer obtained by clock domain crossing synchronization has time delay.
An apparatus for implementing an arbitrary depth asynchronous FIFO, comprising:
a write address operation module, which adds 1 to the write address and the corresponding binary write pointer when writing data by using the write address, wherein the write address is wrapped according to the depth N of the asynchronous FIFO, and the binary write pointer is wrapped according to 2nWound back, 2nMore than or equal to N, wherein N is a positive integer;
the read pointer conversion module receives a Gray code read pointer synchronized across clock domains from a read end and performs binary conversion to obtain a binary read pointer;
and the full judgment module is used for carrying out asynchronous FIFO full judgment according to the binary read pointer and the binary write pointer.
Optionally, the apparatus further comprises:
the writing pointer synchronization module is used for carrying out Gray code conversion on the binary writing pointer to obtain a Gray code writing pointer;
synchronizing the Gray code write pointer to a read end across clock domains to perform binary conversion to obtain a binary write pointer, and performing asynchronous FIFO empty judgment by the read end according to the binary write pointer and a local binary read pointer of the read end;
when a read end reads data by using a read address, the read address and the corresponding binary read pointer are respectively added with 1, the read address is wound back according to the depth N of the asynchronous FIFO, and the binary read pointer is wound according to 2nAnd the wrapped Gray code reading pointer is obtained by performing Gray code conversion on the binary system reading pointer.
Optionally, the full determination module performs asynchronous FIFO full determination according to the binary read pointer and the binary write pointer, and specifically includes:
and if the difference between the binary write pointer and the binary read pointer is equal to N, the full judgment module judges that the asynchronous FIFO is full.
Optionally, a time delay exists between the binary write pointer obtained by clock domain crossing synchronization and the local binary write pointer of the write end; and the number of the first and second groups,
compared with a local binary read pointer at a read end, the binary read pointer obtained by clock domain crossing synchronization has time delay.
Another apparatus for implementing an asynchronous FIFO of arbitrary depth, comprising:
a read address operation module for reading the read address and the read address every time when the read address is used to read dataAdding 1 to the corresponding binary read pointer respectively, wherein the read address is wound back according to the depth N of the asynchronous FIFO, and the binary read pointer is wound according to 2nWound back, 2nMore than or equal to N, wherein N is a positive integer;
the write pointer conversion module receives a Gray code write pointer synchronized across clock domains from a write end and performs binary conversion to obtain a binary write pointer;
and the empty judgment module is used for carrying out asynchronous FIFO empty judgment according to the binary read pointer and the binary write pointer.
Optionally, the apparatus further comprises:
the read pointer synchronization module is used for carrying out Gray code conversion on the binary read pointer to obtain a Gray code read pointer;
synchronizing the Gray code reading pointer to a writing end across clock domains to perform binary conversion to obtain a binary reading pointer, wherein the binary reading pointer is used for the writing end to perform asynchronous FIFO fullness judgment according to the binary reading pointer and a local binary writing pointer of the writing end;
when a write end uses a write address to write data, the write address and the corresponding binary write pointer are respectively added with 1, the write address is wound back according to the depth N of the asynchronous FIFO, and the binary write pointer is wound according to 2nAnd the wrapped Gray code writing pointer is obtained by performing Gray code conversion on the binary writing pointer.
Optionally, the empty determination module performs an asynchronous FIFO empty determination according to the binary read pointer and the binary write pointer, and specifically includes:
and if the difference between the binary write pointer and the binary read pointer is equal to 0, the null determination module determines that the asynchronous FIFO is null.
Optionally, a time delay exists between the binary write pointer obtained by clock domain crossing synchronization and the local binary write pointer of the write end; and the number of the first and second groups,
compared with the binary read pointer acquired by the read end, the binary read pointer acquired by the clock domain crossing synchronization has time delay.
An apparatus for implementing an arbitrary depth asynchronous FIFO, comprising:
at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to enable the at least one processor to:
when writing data by using a write address, adding 1 to the write address and a binary write pointer corresponding to the write address respectively, wherein the write address is wound back according to the depth N of the asynchronous FIFO, and the binary write pointer is wound according to 2nWound back, 2nMore than or equal to N, wherein N is a positive integer;
receiving a Gray code reading pointer synchronized across clock domains from a reading end, and performing binary conversion to obtain a binary reading pointer;
and according to the binary read pointer and the binary write pointer, performing asynchronous FIFO fullness judgment.
Another apparatus for implementing an arbitrary depth asynchronous FIFO, comprising:
at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to enable the at least one processor to:
when reading data by using a read address, adding 1 to the read address and a binary read pointer corresponding to the read address respectively, wherein the read address is wound back according to the depth N of the asynchronous FIFO, and the binary read pointer is wound according to 2nWound back, 2nMore than or equal to N, wherein N is a positive integer;
receiving a Gray code write pointer synchronized across clock domains from a write end, and performing binary conversion to obtain a binary write pointer;
and performing asynchronous FIFO empty judgment according to the binary read pointer and the binary write pointer.
A non-volatile computer storage medium implementing an arbitrary depth asynchronous FIFO, storing computer-executable instructions configured to:
when writing data by using a write address, adding 1 to the write address and a binary write pointer corresponding to the write address respectively, wherein the write address is wound back according to the depth N of the asynchronous FIFO, and the binary write pointer is wound according to 2nWound back, 2nMore than or equal to N, wherein N is a positive integer;
receiving a Gray code reading pointer synchronized across clock domains from a reading end, and performing binary conversion to obtain a binary reading pointer;
and according to the binary read pointer and the binary write pointer, performing asynchronous FIFO fullness judgment.
Another non-volatile computer storage medium implementing an arbitrary depth asynchronous FIFO stores computer-executable instructions configured to:
when reading data by using a read address, adding 1 to the read address and a binary read pointer corresponding to the read address respectively, wherein the read address is wound back according to the depth N of the asynchronous FIFO, and the binary read pointer is wound according to 2nWound back, 2nMore than or equal to N, wherein N is a positive integer;
receiving a Gray code write pointer synchronized across clock domains from a write end, and performing binary conversion to obtain a binary write pointer;
and performing asynchronous FIFO empty judgment according to the binary read pointer and the binary write pointer.
The embodiment of the application adopts at least one technical scheme which can achieve the following beneficial effects: by wrapping the write address and the read address with the corresponding binary write pointer and the binary read pointer in a differentiated manner, cross-clock-domain synchronization between a read end and a write end is performed by using the Gray code write pointer corresponding to the binary write pointer and the Gray code read pointer corresponding to the binary read pointer, asynchronous FIFO empty-full judgment is performed by using the binary write pointer and the binary read pointer, and the binary write pointer and the binary read pointer are both determined according to 2nWrapping around, therefore, is beneficial to ensuring the correctness of the empty and full judgment result and also enables the asynchronous FIFOThe depth is not limited and may be any depth.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a schematic flow chart of a method for implementing an asynchronous FIFO of arbitrary depth according to some embodiments of the present application;
FIG. 2 is a schematic flow chart diagram of another method for implementing an arbitrary depth asynchronous FIFO according to some embodiments of the present application;
fig. 3 is a schematic structural diagram of the asynchronous FIFO in a practical application scenario provided by some embodiments of the present application;
fig. 4a is a schematic structural diagram of a write end of the asynchronous FIFO in a practical application scenario according to some embodiments of the present application;
fig. 4b is a schematic structural diagram of a read end of the asynchronous FIFO in a practical application scenario according to some embodiments of the present application;
fig. 5a is a schematic diagram illustrating a principle of performing asynchronous FIFO full determination in a practical application scenario according to some embodiments of the present application;
fig. 5b is a schematic diagram illustrating a principle of performing asynchronous FIFO empty determination in a practical application scenario according to some embodiments of the present application;
FIG. 6 is a schematic diagram of an apparatus for implementing an asynchronous FIFO of any depth according to the embodiment of the present application and corresponding to the apparatus of FIG. 1;
FIG. 7 is a schematic diagram of an apparatus for implementing an asynchronous FIFO of any depth according to the embodiment of the present application and corresponding to FIG. 2;
FIG. 8 is a schematic diagram of an apparatus for implementing an asynchronous FIFO of any depth according to some embodiments of the present application and corresponding to FIG. 1;
fig. 9 is a schematic diagram of an apparatus for implementing an arbitrary depth asynchronous FIFO according to some embodiments of the present application, and corresponds to fig. 2.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail and completely with reference to the following specific embodiments of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the prior art, because the total number of codes required for gray code encoding is a positive integer power of 2, correspondingly, the depth of an asynchronous FIFO that can be realized is also a positive integer power of 2, and based on some improved schemes, an asynchronous FIFO with an even depth may also be realized. The scheme of this application then can realize the asynchronous FIFO of arbitrary degree of depth, realizes simply and can not add redundant degree of depth, helps saving the data storage space of chip, improves storage space's utilization ratio. The scheme of the present application is explained in detail below.
The asynchronous FIFO is mainly composed of a write terminal (also called write controller), a read terminal (also called read controller) and a memory module, and in addition, there may be some additional functional modules. The write end controls the writing of data by executing a preset write logic; the reading end controls the reading of data by executing preset reading logic; the storage module provides a storage space for data reading and writing; the write end and the read end respectively adopt different clocks, namely, respectively are in different clock domains.
The key for realizing the asynchronous FIFO is that a write end carries out full judgment (whether the write end is full) and a read end carries out empty judgment (whether the read end is empty), and the correct execution of the full judgment and the empty judgment can ensure the correct reading and writing of data in the asynchronous FIFO. Based on this, the description will be made from the viewpoint of the write end and the read end, respectively.
Fig. 1 is a flowchart illustrating a method for implementing an asynchronous FIFO of any depth according to some embodiments of the present application. The execution body of the flow may include a write end, and may also include some additional functional modules, such as a functional module for cross-clock synchronization, and the like, and of course, these modules may also be directly included in the write end.
The process in fig. 1 may include the following steps:
s102: when writing data by using a write address, adding 1 to the write address and a binary write pointer corresponding to the write address respectively, wherein the write address is wound back according to the depth N of the asynchronous FIFO, and the binary write pointer is wound according to 2nWound back, 2nN is more than or equal to N, and N is a positive integer.
The asynchronous FIFO is read and written in a first-in first-out queue mode, the length of the queue is the depth N of the asynchronous FIFO, data can be written in when the asynchronous FIFO is in a non-full state, and the data can be read out when the asynchronous FIFO is in a non-empty state.
In some embodiments of the present application, data is written directly using a write address, where the write address indicates a current position in a queue, data is written sequentially from the head of the queue to each position in sequence at the tail of the queue (write address plus 1 indicates that the current position is changed to the next position), data is written at one position in the queue at a time, and after the tail of the queue is reached, data is written wrapping around the head of the queue (i.e., wrapping around according to depth N); after data is written in each time, asynchronous FIFO full judgment can be carried out, if the data is in a non-full state, the data can be continuously written in the next time, otherwise, the receipt needs to be read by a reading end.
In some embodiments of the present application, the write address has a binary write pointer and a gray code write pointer corresponding thereto, the binary write pointer is represented by a binary code, the gray code write pointer is represented by a gray code, and the binary write pointer and the gray code write pointer can be mutually converted according to a conversion rule between the binary code and the gray code. The binary write pointer is not directly used for writing data, but is matched with the change of a write address to synchronize change cycle counting, and then the binary write pointer is correctly synchronized to a read end across clock domains based on the corresponding Gray code write pointer, wherein the binary write pointer is 2nThe wraparound corresponds toThe adjacent values of the Gray code writing pointer are only different from each other by 1 bit so as to ensure correct synchronization.
Further, to reduce redundancy of the Gray code write pointer, 2 may be usednIs not less than N, and the difference with N is as small as possible. Preferably, 2 can be usedn≥N＞2n-1For example, if N is 3, 2 may be usedn＝22If N is 4, then 2 may be usedn＝23When N is 8, 2 may be usedn＝23＝8。
In some embodiments of the present application, local to a write end, a binary write pointer can match with a change of a write address, and a cycle count of the synchronous change can directly obtain the binary write pointer (referred to as a local binary write pointer of the write end), while for a read end, a gray code write pointer needs to be obtained from the write end across clock domain synchronization, and then the gray code write pointer is converted to obtain the binary write pointer (referred to as a binary write pointer obtained through clock domain crossing synchronization).
S104: and receiving a Gray code reading pointer synchronized across clock domains from a reading end, and performing binary conversion to obtain a binary reading pointer.
In some embodiments of the present application, similar to the write end, the read end may also have a corresponding read address, a gray code read pointer, and a binary read pointer, and the relationship between the read address, the gray code read pointer, and the binary read pointer may refer to the description of the write end above. It should be noted that, even if the difference between writing and reading is not considered, the scheme of the reading end and the scheme of the writing end may still be inconsistent, however, whichever scheme is adopted, the reading end can at least provide the gray code read pointer to the writing end so that the writing end obtains the corresponding binary read pointer.
S106: and according to the binary read pointer and the binary write pointer, performing asynchronous FIFO fullness judgment.
In some embodiments of the present application, although the binary write pointer and the write address may wrap around according to different values, since the binary write pointer and the write address change synchronously, the binary write pointer can still reflect the relative change of the write address, and similarly, the binary read pointer can still reflect the relative change of the read address. From these two relative changes it is possible to determine the absolute difference between the write address and the read address, from which a full decision and an empty decision can be made.
Further, since the binary code can more conveniently support the calculation of the difference value by the subtraction than the gray code, the determination can be made by the subtraction using the corresponding binary write pointer and binary read pointer instead of using the gray code write pointer and gray code read pointer.
Based on this, for the write end, an asynchronous FIFO full determination may be made based on the binary read pointer and the binary write pointer, and similarly, for the read end, an asynchronous FIFO empty determination may be made based on the binary read pointer and the binary write pointer, with specific determination conditions differing depending on the actual relationship between the binary read pointer and the binary write pointer.
By the method of fig. 1, the write address and the corresponding binary write pointer are wrapped differently, the gray code write pointer corresponding to the binary write pointer is used to perform clock domain crossing synchronization between the read end and the write end, and then the binary write pointer and the binary read pointer are used to perform asynchronous FIFO full determination, and the binary read pointer can be 2nThe wrap-around is beneficial to ensuring the correctness of the full judgment result and also ensures that the depth of the asynchronous FIFO is not limited and can be any depth.
Based on the same idea, some embodiments of the present application further provide a flow chart diagram of another method for implementing an asynchronous FIFO with an arbitrary depth, as shown in fig. 2. The execution body of the flow may include a read end, and may also include some additional functional modules, such as a functional module for synchronization across clocks, and the like, and of course, these modules may also be directly included in the read end. Fig. 2 is a scheme consistent with fig. 1, and fig. 2 can be understood with reference to the description of fig. 1 above.
The process in fig. 2 may include the following steps:
s202: when reading data by using a read address, the read address and a corresponding binary read pointer are respectively added with 1, the read address is wound back according to the depth N of the asynchronous FIFO, and the binary inputThe read pointer is according to 2nWound back, 2nN is more than or equal to N, and N is a positive integer.
S204: and receiving a Gray code write pointer synchronized across clock domains from a write end, and performing binary conversion to obtain a binary write pointer.
S206: and performing asynchronous FIFO empty judgment according to the binary read pointer and the binary write pointer.
By the method of fig. 2, the read address and the corresponding binary read pointer are wrapped differently, the gray code read pointer corresponding to the binary read pointer is used to perform clock domain crossing synchronization between the read end and the write end, and then the binary write pointer and the binary read pointer are used to perform asynchronous FIFO empty determination, and the binary write pointer may be 2nThe wrap-around is beneficial to ensuring the correctness of the empty judgment result and ensuring that the depth of the asynchronous FIFO is not limited and can be any depth.
Assuming that the write side and the read side respectively adopt the schemes of fig. 1 and fig. 2 (that is, adopt the consistent scheme), the difference between the binary write pointer and the binary read pointer can be directly used as the empty-full determination condition. Specifically, for example, assuming that the actual value ranges of the binary write pointer and the binary read pointer are aligned, if the difference between the binary write pointer and the binary read pointer is equal to N, it may be determined that the asynchronous FIFO is full, and if the difference between the binary write pointer and the binary read pointer is equal to 0 (that is, the two are equal), it may be determined that the asynchronous FIFO is empty.
It should be noted that, in practical applications, the write side and the read side may also adopt an inconsistent scheme, where one side uses the scheme in fig. 1 or fig. 2, an asynchronous FIFO of any depth may be implemented, and if the inconsistent scheme is adopted, the empty-full determination condition may also be changed correspondingly.
In some embodiments of the present application, for the method of fig. 1, it may further be performed: performing Gray code conversion on the binary system write pointer to obtain a Gray code write pointer, synchronizing the Gray code write pointer to the read end across clock domains to perform binary system conversion to obtain a binary system write pointer, and using the binary system write pointer to the read end according to the binary system write pointerAnd carrying out asynchronous FIFO empty judgment by using a pointer and a binary read pointer acquired locally at a read end. Assuming that the write end and the read end adopt the above-mentioned consistent scheme, the read end can add 1 to the read address and its corresponding binary read pointer when reading data by using the read address, the read address is wrapped according to the depth N of the asynchronous FIFO, the binary read pointer is 2nAnd the wrapped Gray code reading pointer is obtained by carrying out Gray code conversion on the binary system reading pointer.
Similarly, for the method of fig. 2, it may also be performed: and performing Gray code conversion on the binary system read pointer to obtain a Gray code read pointer, synchronizing the Gray code read pointer to the write end across a clock domain to perform binary conversion to obtain a binary system read pointer, and performing asynchronous FIFO fullness judgment by the write end according to the binary system read pointer and the binary system write pointer locally acquired at the write end. Assuming that the read end and the write end adopt the above-mentioned consistent scheme, the write end can add 1 to the write address and the corresponding binary write pointer thereof, respectively, when writing data by using the write address, the write address wraps around according to the depth N of the asynchronous FIFO, and the binary write pointer wraps around according to 2nAnd the wrap-around Gray code writing pointer is obtained by carrying out Gray code conversion on the binary writing pointer.
In some embodiments of the present application, it has been mentioned above that, for the write side, a binary write pointer local to the write side can be obtained, and the read side also obtains the binary write pointer through clock domain crossing synchronization. The two binary write pointers are effectively the same parameter. However, in practical applications, because clock domain crossing synchronization needs to be performed, there may be a time delay between the binary write pointer obtained through clock domain crossing synchronization and the local binary write pointer of the write end, and the values of the two may be different at the same time.
Similarly, the binary read pointer obtained by clock domain crossing synchronization may have a time delay compared to the local binary read pointer of the read end.
Based on the foregoing description, it is more intuitive that some embodiments of the present application further provide a schematic structure of the asynchronous FIFO in a practical application scenario, where the structure is omitted and only a part of the main modules are listed, as shown in fig. 3.
In fig. 3, the write end of the asynchronous FIFO writes data into the memory module using a write address, and the read end reads data from the memory module using a read address; the write end and the read end respectively adopt own clocks, and carry out clock domain crossing synchronization through logic comprising a plurality of triggers and a pointer in a gray code form so as to obtain the pointer in a binary form, thereby being convenient for the write end to carry out full judgment and the read end to carry out empty judgment.
Specifically, in a practical application scenario provided by some embodiments of the present application, the structures of the write end and the read end of the asynchronous FIFO are omitted, which are shown in fig. 4a and 4b, respectively.
In fig. 4a, at least a partial structure of a write end is shown, which is in a write clock domain, wherein inputs of an and gate are respectively connected with a write enable signal and a non-full state signal, data can be written when the write enable signal and the non-full state signal are in the write enable signal and the non-full state signal, a write address is added with 1 when the data is written, a binary write pointer is added with 1, and the binary write pointer is converted into a gray code write pointer through logic processing of binary conversion gray code. The binary write pointer can be directly used at the local of the write end, and the Gray code write pointer can be synchronized across clock domains towards the read end so as to facilitate the read end to obtain the binary write pointer.
In fig. 4b, at least a partial structure of the read end is shown, which is in the read clock domain, wherein the input of the and gate receives the read enable signal and the non-empty state signal, respectively, when the read enable signal and the non-empty state are in the read state, the data can be read, when the data is read, the read address is increased by 1, and the binary read pointer is converted into the gray code read pointer through the logic processing of binary conversion gray code. The binary read pointer can be directly used at the local of the read end, and the Gray code read pointer can be synchronized to the write end across clock domains so as to facilitate the write end to obtain the binary read pointer.
Specifically, some embodiments of the present application provide a schematic diagram of a principle of performing asynchronous FIFO full determination and asynchronous FIFO empty determination in a practical application scenario, which is shown in fig. 5a and 5b, respectively.
In fig. 5a, the gray code read pointer is synchronized across clock domains from the read end, and the binary read pointer is obtained from the write end through logic processing of gray code conversion binary, and the binary write pointer can also be directly obtained locally at the write end, the binary write pointer and the binary read pointer are respectively input to the input ports x1 and x2 of the comparison logic, and through comparison, if (x1-x2) is determined to be N, a determination signal indicating a full state is output from the output port u1 of the comparison logic, otherwise, a determination signal indicating a non-full state can be output.
In fig. 5b, the gray code write pointer is synchronized across clock domains from the write port, and the read port obtains the binary write pointer through gray code conversion binary logic processing, and the binary read pointer can also be directly obtained locally at the read port, and the binary read pointer and the binary write pointer are respectively input to the input ports x1 and x2 of the comparison logic, and through comparison, if x1 is determined to be x2, a determination signal indicating an empty state is output from the output port u1 of the comparison logic, otherwise, a determination signal indicating a non-empty state may be output.
In addition, it should be noted that in fig. 3, 4a, 4b, 5a and 5b, a trigger is used, and the main purpose is to acquire signals more accurately. Especially in fig. 5a, 5b, at least two flip-flops in series may be used, respectively, which helps to synchronize the signals more accurately across the clock domains.
Based on the same idea, some embodiments of the present application further provide an apparatus, a device, and a non-volatile computer storage medium corresponding to the above method.
Fig. 6 is a schematic structural diagram of an apparatus for implementing an arbitrary depth asynchronous FIFO corresponding to fig. 1 according to some embodiments of the present application, where a dashed box represents an optional module, and the apparatus includes:
the write address operation module 601, when writing data by using a write address, adds 1 to the write address and its corresponding binary write pointer, respectively, where the write address wraps around according to the depth N of the asynchronous FIFO, and the binary write pointer wraps around according to 2nWound back, 2nMore than or equal to N, wherein N is a positive integer;
a read pointer conversion module 602, which receives a gray code read pointer synchronized across clock domains from a read end, and performs binary conversion to obtain a binary read pointer;
and the full judgment module 603 performs asynchronous FIFO full judgment according to the binary read pointer and the binary write pointer.
Optionally, the apparatus further comprises:
a write pointer synchronization module 604, configured to perform gray code conversion on the binary write pointer to obtain a gray code write pointer;
synchronizing the Gray code write pointer to a read end across clock domains to perform binary conversion to obtain a binary write pointer, and performing asynchronous FIFO empty judgment by the read end according to the binary write pointer and a local binary read pointer of the read end;
when a read end reads data by using a read address, the read address and the corresponding binary read pointer are respectively added with 1, the read address is wound back according to the depth N of the asynchronous FIFO, and the binary read pointer is wound according to 2nAnd the wrapped Gray code reading pointer is obtained by performing Gray code conversion on the binary system reading pointer.
Optionally, the full determination module 604 performs asynchronous FIFO full determination according to the binary read pointer and the binary write pointer, and specifically includes:
if the difference between the binary write pointer and the binary read pointer is equal to N, the full determination module 604 determines that the asynchronous FIFO is full.
Optionally, a time delay exists between the binary write pointer obtained by clock domain crossing synchronization and the local binary write pointer of the write end; and the number of the first and second groups,
compared with a local binary read pointer at a read end, the binary read pointer obtained by clock domain crossing synchronization has time delay.
Fig. 7 is a schematic diagram of an apparatus for implementing an arbitrary depth asynchronous FIFO according to some embodiments of the present application, where the dashed boxes represent optional modules, and the apparatus includes:
a read address operation module 701 for reading data using a read address whenever the data is readAdding 1 to an address and a binary read pointer corresponding to the address respectively, wherein the read address is wound back according to the depth N of the asynchronous FIFO, and the binary read pointer is wound according to 2nWound back, 2nMore than or equal to N, wherein N is a positive integer;
a write pointer conversion module 702, which receives a gray code write pointer synchronized across clock domains from a write end, and performs binary conversion to obtain a binary write pointer;
and the empty judgment module 703 is configured to perform an asynchronous FIFO empty judgment according to the binary read pointer and the binary write pointer.
Optionally, the apparatus further comprises:
a read pointer synchronization module 704, which performs gray code conversion on the binary read pointer to obtain a gray code read pointer;
synchronizing the Gray code reading pointer to a writing end across clock domains to perform binary conversion to obtain a binary reading pointer, wherein the binary reading pointer is used for the writing end to perform asynchronous FIFO fullness judgment according to the binary reading pointer and a local binary writing pointer of the writing end;
when a write end uses a write address to write data, the write address and the corresponding binary write pointer are respectively added with 1, the write address is wound back according to the depth N of the asynchronous FIFO, and the binary write pointer is wound according to 2nAnd the wrapped Gray code writing pointer is obtained by performing Gray code conversion on the binary writing pointer.
Optionally, the empty determination module performs an asynchronous FIFO empty determination according to the binary read pointer and the binary write pointer, and specifically includes:
and if the difference between the binary write pointer and the binary read pointer is equal to 0, the null determination module determines that the asynchronous FIFO is null.
Optionally, a time delay exists between the binary write pointer obtained by clock domain crossing synchronization and the local binary write pointer of the write end; and the number of the first and second groups,
compared with a local binary write pointer at a read end, the binary read pointer obtained by clock domain crossing synchronization has time delay.
Fig. 8 is a schematic structural diagram of an apparatus for implementing an arbitrary depth asynchronous FIFO, according to some embodiments of the present application, and the apparatus includes:
at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to enable the at least one processor to:
when writing data by using a write address, adding 1 to the write address and a binary write pointer corresponding to the write address respectively, wherein the write address is wound back according to the depth N of the asynchronous FIFO, and the binary write pointer is wound according to 2nWound back, 2nMore than or equal to N, wherein N is a positive integer;
receiving a Gray code reading pointer synchronized across clock domains from a reading end, and performing binary conversion to obtain a binary reading pointer;
and according to the binary read pointer and the binary write pointer, performing asynchronous FIFO fullness judgment.
Fig. 9 is a schematic structural diagram of an apparatus for implementing an arbitrary depth asynchronous FIFO, according to some embodiments of the present application, and the apparatus includes:
at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to enable the at least one processor to:
when reading data by using a read address, adding 1 to the read address and a binary read pointer corresponding to the read address respectively, wherein the read address is wound back according to the depth N of the asynchronous FIFO, and the binary read pointer is wound according to 2nWound back, 2nMore than or equal to N, wherein N is a positive integer;
receiving a Gray code write pointer synchronized across clock domains from a write end, and performing binary conversion to obtain a binary write pointer;
and performing asynchronous FIFO empty judgment according to the binary read pointer and the binary write pointer.
Some embodiments of the present application provide a non-volatile computer storage medium corresponding to fig. 1 implementing an arbitrary depth asynchronous FIFO, storing computer-executable instructions configured to:
when writing data by using a write address, adding 1 to the write address and a binary write pointer corresponding to the write address respectively, wherein the write address is wound back according to the depth N of the asynchronous FIFO, and the binary write pointer is wound according to 2nWound back, 2nMore than or equal to N, wherein N is a positive integer;
receiving a Gray code reading pointer synchronized across clock domains from a reading end, and performing binary conversion to obtain a binary reading pointer;
and according to the binary read pointer and the binary write pointer, performing asynchronous FIFO fullness judgment.
Some embodiments of the present application provide a non-volatile computer storage medium corresponding to fig. 2, storing computer-executable instructions configured to:
when reading data by using a read address, adding 1 to the read address and a binary read pointer corresponding to the read address respectively, wherein the read address is wound back according to the depth N of the asynchronous FIFO, and the binary read pointer is wound according to 2nWound back, 2nMore than or equal to N, wherein N is a positive integer;
receiving a Gray code write pointer synchronized across clock domains from a write end, and performing binary conversion to obtain a binary write pointer;
and performing asynchronous FIFO empty judgment according to the binary read pointer and the binary write pointer.
The embodiments in the present application are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus, device and media embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference may be made to some descriptions of the method embodiments for relevant points.
The apparatus, the device, the apparatus, and the medium provided in the embodiment of the present application correspond to the method one to one, and therefore, the apparatus, the device, and the medium also have beneficial technical effects similar to those of the corresponding method.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (20)
1. A method for realizing asynchronous first-in first-out FIFO with any depth is characterized by comprising the following steps:
when writing data by using a write address, adding 1 to the write address and a binary write pointer corresponding to the write address respectively, wherein the write address is wound back according to the depth N of the asynchronous FIFO, and the binary write pointer is wound according to 2nWound back, 2nMore than or equal to N, wherein N is a positive integer;
receiving a Gray code reading pointer synchronized across clock domains from a reading end, and performing binary conversion to obtain a binary reading pointer;
and according to the binary read pointer and the binary write pointer, performing asynchronous FIFO fullness judgment.
2. The method of claim 1, wherein the method further comprises:
performing Gray code conversion on the binary writing pointer to obtain a Gray code writing pointer;
synchronizing the Gray code write pointer to a read end across clock domains to perform binary conversion to obtain a binary write pointer, and performing asynchronous FIFO empty judgment by the read end according to the binary write pointer and a local binary read pointer of the read end;
when the read end reads data by using the read address, the read address and the corresponding read address are usedAdding 1 to the binary read pointer respectively, wrapping the read address according to the depth N of the asynchronous FIFO, and wrapping the binary read pointer according to 2nAnd the wrapped Gray code reading pointer is obtained by performing Gray code conversion on the binary system reading pointer.
3. The method of claim 2, wherein said performing an asynchronous FIFO full determination based on the binary read pointer and the binary write pointer comprises:
and if the difference between the binary write pointer and the binary read pointer is equal to N, judging that the asynchronous FIFO is full.
4. The method of claim 2, wherein the binary write pointer obtained by cross-clock domain synchronization has a time delay compared to the binary write pointer local to the write end; and the number of the first and second groups,
compared with a local binary read pointer at a read end, the binary read pointer obtained by clock domain crossing synchronization has time delay.
5. A method for realizing asynchronous first-in first-out FIFO with any depth is characterized by comprising the following steps:
when reading data by using a read address, adding 1 to the read address and a binary read pointer corresponding to the read address respectively, wherein the read address is wound back according to the depth N of the asynchronous FIFO, and the binary read pointer is wound according to 2nWound back, 2nMore than or equal to N, wherein N is a positive integer;
receiving a Gray code write pointer synchronized across clock domains from a write end, and performing binary conversion to obtain a binary write pointer;
and performing asynchronous FIFO empty judgment according to the binary read pointer and the binary write pointer.
6. The method of claim 5, wherein the method further comprises:
performing Gray code conversion on the binary system reading pointer to obtain a Gray code reading pointer;
synchronizing the Gray code reading pointer to a writing end across clock domains to perform binary conversion to obtain a binary reading pointer, wherein the binary reading pointer is used for the writing end to perform asynchronous FIFO fullness judgment according to the binary reading pointer and a local binary writing pointer of the writing end;
when a write end uses a write address to write data, the write address and the corresponding binary write pointer are respectively added with 1, the write address is wound back according to the depth N of the asynchronous FIFO, and the binary write pointer is wound according to 2nAnd the wrapped Gray code writing pointer is obtained by performing Gray code conversion on the binary writing pointer.
7. The method of claim 6, wherein said performing an asynchronous FIFO empty determination based on said binary read pointer and said binary write pointer comprises:
and if the difference between the binary write pointer and the binary read pointer is equal to 0, judging that the asynchronous FIFO is empty.
8. The method of claim 6, wherein the binary write pointer obtained by cross-clock domain synchronization has a time delay compared to the binary write pointer local to the write end; and the number of the first and second groups,
compared with a local binary read pointer at a read end, the binary read pointer obtained by clock domain crossing synchronization has time delay.
9. An apparatus for implementing an asynchronous first-in first-out FIFO of any depth, comprising:
a write address operation module, which adds 1 to the write address and the corresponding binary write pointer when writing data by using the write address, wherein the write address is wrapped according to the depth N of the asynchronous FIFO, and the binary write pointer is wrapped according to 2nWound back, 2nMore than or equal to N, wherein N is a positive integer;
the read pointer conversion module receives a Gray code read pointer synchronized across clock domains from a read end and performs binary conversion to obtain a binary read pointer;
and the full judgment module is used for carrying out asynchronous FIFO full judgment according to the binary read pointer and the binary write pointer.
10. The apparatus of claim 9, wherein the apparatus further comprises:
the writing pointer synchronization module is used for carrying out Gray code conversion on the binary writing pointer to obtain a Gray code writing pointer;
synchronizing the Gray code write pointer to a read end across clock domains to perform binary conversion to obtain a binary write pointer, and performing asynchronous FIFO empty judgment by the read end according to the binary write pointer and a local binary read pointer of the read end;
when a read end reads data by using a read address, the read address and the corresponding binary read pointer are respectively added with 1, the read address is wound back according to the depth N of the asynchronous FIFO, and the binary read pointer is wound according to 2nAnd the wrapped Gray code reading pointer is obtained by performing Gray code conversion on the binary system reading pointer.
11. The apparatus of claim 10, wherein the full determination module performs asynchronous FIFO full determination based on the binary read pointer and the binary write pointer, and specifically comprises:
and if the difference between the binary write pointer and the binary read pointer is equal to N, the full judgment module judges that the asynchronous FIFO is full.
12. The apparatus of claim 10, wherein the binary write pointer obtained by cross-clock domain synchronization has a delay compared to a binary write pointer local to the write end; and the number of the first and second groups,
compared with a local binary read pointer at a read end, the binary read pointer obtained by clock domain crossing synchronization has time delay.
13. An apparatus for implementing an asynchronous first-in first-out FIFO of any depth, comprising:
the read address operation module adds 1 to the read address and the corresponding binary read pointer when reading data by using the read address, the read address is wound back according to the depth N of the asynchronous FIFO, and the binary read pointer is wound according to 2nWound back, 2nMore than or equal to N, wherein N is a positive integer;
the write pointer conversion module receives a Gray code write pointer synchronized across clock domains from a write end and performs binary conversion to obtain a binary write pointer;
and the empty judgment module is used for carrying out asynchronous FIFO empty judgment according to the binary read pointer and the binary write pointer.
14. The apparatus of claim 13, wherein the apparatus further comprises:
the read pointer synchronization module is used for carrying out Gray code conversion on the binary read pointer to obtain a Gray code read pointer;
synchronizing the Gray code reading pointer to a writing end across clock domains to perform binary conversion to obtain a binary reading pointer, wherein the binary reading pointer is used for the writing end to perform asynchronous FIFO fullness judgment according to the binary reading pointer and a local binary writing pointer of the writing end;
when a write end uses a write address to write data, the write address and the corresponding binary write pointer are respectively added with 1, the write address is wound back according to the depth N of the asynchronous FIFO, and the binary write pointer is wound according to 2nAnd the wrapped Gray code writing pointer is obtained by performing Gray code conversion on the binary writing pointer.
15. The apparatus of claim 14, wherein the empty determination module performs an asynchronous FIFO empty determination based on the binary read pointer and the binary write pointer, specifically comprising:
and if the difference between the binary write pointer and the binary read pointer is equal to 0, the null determination module determines that the asynchronous FIFO is null.
16. The apparatus of claim 14, wherein the binary write pointer obtained by cross-clock domain synchronization has a latency compared to the binary write pointer local to the write end; and the number of the first and second groups,
compared with a local binary read pointer at a read end, the binary read pointer obtained by clock domain crossing synchronization has time delay.
17. An apparatus for implementing an asynchronous first-in first-out FIFO of any depth, comprising:
at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to enable the at least one processor to:
when writing data by using a write address, adding 1 to the write address and a binary write pointer corresponding to the write address respectively, wherein the write address is wound back according to the depth N of the asynchronous FIFO, and the binary write pointer is wound according to 2nWound back, 2nMore than or equal to N, wherein N is a positive integer;
receiving a Gray code reading pointer synchronized across clock domains from a reading end, and performing binary conversion to obtain a binary reading pointer;
and according to the binary read pointer and the binary write pointer, performing asynchronous FIFO fullness judgment.
18. An apparatus for implementing an asynchronous first-in first-out FIFO of any depth, comprising:
at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to enable the at least one processor to:
when reading data by using read address, the read address and its corresponding binary read pointer are respectivelyAdding 1, wrapping the read address according to the depth N of the asynchronous FIFO, and setting the binary read pointer according to 2nWound back, 2nMore than or equal to N, wherein N is a positive integer;
receiving a Gray code write pointer synchronized across clock domains from a write end, and performing binary conversion to obtain a binary write pointer;
and performing asynchronous FIFO empty judgment according to the binary read pointer and the binary write pointer.
19. A non-volatile computer storage medium implementing an arbitrary depth asynchronous first-in first-out FIFO, storing computer-executable instructions configured to:
when writing data by using a write address, adding 1 to the write address and a binary write pointer corresponding to the write address respectively, wherein the write address is wound back according to the depth N of the asynchronous FIFO, and the binary write pointer is wound according to 2nWound back, 2nMore than or equal to N, wherein N is a positive integer;
receiving a Gray code reading pointer synchronized across clock domains from a reading end, and performing binary conversion to obtain a binary reading pointer;
and according to the binary read pointer and the binary write pointer, performing asynchronous FIFO fullness judgment.
20. A non-volatile computer storage medium implementing an arbitrary depth asynchronous first-in first-out FIFO, storing computer-executable instructions configured to:
when reading data by using a read address, adding 1 to the read address and a binary read pointer corresponding to the read address respectively, wherein the read address is wound back according to the depth N of the asynchronous FIFO, and the binary read pointer is wound according to 2nWound back, 2nMore than or equal to N, wherein N is a positive integer;
receiving a Gray code write pointer synchronized across clock domains from a write end, and performing binary conversion to obtain a binary write pointer;
and performing asynchronous FIFO empty judgment according to the binary read pointer and the binary write pointer.
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