CN103377029A - Parametric universal FIFO control method - Google Patents

Abstract

The invention relates to a parametric universal FIFO control method. The method includes the steps; 1, static input parameters are input to a universal FIFO control circuit; 2, internal variables required to implement the FIFO control circuit are obtained according to the static input parameters; 3, the required universal FIFO control circuit is achieved according to the internal variables generated in the step 2 and required by the FIFO control circuit. The preset parameter precompiling means has the advantages that the means can be reused in all designs requiring FIFO, and multiple designing is avoided; 'section Gray encoding' is utilized, namely a fixed incremental value is centrally added to read and write addresses, and accordingly the maximum and minimum binary Gray code converted from the incremental value is provided with different numerical sections under only one bit; Gray code transform is applied to the code, so that the depth can be any even.

Description

Parameterized Universal FIFO control method

Technical field

The invention belongs to the computer hardware technology field, relate to a kind of circuit control method, relate in particular to a kind of parameterized Universal FIFO control method.

Background technology

FIFO (First-In, First-out), namely push-up storage is divided into synchronization fifo and asynchronous FIFO, a kind of circuit devcie that is usually used in data buffer storage, can be applicable to comprise high-speed data acquisition, multiprocessor interface and communicate by letter in the various fields such as speed buffering.Different with applied environment according to demand, FIFO may have the different degree of depth, different data bit widths, different read-write timing relationships, full indicating mode of different skies etc., usually need by repeatedly respectively design of demand, and asynchronous FIFO generally all uses Gray code to read, write address relatively, if this just causes the FIFO degree of depth is not 2 power, read, write address is by maximal value (degree of depth-1) when getting back to 0 value, because it is 1 that peaked scale-of-two Gray code has multidigit, multidigit can occur when becoming full 0 again by 1 to 0 saltus step, thereby lose the advantage that the adjacent code value of Gray code only has a saltus step, bring metastable state hidden danger, therefore the asynchronous FIFO degree of depth is confined to 2 power usually, cause the wasting of resources, use also very inconvenient.

Summary of the invention

In order to solve the above-mentioned technical matters that exists in the background technology, the invention provides a kind of precompile means by parameter preset, can need use in the design of FIFO multiplexing at all, avoid repeatedly designing, use simultaneously " section Gray code ", namely unification adds a fixed increment value to reading, writing address, make its scale-of-two Gray code that transforms to a maximal value and minimum value only have a different numerical value section, carry out again Gray code conversion and go to use, thereby make the degree of depth can be the parametrization Universal FIFO control method of any even number.

Technical solution of the present invention is: the invention provides a kind of parameterized Universal FIFO control method, its special character is: described parameterized Universal FIFO control method may further comprise the steps:

1) the Universal FIFO control circuit is inputted static input parameter;

2) shine upon the required built-in variable of accomplished fifo control circuit according to static input parameter;

3) according to step 2) FIFO that produces controls required inside circuit variable and realizes required Universal FIFO control circuit, and wherein address comparison circuit adopts " section Gray code " to realize.

Above-mentioned static input parameter comprises FIFO depth D EPTH, the full threshold value PROG_FULL_THRESH of programming and data pre-head model selection FIRST_WORD_FT;

Described FIFO depth D EPTH realizes that resource allows any even number in the limit;

The setting value of the full threshold value PROG_FULL_THRESH of described programming is the positive integer less than FIFO depth D EPTH;

The setting value of described data pre-head model selection FIRST_WORD_FT is 1 or 0; The setting value of described data pre-head model selection FIRST_WORD_FT is 1 o'clock, and pre-reading mode is selected in expression, always read in advance on the data fifo output bus DOUT FIFO go out in current first data; The setting value of described data pre-head model selection FIRST_WORD_FT is 0 o'clock, and non-pre-reading mode is selected in expression, only have when read enable signal RD_EN effective after, just export current first data on the data-out bus DOUT.

Above-mentioned fifo control circuit built-in variable comprises dual-port bank-address width ADDR_WIDTH, data writing counter bit wide WR_DATA_COUNT_WIDTH, readable data counter bit wide RD_DATA_COUNT_WIDTH, read/write address Gray code conversion section increment SECTION_INC and section Gray code data bit width GRAY_WIDTH;

Described dual-port bank-address width ADDR_WIDTH is round values, the bus bit wide of reading address read_addr, write address write_addr that about beam control circuit generates; Generate when realizing the complete necessary dual-port memory bank of fifo circuit, also be used for determining its size;

Said write data counter bit wide WR_DATA_COUNT_WIDTH is round values, the bit wide of the data writing number count value of about beam control circuit output;

Described readable data counter bit wide RD_DATA_COUNT_WIDTH is round values, the bit wide of the readable data number count value of about beam control circuit output;

Described read/write address Gray code conversion section increment SECTION_INC is round values, the starting point of selected numerical value section when carrying out Gray code conversion for the constraint read/write address;

Described section Gray code data bit width GRAY_WIDTH is round values, is used for the data bit width of constraint section Gray code.

Above-mentioned steps 2) mapping relations are:

The specific implementation of described dual-port bank-address width ADDR_WIDTH draws mode and is:

ADDR_WIDTH=clogb2 (DEPTH); Wherein: clogb2 is function name, and described clogb2 calculates and return function result of calculation according to the input value in the bracket; Described DEPTH is FIFO depth D EPTH;

Said write data counter bit wide WR_DATA_COUNT_WIDTH and readable data counter bit wide RD_DATA_COUNT_WIDTH satisfy following condition:

WR_DATA_COUNT_WIDTH＝RD_DATA_COUNT_WIDTH＝ADDR_WIDTH；

The mode that specifically draws of described reading, writing address Gray code conversion section increment SECTION_INC and section Gray code bit wide GRAY_WIDTH is:

A) SECTION_INC=0; Compose initial value to SECTION_INC, wait for later step calculating;

B) Temp_0=bin_to_gray (SECTION INC); Temp_1=bin_to_gray (SECTION_INC+DEPTH); Described Temp_0 and Temp_1 are the temporary variable of definition, and bin_to_gray is function name, and described bin_to_gray is according to the binary code of the input value in the bracket, are converted to Gray's agate and return;

C) GRAY_WIDTH=clogb2 (Temp_1); Compose initial value to GRAY_WIDTH, wait for later step calculating; Described clogb2 is function name, and described clogb2 calculates and return function result of calculation according to the input value in the bracket;

D) by turn relatively Temp_0 and Temp_1 and record its unequal figure place if unequal bits number is 1, then obtain SECTION_INC and GRAY_WIDTH value this moment, and end; Otherwise SECTION_INC=SECTION_INC+1 returns step b), and repeating step b) to steps d).

Above-mentioned function clogb2 (input) is the bit wide of calculating and export input value input, and its specific implementation is:

A) result=0; Tmp=input; Tmp is the inner temporary variable of function for this reason, and result is result of calculation;

b)tmp＝tmp＞＞1；

c)result＝result+1；

D) if tmp, returns step b greater than 0) and repeat b) to steps d); Otherwise the value of output result finishes;

Described function bin_to_gray (bin) is converted into Gray code and output with input value, and specific implementation is:

A) N=clogb2 (bin); N is the inner temporary variable of function for this reason;

B) gray[k]=bin[k] ^bin[k+1], k=0,1 ... N-2, described ^ are xor operation; Gray[N-1]=bin[N-1]

C) value of output gray.

Above-mentioned Universal FIFO control circuit comprise write make energy control module, write address generation module, write address section Gray code conversion module, full signal generates and the data writing counter module, read to make energy control module, read address generating module, read address section Gray code conversion module, spacing wave generates and the readable data counter module.

To writing the specific implementation that makes energy control module implement control be: writing the function that makes energy control module is that writing of output dual-port memory bank enables control signal write_en; This signal high level is effective, use Combinational logic output, to enable input signal wr_en be high level and come self-satisfied signal to generate and the full signal full of data writing counter module when writing of fifo control circuit, write_en output high level then, otherwise output low level;

The specific implementation of the write address generation module being implemented control is: the function of write address generation module is the address bus signal write_addr[ADDR_WIDTH-1:0 that generates and output to dual-port memory bank write port]; Described write address generation module is to work in the synchronizing circuit of writing under the clock wr_clk, and reset signal is wr_rst; Write_addr is register output, and reset values is 0; When the rising edge of wr_clk occur and reset signal invalid, at this moment:

If a) fifo control circuit input write that to enable wr_en be high level, come self-satisfied signal to generate and the full signal full of data writing counter module is low level, then go to step b), otherwise write_addr keeps initial value;

B) if write_addr equals DEPTH-1, write_addr output 0, otherwise write_addr is from increasing 1 output;

The specific implementation of write address section Gray code conversion module being implemented control is: the function of write address section Gray code conversion module is with write address write_addr[ADDR_WIDTH-1:0] be converted to Gray code wr_addr_gra[GRAY_WIDTH-1:0 after adding upper curtate increment size SECTION_INC] and output; Described SECTION_INC is the section incrementation parameter that calculates;

Write address section Gray code conversion module is to work in the synchronizing circuit of writing under the clock wr_clk, Gray code wr_addr_gra[GRAY_WIDTH-1:0] be register output, reset values is SECTION_INC; Be described below:

Wr_addr_gra[k]=(write_addr+SECTION_INC) [k] ^ (write_addr+SECTION_INC) [k+1], k=0,1 ... GRAY_WIDTH-2, described ^ is xor operation;

wr_addr_gra[GRAY_WIDTH-1]＝(write_addr+SECTION_INC)[GRAY_WIDTH-1]；

To the specific implementation that full signal generates and the data writing counter module is implemented to control be: the function of full signal generation and data writing counter module is the full indicator signal full of output FIFO, full signal prog_full and data writing count value wr_data_count[ADDR_WIDTH-1:0 programme]; This module is to work in the synchronizing circuit of writing under the clock wr_clk, and above-mentioned each signal is register output, and reset values is 0;

Described full signal generates and the vectorial cntw_size_var_int[ADDR_WIDTH:0 of the interior definition of data writing counter module], its value:

If a) (write_addr+SECTION_INC) greater than rd_addr_bin, cntw_size_var_int=(write_addr+SECTION_INC)-rd_addr_bin;

B) if otherwise (write_addr+SECTION_INC) equal rd_addr_bin, if full is low level, cntw_size_var_int=0; If full is high level, cntw_size_var_int=DEPTH;

C) otherwise, cntw_size_var_int=(DEPTH+ (write_addr+SECTION_INC))-rd_addr_bin;

Wherein, rd_addr_bin[GRAY WIDTH-1:0] for from after reading the reading address section gray code signal and be synchronized to the wr_clk clock zone through this module inter-sync circuit of address section Gray code conversion module, be converted into the vector signal of scale-of-two code value;

The condition of the full indicator signal full output of FIFO high level be among the current FIFO data with existing number cntw_size_var_int more than or equal to DEPTH or this time write operation will make among the FIFO data with existing number cntw_size_var_int more than or equal to DEPTH, otherwise be output low level;

The generation of the full signal prog_full of FIFO programming also is similar to the generation of full signal; The condition of the full signal prog_full output of programming high level be among the current FIFO data with existing number cntw_size_var_int more than or equal to the full threshold parameter PROG_FULL_THRESH of programming or this time write operation will make among the FIFO data with existing number cntw_size_var_int more than or equal to the full threshold parameter PROG_FULL_THRESH of programming, otherwise be output low level;

The value of output (write_addr+SECTION_INC)-rd_addr_bin when FIFO written data count value wr_data_count arrives more than or equal to rd_addr_bin at (write_addr+SECTION_INC); Otherwise, the value of output (DEPTH+ (write_addr+SECTION_INC))-rd_addr_bin;

To the specific implementation of reading energy control module is controlled be: the function of reading to make energy control module be output dual-port memory bank read to enable control signal read_en; This signal high level is effective, and selecting the FIRST_WORD_FT setting value when the pre-reading mode of static parameter data is 1, and then read_en exports fixedly high level, i.e. Chang Youxiao; Otherwise read_en reads to enable rd_en output with the FIFO input;

To reading the specific implementation that the address generation module controls be: the function of reading the address generation module is the address bus signal read_addr[ADDR_WIDTH-1:0 that generates and output to dual-port memory bank read port]; This module is to work in the synchronizing circuit of reading under the clock rd_clk, and reset signal is rd_rst; Read_addr is register output, and reset values is 0; When the rising edge of rd_clk occur and reset signal invalid, at this moment:

If a) FIFO input read enable rd_en and be high level, generate and the spacing wave empty of readable data counter module is low level from spacing wave, then go to step b), otherwise read_addr keeps initial value;

B) if read_addr equals DEPTH-1, read_addr output 0, otherwise read_addr is from increasing 1 output;

To reading the specific implementation that address section Gray code conversion module controls be: the function of reading address section Gray code conversion module is to read address read_addr[ADDR_WIDTH-1:0] be converted to Gray code rd_addr_gra[GRAY_WIDTH-1:0 after adding upper curtate increment size SECTION_INC] and output; Described SECTION_INC is the section incrementation parameter that calculates;

Reading address section Gray code conversion module is to work in the synchronizing circuit of writing under the clock rd_clk, and reset signal is rd_rst; Gray code rd_addr_gra[GRAY_WIDTH-1:0] be register output, reset values is SECTION_INC, is described below:

Rd_addr_gra[k]=(read_addr+SECTION_INC) [k] ^ (read_addr+SECTION_INC) [k+1], k=0,1 ... GRAY_WIDTH-2, described ^ is xor operation;

rd_addr_gra[GRAY_WIDTH-1]＝(read_addr+SECTION_INC)[GRAY_WIDTH-1]。

To the specific implementation that spacing wave generates and the readable data counter module is controlled be: spacing wave generates and the function of readable data counter module is the empty indicator signal empty of output FIFO and readable data count value rd_data_count[ADDR_WIDTH-1:0], this module is to work in the synchronizing circuit of writing under the clock rd_clk, and reset signal is rd_rst; Above-mentioned each signal is register output, and reset values is 0;

The vectorial cntr_size_var_int[ADDR_WIDTH:0 of definition in the module], its value:

If wr_addr_bin is greater than (read_addr+SECTION_INC), cntr_size_var_int=wr_addr_bin-(read_addr+SECTION_INC);

If otherwise wr_addr_bin equals (read_addr+SECTION_INC), if empty is high level, cntr_size_var_int=0; If empty is low level, cntr_size_var_int=DEPTH.

Otherwise, cntr_size_var_int=(DEPTH+wr_addr_bin)-(read_addr+SECTION_INC);

Wherein, wr_addr_bin[GRAY_WIDTH-1:0] for after the write address section gray code signal from write address section Gray code conversion module is synchronized to the rd_clk clock zone through this module inter-sync circuit, be converted into the vector signal of scale-of-two code value;

The condition of the empty indicator signal empty output of FIFO high level be among the current FIFO data with existing number cntr_size_var_int equal 0 or this time read operation will make that data with existing number cntr_size_var_int equals 0 among the FIFO, otherwise be output low level;

Readable data count value rd_data_count is in the value of wr_addr_bin time output wr_addr_bin-(read_addr+SECTION_INC) more than or equal to (read_addr+SECTION_INC) among the FIFO; Otherwise, the value of output (DEPTH+wr_addr_bin)-(read_addr+SECTION_INC).

Advantage of the present invention is:

Parameterized Universal FIFO control circuit disclosed by the invention and implementation method, only need to specify three static input parameters, just can generate required fifo control circuit, comprise write make energy control module, write address generation module, write address section Gray code conversion module, full signal generates and the data writing counter module, read to make energy control module, read address generating module, read address section Gray code conversion module, spacing wave generates and the readable data counter module.Static input parameter comprises FIFO depth D EPTH, the full threshold value PROG_FULL_THRESH of programming, and first data pre-head model selection FIRST_WORD_FT.The present invention is parametrization, General design, by the precompile means, can be applied to that any needs are used synchronously, in ASIC, SoC chip design, checking and the FPGA product of asynchronous FIFO memory design, extremely be conducive to use and promote as the soft nuclear of IP, break away from the dependence to external IP kernel, improve reliability and the controllability of design.

The present invention adopts precompilation techniques, only needs to specify three static parameters, just can automatically calculate the indoor design parameter according to the static parameter of input, avoids the duplication of labour, versatility, portable strong; The FIFO degree of depth is disposed by static parameter, is not limited to 2 power, can be any even number, greatly reduces circuit area and power consumption; The pre-reading mode of optional data is by static input parameter configuration; The reading and writing control circuit is independent clock territory, individual reset design, and synchronization fifo, asynchronous FIFO use identical isolated design, and reliability is high; Optional FIFO readable data counting and the output of written data counting are provided, satisfy multiple application demand; Control circuit does not comprise memory bank, is not subject to the difference of data bit width, and dirigibility is strong.

Description of drawings

Fig. 1 be the Universal FIFO control circuit and with the connection diagram of dual-port memory bank.

Embodiment

Parameterized Universal FIFO control circuit disclosed by the invention and implementation method, can be by the precompile means, realize the control circuits such as synchronization fifo or the necessary home address of asynchronous FIFO produce, the control of read-write pointer, empty full scale will according to the static input parameter that the degree of depth, the full threshold value of programming etc. is preset, the corresponding dual-ported memory of outside connection can consist of the FIFO that finishes function.

This circuit structure and implementation method can by the precompile means, realize all control circuits except memory bank such as synchronization fifo or the necessary home address of asynchronous FIFO produce, the control of read-write pointer, empty full scale will according to default static input parameters such as the degree of depth, the full threshold values of programming.

The static input parameter of parameterized Universal FIFO control circuit comprises the FIFO degree of depth, the full threshold value of programming and data pre-head model selection.Control circuit comprise write make energy control module, write address generation module, write address section Gray code conversion module, full signal generates and the data writing counter module, read to make energy control module, read address generating module, read address section Gray code conversion module, spacing wave generates and the readable data counter module, as shown in Figure 1.

Below the design of parametrization implementation method and each modular circuit is described in detail.

This parameterized Universal FIFO control circuit, its static input parameter comprises:

1) FIFO depth D EPTH: can be and realize that resource allows any even number in the limit;

2) the full threshold value PROG_FULL_THRESH of programming: its setting value is the positive integer less than DEPTH;

3) data pre-head model selection FIRST_WORD_FT, its setting value is required to be 1 or 0; Be preset as at 1 o'clock and namely select pre-reading mode, always read in advance on the data fifo output bus FIFO go out in current first data; Be preset as at 0 o'clock and select non-pre-reading mode, only have when read enable signal RD_EN effectively after, just export current first data on the data-out bus.

Realize each functional module of control circuit, relate to some built-in variables, comprising:

1) dual-port bank-address width ADDR_WIDTH: round values, the bus bit wide of reading address read_addr, write address write_addr that about beam control circuit generates; Generate when realizing the complete necessary dual-port memory bank of fifo circuit, also be used for determining its size;

2) data writing counter bit wide WR_DATA_COUNT_WIDTH and readable data counter bit wide RD_DATA_COUNT_WIDTH: round values, respectively the data writing number count value of about beam control circuit output and the bit wide of readable data number count value;

3) reading, writing address Gray code conversion section increment SECTION_INC: round values, the starting point of selected numerical value section when the constraint reading, writing address carries out Gray code conversion.

4) section Gray code data bit width GRAY_WIDTH: round values, for the data bit width of constraint section Gray code.

Built-in variable all can be calculated by writing setup code by static input parameter, and computing method are as follows in detail.

Dual-port bank-address width: ADDR_WIDTH, its value of ADDR_WIDTH is drawn by following methods:

ADDR_WIDTH=clogb2 (DEPTH); //clogb2 is function name, and it calculates and return function result of calculation according to the input value in the bracket.

Data writing counter bit wide WR_DATA_COUNT_WIDTH and readable data counter bit wide RD_DATA_COUNT_WIDTH, satisfy following condition:

WR_DATA_COUNT_WIDTH＝RD_DATA_COUNT_WIDTH＝ADDR_WIDTH。

Reading, writing address Gray code conversion section increment SECTION_INC and section Gray code bit wide GRAY_WIDTH, the iteration that SECTION_INC and GRAY_WIDTH must be worth by following steps draws:

A) SECTION_INC=0; // compose initial value to SECTION_INC, wait for later step calculating;

B) Temp_0=bin_to_gray (SECTION_INC); Temp_1=bin_to_gray (SECTION_INC+DEPTH); //Temp_0 and Temp_1 are the temporary variable of definition, and bin_to_gray is function name, and it is according to the binary code of the input value in the bracket, are converted to Gray code and return.

C) GRAY_WIDTH=clogb2 (Temp_1); // compose initial value to GRAY_WIDTH, wait for later step calculating; Clogb2 is function name, and it calculates and return function result of calculation according to the input value in the bracket.

D) by turn relatively Temp_0 and Temp_1 and record its unequal figure place if unequal bits number is 1, then obtain SECTION_INC and GRAY_WIDTH value this moment, end; Otherwise SECTION_INC=SECTION_INC+1 returns step b), and repeating step b) to steps d).

Wherein, function clogb2 (input), its function is achieved as follows for calculating and export the bit wide of input value input:

A) result=0; Tmp=input; //tmp is the inner temporary variable of function for this reason, and result is result of calculation;

B) tmp=tmp＞＞1; (moving to right one)

c)result＝result+1；

D) if tmp, returns step b greater than 0) and repeating step b) to steps d); Otherwise the value of output result finishes.

Function bin_to_gray (bin), this function performance is achieved as follows for input value being converted into Gray code and output:

A) N=clogb2 (bin); //N is the inner temporary variable of function for this reason, and clogb2 is function mentioned above;

B) gray[k]=bin[k] ^bin[k+1], k=0,1 ... N-2, " ^ " they are xor operation; Gray[N-1]=bin[N-1]

C) value of output gray.

Function and the implementation method of a following description control circuit functional module.

Write and make energy control module:

Writing the function that makes energy control module is that writing of output dual-port memory bank enables control signal write_en.This signal high level is effective, uses Combinational logic output, is high level and the full signal full that comes self-satisfied signal generation and data writing counter module when writing of FIFO enables input signal wr_en, and then write_en exports high level, otherwise output low level.

The write address generation module:

The function of write address generation module is the address bus signal write_addr[ADDR_WIDTH-1:0 that generates and output to dual-port memory bank write port].This module is to work in the synchronizing circuit of writing under the clock wr_clk, and reset signal is wr_rst.Write_addr is register output, and reset values is 0.When the rising edge of wr_clk occur and reset signal invalid, at this moment:

If a) FIFO input write that to enable wr_en be high level, come self-satisfied signal to generate and the full signal full of data writing counter module is low level, then go to b, otherwise write_addr keeps initial value;

B) if write_addr equals DEPTH-1, write_addr output 0, otherwise write_addr is from increasing 1 output.

Write address section Gray code conversion module:

The function of write address section Gray code conversion module is with write address write_addr[ADDR_WIDTH-1:0] be converted to Gray code wr_addr_gra[GRAY_WIDTH-1:0 after adding upper curtate increment size SECTION_INC] and output.

The realization of asynchronous FIFO such as is generally all directly carried out reading, writing address comparing after the conversion of Gray code at the computing, this has just limited the FIFO degree of depth and has been necessary for 2 power, otherwise at reading, writing address by maximal value (DEPTH-1) when getting back to 0 value, the multidigit saltus step can occur in its corresponding Gray code, thereby lose the advantage that the adjacent code value of Gray code only has a saltus step, bring metastable state hidden danger.Therefore remake conversion after write address being added upper curtate increment size SECTION_INC herein, the Gray code section of write address is become by SECTION_INC to (SECTION_INC+DEPTH-1) to (DEPTH-1) by 0.Wherein, SECTION_INC is the section incrementation parameter that calculates.Empirical tests, when DEPTH is even number, always can find the such numerical value of SECTION_INC, its characteristics be can so that the Gray code of the head and the tail numerical value of selected section (being SECTION_INC and SECTION_INC+DEPTH-1) only have 1 different, thereby the limited problem of the degree of depth when having avoided adopting the address directly to change is so that DEPTH can be any even number.Be 10 o'clock such as the degree of depth, SECTION_INC is 3,0 (Gray code is 0000) to the Gray code section of 9 (Gray code is 1101) can be adjusted to 3 (0010) to 12 (1010); In addition, when depth D EPTH was 2 power, SECTION_INC was 0.

Write address section Gray code conversion module is to work in the synchronizing circuit of writing under the clock wr_clk, Gray code wr_addr_gra[GRAY_WIDTH-1:0] be register output, reset values is SECTION_INC.Be described below:

Wr_addr_gra[k]=(write_addr+SECTION_INC) [k] ^ (write_addr+SECTION_INC) [k+1], k=0,1 ... GRAY_WIDTH-2, " ^ " they are xor operation;

wr_addr_gra[GRAY_WIDTH-1]＝(write_addr+SECTION_INC)[GRAY_WIDTH-1]。

Full signal generates and the data writing counter module:

Full signal generates and the function of data writing counter module is the full indicator signal full of output FIFO, the full signal prog_full of programming and data writing count value wr_data_count[ADDR_WIDTH-1:0].This module is to work in the synchronizing circuit of writing under the clock wr_clk, and above-mentioned each signal is register output, and reset values is 0.

The vectorial cntw_size_var_int[ADDR_WIDTH:0 of definition in the module], its value:

If a) (write_addr+SECTION_INC) greater than rd_addr_bin, cntw_size_var_int=(write_addr+SECTION_INC)-rd_addr_bin;

B) if otherwise (write_addr+SECTION_INC) equal rd_addr_bin, if full is low level, cntw_size_var_int=0; If full is high level, cntw_size_var_int=DEPTH.

C) otherwise, cntw_size_var_int=(DEPTH+ (write_addr+SECTION_INC))-rd_addr_bin;

Wherein, rd_addr_bin[GRAY_WIDTH-1:0] for from after reading the reading address section gray code signal and be synchronized to the wr_clk clock zone through this module inter-sync circuit of address section Gray code conversion module, be converted into the vector signal of scale-of-two code value.

The condition of the full indicator signal full output of FIFO high level be among the current FIFO data with existing number cntw_size_var_int more than or equal to DEPTH or this time write operation will make among the FIFO data with existing number cntw_size_var_int more than or equal to DEPTH, otherwise be output low level.

The generation of the full signal prog_full of FIFO programming also is similar to the generation of full signal.The condition of the full signal prog_full output of programming high level be among the current FIFO data with existing number cntw_size_var_int more than or equal to the full threshold parameter PROG_FULL_THRESH of programming or this time write operation will make among the FIFO data with existing number cntw_size_var_int more than or equal to the full threshold parameter PROG_FULL_THRESH of programming, otherwise be output low level.

The value of output (write_addr+SECTION_INC)-rd_addr_bin when FIFO written data count value wr_data_count arrives more than or equal to rd_addr_bin at (write_addr+SECTION_INC); Otherwise, the value of output (DEPTH+ (write_addr+SECTION_INC))-rd_addr_bin.

Read to make energy control module:

The function of reading to make energy control module be output dual-port memory bank read to enable control signal read_en.This signal high level is effective, and selecting the FIRST_WORD_FT setting value when the pre-reading mode of static parameter data is 1, and then read_en exports fixedly high level, i.e. Chang Youxiao; Otherwise read_en reads to enable rd_en output with the FIFO input.

Read the address generation module:

The function of reading the address generation module is the address bus signal read_addr[ADDR_WIDTH-1:0 that generates and output to dual-port memory bank read port].This module is to work in the synchronizing circuit of reading under the clock rd_clk, and reset signal is rd_rst.Read_addr is register output, and reset values is 0.When the rising edge of rd_clk occur and reset signal invalid, at this moment;

If a) FIFO input read enable rd_en and be high level, generate and the spacing wave empty of readable data counter module is low level from spacing wave, then go to b, otherwise read_addr keeps initial value;

B) if read_addr equals DEPTH-1, read_addr output 0, otherwise read_addr is from increasing 1 output.

Read address section Gray code conversion module:

The function of degree address section Gray code conversion module is to read address read_addr[ADDR_WIDTH-1:0] be converted to Gray code rd_addr_gra[GRAY_WIDTH-1:0 after adding upper curtate increment size SECTION_INC] and output.

The realization of asynchronous FIFO such as is generally all directly carried out reading, writing address comparing after the conversion of Gray code at the computing, this has just limited the FIFO degree of depth and has been necessary for 2 power, otherwise at reading, writing address by maximal value (DEPTH-1) when getting back to 0 value, the multidigit saltus step can occur in its corresponding Gray code, thereby lose the advantage that the adjacent code value of Gray code only has a saltus step, bring metastable state hidden danger.Therefore will read to remake conversion after the address adds upper curtate increment size SECTION_INC herein, the Gray code section of reading the address is become by SECTION_INC to (SECTION_INC+DEPTH-1) to (DEPTH-1) by 0.Wherein, SECTION_INC is the section incrementation parameter that calculates.Empirical tests, when DEPTH is even number, always can find the such numerical value of SECTION_INC, its characteristics be can so that the Gray code of the head and the tail numerical value of selected section (being SECTION_INC and SECTION_INC+DEPTH-1) only have 1 different, thereby the limited problem of the degree of depth when having avoided adopting the address directly to change is so that DEPTH can be any even number.Be 10 o'clock such as the degree of depth, SECTION_INC is 3,0 (Gray code is 0000) to the Gray code section of 9 (Gray code is 1101) can be adjusted to 3 (0010) to 12 (1010); In addition, when depth D EPTH was 2 power, SECTION_INC was 0.

Reading address section Gray code conversion module is to work in the synchronizing circuit of writing under the clock rd_clk, and reset signal is rd_rst.Gray code rd_addr_gra[GRAY_WIDTH-1:0] be register output, reset values is SECTION_INC.Be described below:

Rd_addr_gra[k]=(read_addr+SECTION_INC) [k] ^ (read_addr+SECTION_INC) [k+1], k=0,1 ... GRAY_WIDTH-2, " ^ " they are xor operation;

rd_addr_gra[GRAY_WIDTH-1]＝(read_addr+SECTION_INC)[GRAY_WIDTH-1]。

Spacing wave generates and the readable data counter module:

Spacing wave generates and the function of readable data counter module is the empty indicator signal empty of output FIFO and readable data count value rd_data_count[ADDR_WIDTH-1:0].This module is to work in the synchronizing circuit of writing under the clock rd_clk, and reset signal is rd_rst.Above-mentioned each signal is register output, and reset values is 0.

The vectorial cntr_size_var_int[ADDR_WIDTH:0 of definition in the module], its value:

If a) wr_addr_bin is greater than (read_addr+SECTION_INC), cntr_size_var_int=wr_addr_bin-(read_addr+SECTION_INC);

B) if otherwise wr_addr_bin equals (read_addr+SECTION_INC), if empty is high level, cntr_size_var_int=0; If empty is low level, cntr_size_var_int=DEPTH.

C) otherwise, cntr_size_var_int=(DEPTH+wr_addr_bin)-(read_addr+SECTION_INC);

Wherein, wr_addr_bin[GRAY_WIDTH-1:0] for after the write address section gray code signal from write address section Gray code conversion module is synchronized to the rd_clk clock zone through this module inter-sync circuit, be converted into the vector signal of scale-of-two code value.

The condition of the empty indicator signal empty output of FIFO high level be among the current FIFO data with existing number cntr_size_var_int equal 0 or this time read operation will make that data with existing number cntr_size_var_int equals 0 among the FIFO, otherwise be output low level.

Readable data count value rd_data_count is in the value of wr_addr_bin time output wr_addr_bin-(read_addr+SECTION_INC) more than or equal to (read_addr+SECTION_INC) among the FIFO; Otherwise, the value of output (DEPTH+wr_addr_bin)-(read_addr+SECTION_INC).

Claims (7)

1. parameterized Universal FIFO control method, it is characterized in that: described parameterized Universal FIFO control method may further comprise the steps:

1) the Universal FIFO control circuit is inputted static input parameter;

2) shine upon the required built-in variable of accomplished fifo control circuit according to static input parameter;

3) according to step 2) the required built-in variable of fifo control circuit that produces realizes required Universal FIFO control circuit.

2. parameterized Universal FIFO control method according to claim 1 is characterized in that: described static input parameter comprises FIFO depth D EPTH, the full threshold value PROG_FULL_THRESH of programming and data pre-head model selection FIRST_WORD_FT;

Described FIFO depth D EPTH realizes that resource allows any even number in the limit;

The setting value of the full threshold value PROG_FULL_THRESH of described programming is the positive integer less than FIFO depth D EPTH;

The setting value of described data pre-head model selection FIRST_WORD FT is 1 or 0; The setting value of described data pre-head model selection FIRST_WORD_FT is 1 o'clock, and pre-reading mode is selected in expression, always read in advance on the data fifo output bus DOUT FIFO go out in current first data; The setting value of described data pre-head model selection FIRST_WORD_FT is 0 o'clock, and non-pre-reading mode is selected in expression, only have when read enable signal RD_EN effective after, just export current first data on the data-out bus DOUT.

3. parameterized Universal FIFO control method according to claim 2, it is characterized in that: described fifo control circuit built-in variable comprises dual-port bank-address width ADDR_WIDTH, data writing counter bit wide WR_DATA_COUNT_WIDTH, readable data counter bit wide RD_DATA_COUNT_WIDTH, read/write address Gray code conversion section increment SECTION_INC and section Gray code data bit width GRAY_WIDTH;

Described dual-port bank-address width ADDR_WIDTH is round values, the bus bit wide of reading address read_addr, write address write_addr that about beam control circuit generates; Generate when realizing the complete necessary dual-port memory bank of fifo circuit, also be used for determining its size;

Said write data counter bit wide WR_DATA_COUNT_WIDTH is round values, the bit wide of the data writing number count value of about beam control circuit output;

Described readable data counter bit wide RD_DATA_COUNT_WIDTH is round values, the bit wide of the readable data number count value of about beam control circuit output;

Described read/write address Gray code conversion section increment SECTION_INC is round values, the starting point of selected numerical value section when carrying out Gray code conversion for the constraint read/write address;

Described section Gray code data bit width GRAY_WIDTH is round values, is used for the data bit width of constraint section Gray code.

4. parameterized Universal FIFO control method according to claim 3, it is characterized in that: mapping relations described step 2) are:

The specific implementation of described dual-port bank-address width ADDR_WIDTH draws mode and is:

ADDR_WIDTH=clogb2 (DEPTH); Wherein: clogb2 is function name, and described clogb2 calculates and return function result of calculation according to the input value in the bracket; Described DEPTH is FIFO depth D EPTH;

Said write data counter bit wide WR_DATA_COUNT_WIDTH and readable data counter bit wide RD_DATA_COUNT_WIDTH satisfy following condition:

WR_DATA_COUNT_WIDTH＝RD_DATA_COUNT_WIDTH＝ADDR_WIDTH；

The mode that specifically draws of described reading, writing address Gray code conversion section increment SECTION_INC and section Gray code bit wide GRAY_WIDTH is:

A) SECTION_INC=0; Compose initial value to SECTION_INC, wait for later step calculating;

B) Temp_0=bin_to_gray (SECTION_INC); Temp_1=bin_to_gray (SECTION_INC+DEPTH); Described Temp_0 and Temp_1 are the temporary variable of definition, and bin_to_gray is function name, and described bin_to_gray is according to the binary code of the input value in the bracket, are converted to Gray's agate and return;

C) GRAY_WIDTH=clogb2 (Temp_1); Compose initial value to GRAY_WIDTH, wait for later step calculating; Described clogb2 is function name, and described clogb2 calculates and return function result of calculation according to the input value in the bracket;

D) by turn relatively Temp_0 and Temp_1 and record its unequal figure place if unequal bits number is 1, then obtain SECTION_INC and GRAY_WIDTH value this moment, and end; Otherwise SECTION_INC=SECTION_INC+1 returns step b), and repeating step b) to steps d).

5. parameterized Universal FIFO control method according to claim 4 is characterized in that: described function clogb2 (input) calculates and the bit wide of output input value input, and its specific implementation is:

A) result=0; Tmp=input; Tmp is the inner temporary variable of function for this reason, and result is result of calculation;

b)tmp＝tmp＞＞1；

c)result＝result+1；

D) if tmp, returns step b greater than 0) and repeat b) to steps d); Otherwise the value of output result finishes;

Described function bin_to_gray (bin) is converted into Gray code and output with input value, and specific implementation is:

A) N=clogb2 (bin); N is the inner temporary variable of function for this reason;

B) gray[k]=bin[k] ^bin[k+1], k=0,1 ... N-2, described ^ are xor operation; Gray[N-1]=bin[N-1]

C) value of output gray.

6. the described parameterized Universal FIFO control method of arbitrary claim according to claim 1-5 is characterized in that: described Universal FIFO control circuit comprise write make energy control module, write address generation module, write address section Gray code conversion module, full signal generates and the data writing counter module, read to make energy control module, read address generating module, read address section Gray code conversion module, spacing wave generates and the readable data counter module.

7. parameterized Universal FIFO control method according to claim 6 is characterized in that:

Describedly to writing the specific implementation that makes energy control module implement control be: writing the function that makes energy control module is that writing of output dual-port memory bank enables control signal write_en; This signal high level is effective, use Combinational logic output, to enable input signal wr_en be high level and come self-satisfied signal to generate and the full signal full of data writing counter module when writing of fifo control circuit, write_en output high level then, otherwise output low level;

The specific implementation of the write address generation module being implemented control is: the function of write address generation module is the address bus signal write_addr[ADDR_WIDTH-1:0 that generates and output to dual-port memory bank write port]; Described write address generation module is to work in the synchronizing circuit of writing under the clock wr_clk, and reset signal is wr_rst; Write_addr is register output, and reset values is 0; When the rising edge of wr_clk occur and reset signal invalid, at this moment:

If a) fifo control circuit input write that to enable wr_en be high level, come self-satisfied signal to generate and the full signal full of data writing counter module is low level, then go to step b), otherwise write_addr keeps initial value;

B) if write_addr equals DEPTH-1, write_addr output 0, otherwise write_addr is from increasing 1 output;

The specific implementation of write address section Gray code conversion module being implemented control is: the function of write address section Gray code conversion module is with write address write_addr[ADDR_WIDTH-1:0] be converted to Gray code wr_addr_gra[GRAY_WIDTH-1:0 after adding upper curtate increment size SECTION_INC] and output; Described SECTION_INC is the section incrementation parameter that calculates;

Write address section Gray code conversion module is to work in the synchronizing circuit of writing under the clock wr_clk, Gray code wr_addr_gra[GRAY_WIDTH-1:0] be register output, reset values is SECTION_INC; Be described below:

Wr_addr_gra[k]=(write_addr+SECTION_INC) [k] ^ (write_addr+SECTION_INC) [k+1], k=0,1 ... GRAY_WIDTH-2, described ^ is xor operation;

wr_addr_gra[GRAY_WIDTH-1]＝(write_addr+SECTION_INC)[GRAY_WIDTH-1]；

To the specific implementation that full signal generates and the data writing counter module is implemented to control be: the function of full signal generation and data writing counter module is the full indicator signal full of output FIFO, full signal prog_full and data writing count value wr_data_count[ADDR_WIDTH-1:0 programme]; This module is to work in the synchronizing circuit of writing under the clock wr_clk, and above-mentioned each signal is register output, and reset values is 0;

Described full signal generates and the vectorial cntw_size_var_int[ADDR_WIDTH:0 of the interior definition of data writing counter module], its value:

If a) (write_addr+SECTION_INC) greater than rd_addr_bin, cntw_size_var_int=(write_addr+SECTION_INC)-rd_addr_bin;

B) if otherwise (write_addr+SECTION_INC) equal rd_addr_bin, if full is low level, cntw_size_var_int=0; If full is high level, cntw_size_var_int=DEPTH;

C) otherwise, cntw_size_var_int=(DEPTH+ (write_addr+SECTION_INC))-rd_addr_bin;

Wherein, rd_addr_bin[GRAY_WIDTH-1:0] for from after reading the reading address section gray code signal and be synchronized to the wr_clk clock zone through this module inter-sync circuit of address section Gray code conversion module, be converted into the vector signal of scale-of-two code value;

The condition of the full indicator signal full output of FIFO high level be among the current FIFO data with existing number cntw_size_var_int more than or equal to DEPTH or this time write operation will make among the FIFO data with existing number cntw_size_var_int more than or equal to DEPTH, otherwise be output low level;

The generation of the full signal prog_full of FIFO programming also is similar to the generation of full signal; The condition of the full signal prog_full output of programming high level be among the current FIFO data with existing number cntw_size_var_int more than or equal to the full threshold parameter PROG_FULL_THRESH of programming or this time write operation will make among the FIFO data with existing number cntw_size_var_int more than or equal to the full threshold parameter PROG_FULL_THRESH of programming, otherwise be output low level;

The value of output (write_addr+SECTION_INC)-rd_addr_bin when FIFO written data count value wr_data_count arrives more than or equal to rd_addr_bin at (write_addr+SECTION_INC); Otherwise, the value of output (DEPTH+ (write_addr+SECTION_INC))-rd_addr_bin;

To the specific implementation of reading energy control module is controlled be: the function of reading to make energy control module be output dual-port memory bank read to enable control signal read_en; This signal high level is effective, and selecting the FIRST_WORD_FT setting value when the pre-reading mode of static parameter data is 1, and then read_en exports fixedly high level, i.e. Chang Youxiao; Otherwise read_en reads to enable rd_en output with the FIFO input;

To reading the specific implementation that the address generation module controls be: the function of reading the address generation module is the address bus signal read_addr[ADDR_WIDTH-1:0 that generates and output to dual-port memory bank read port]; This module is to work in the synchronizing circuit of reading under the clock rd_clk, and reset signal is rd_rst; Read_addr is register output, and reset values is 0; When the rising edge of rd_clk occur and reset signal invalid, at this moment:

If a) FIFO input read enable rd_en and be high level, generate and the spacing wave empty of readable data counter module is low level from spacing wave, then go to step b), otherwise read_addr keeps initial value;

B) if read_addr equals DEPTH-1, read_addr output 0, otherwise read_addr is from increasing 1 output;

To reading the specific implementation that address section Gray code conversion module controls be: the function of reading address section Gray code conversion module is to read address read_addr[ADDR_WIDTH-1:0] be converted to Gray code rd_addr_gra[GRAY_WIDTH-1:0 after adding upper curtate increment size SECTION_INC] and output; Described SECTION_INC is the section incrementation parameter that calculates;

Reading address section Gray code conversion module is to work in the synchronizing circuit of writing under the clock rd_clk, and reset signal is rd_rst; Gray code rd_addr_gra[GRAY_WIDTH-1:0] be register output, reset values is SECTION_INC, is described below:

Rd_addr_gra[k]=(read_addr+SECTION_INC) [k] ^ (read_addr+SECTION_INC) [k+1], k=0,1 ... GRAY_WIDTH-2, described ^ is xor operation;

rd_addr_gra[GRAY_WIDTH-1]＝(read_addr+SECTION_INC)[GRAY_WIDTH-1]。

To the specific implementation that spacing wave generates and the readable data counter module is controlled be: spacing wave generates and the function of readable data counter module is the empty indicator signal empty of output FIFO and readable data count value rd_data_count[ADDR_WIDTH-1:0], this module is to work in the synchronizing circuit of writing under the clock rd_clk, and reset signal is rd_rst; Above-mentioned each signal is register output, and reset values is 0;

The vectorial cntr_size_var_int[ADDR_WIDTH:0 of definition in the module], its value:

If wr_addr_bin is greater than (read_addr+SECTION_INC), cntr_size_var_int=wr_addr_bin-(read_addr+SECTION_INC);

If otherwise wr_addr_bin equals (read_addr+SECTION_INC), if empty is high level, cntr_size_var_int=0; If empty is low level, cntr_size_var_int=DEPTH.

Otherwise, cntr_size_var_int=(DEPTH+wr_addr_bin)-(read_addr+SECTION_INC);

Wherein, wr_addr_bin[GRAY_WIDTH-1:0] for after the write address section gray code signal from write address section Gray code conversion module is synchronized to the rd_clk clock zone through this module inter-sync circuit, be converted into the vector signal of scale-of-two code value;

The condition of the empty indicator signal empty output of FIFO high level be among the current FIFO data with existing number cntr_size_var_int equal 0 or this time read operation will make that data with existing number cntr_size_var_int equals 0 among the FIFO, otherwise be output low level;

Readable data count value rd_data_count is in the value of wr_addr_bin time output wr_addr_bin-(read_addr+SECTION_INC) more than or equal to (read_addr+SECTION_INC) among the FIFO; Otherwise, the value of output (DEPTH+wr_addr_bin)-(read_addr+SECTION_INC).

Images