CN100483541C - Asynchronous data clock domain conversion - Google Patents
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- CN100483541C CN100483541C CNB2004100767310A CN200410076731A CN100483541C CN 100483541 C CN100483541 C CN 100483541C CN B2004100767310 A CNB2004100767310 A CN B2004100767310A CN 200410076731 A CN200410076731 A CN 200410076731A CN 100483541 C CN100483541 C CN 100483541C
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Abstract
A system for converting clock domain of asynchronous data is featured as providing a RAM active window for utilizing parameter to control read and write address collision scope and providing a delay protective mechanism for not outputting adjustment signal at certain period of time when read and write address collision is happened .
Description
Technical field
The present invention relates to the interfacing of chip, particularly the asynchronous clock domain switch technology.
Background technology
The interface module of chip can adopt fifo queue (First In First Out is called for short " FIFO ") to realize, if but input and output are in different clock zones, then may cause the reading and writing conflict.For example, when read clock in a period of time because frequency jitter has surpassed and has write clock frequency, just might cause that to read the address increase too fast, these data of reading the address do not write as yet, read the invalid or mistake of data of address, will cause read/write conflict in read operation.Therefore in the interface module design, need carry out the asynchronous clock domain conversion,, avoid causing Data Receiving mistake to occur because of the shake of asynchronous clock to realize the Flow Control of data.
Existing technical scheme adopts dual port random access storer (Random AccessMemory is called for short " RAM ") to constitute fifo queue usually and realizes the asynchronous clock domain conversion.The interface signal of the asynchronous clock domain converting system of prior art scheme comprises asynchronous writing clock (W_clk) and read clock (R_clk), with write writing of clock synchronization enable (W_en) and write data (W_data), with read clock synchronization read to enable (R_en) and read data (R_data).Simultaneously, in order to realize correct read-write and to avoid the overflow or the underflow of dual port RAM, also should provide and read clock and write the sky sign (empty) of clock synchronization and full scale will (full) to forbid read-write operation.
Because empty sign and full scale will have been controlled the reading and writing operation of RAM, so the wrong mistake that can cause operation of sign.Those of ordinary skill in the art are appreciated that the generation of sign is by to relatively the producing of read/write address, when the read-write clock complete when asynchronous, when binary read/write address is compared, the result that may make mistake.For example, in reading the address change process,, calculate the difference of read/write address, may produce the difference of mistake, cause producing wrong full scale will signal owing to everybody variation of reading the address is also asynchronous.If in the time of will being changed to full scale will less than sign, may reduce the performance of using, reduce write data speed; And will completely put the sign be changed to less than the time, carry out one time write operation, then may produce overflow error, this definitely should be avoided for practical application.Equally, the generation of empty marking signal also may produce similar mistake.Why can make a mistake is because when address change, because the every transformation period difference in multidigit address, numerical value may be for being different from other values of numerical value after the address change when asynchronous clock was sampled to it, asynchronously produce wrong sky sign and full scale will, so that produce the reading and writing operating mistake of RAM.
Based on above-mentioned consideration, in the existing technical scheme, reading, writing address adds one under the effect that reading and writing enable, and reading, writing address is carried out comparing after the Gray code conversion, and then produce empty, full scale will, again by process empty, full scale will control RAM reading and writing operation.Those of ordinary skill in the art understand, and Gray code is a kind of coded system that changes of having only between adjacent count value, if read/write address adopts the gray encoding mode, just can solve top problem.
In actual applications, there is following problem in such scheme: existing technical scheme is provided with dumb to the degrees of tolerance of clock jitter, and the conflict that may exist reading and writing clock to cause causes the repeatedly adjustment of reading and writing operation.
Cause the main cause of this situation to be, the condition that existing technical scheme hollow, full scale will produce can not be changed, and the conflict condition that promptly belongs to the reading and writing clock of different clock-domains can not be changed, and therefore the degrees of tolerance to clock jitter is provided with dumb; And the sky in the prior art scheme, full signal are to postpone certain umber of beats by the reading, writing address behind the commentaries on classics Gray code relatively to produce, when conflicting, reading, writing address may have the level shake, this may cause the repeatedly variation of sky, full signal with regard to a reading, writing address conflict, thereby causes repeatedly adjustment of reading and writing operation.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of system of asynchronous data clock zone conversion, making can be according to the actual conditions of hardware clock, the time-delay of satisfying input, output data to greatest extent under the situation of tolerance clock jitter is fixed, and avoiding simultaneously once conflicts causes repeatedly adjustment of reading and writing operation.
For achieving the above object, the invention provides a kind of system of asynchronous data clock zone conversion, comprise the dual port random access memory module, described dual port random access memory module is used for storing data and carries out corresponding accessing operation according to the address of read/write address module;
Also comprise: read/write address module, conflict judge module, holding circuit module and address set module;
Described read/write address module is used for storage and reading, writing address is provided;
Described conflict judge module is used for when the described reading, writing address of described read/write address module conflicts signal being adjusted in the address and is changed to effectively;
Described holding circuit module is used for receiving described address adjustment signal and to described address set module output, in a period of time after the effective described address adjustment signal of output is effective, shielding described address adjustment signal from described conflict judge module;
Described address set module is used for adjusting the reading, writing address in the described read/write address module receiving effective described address when adjusting signal.
Wherein, described conflict judge module also is used for whether dropping on according to reading the address whether decision is changed to described address adjustment signal effectively in the forbidden zone of described write address front and back.
In the described conflict judge module, the size of the forbidden zone before and after the described write address can be passed through parameter setting.
Described conflict judge module also comprises: delay register group and conflict logic are judged submodule;
Described delay register group is used for reading, writing address is converted to behind the Gray code reading clock zone and generates the reading, writing address that Gray code with different delayed time is represented through a plurality of delay registers respectively;
Described conflict logic judges that the reading, writing address that submodule is used for representing with the Gray code with different delayed time that described delay register group generates is input, produces described address and adjusts signal.
Described conflict logic judges that submodule also comprises: combined circuit module and MUX;
The reading, writing address that described combined circuit module is used for representing with the Gray code with different delayed time that described delay register group produces is as input, produces described address that institute might the parameter correspondence and adjusts signal and import as the multichannel of described MUX;
Described MUX as control signal, selects the described address of this parameter correspondence to adjust signal output with described parameter.
Described conflict logic judges in the submodule, and all the reading, writing address centerings after the difference of time-delay umber of beats is smaller or equal to the Gray code conversion of described parameter are if having any a pair of identical then signal is adjusted in described address be changed to effectively.
In the described read/write address module binary representation described to read the initial value most significant digit of address and described write address opposite, other is identical.
Counter of set and begin counting when described holding circuit module is adjusted signal in the effective described address of output when the count value of this counter during less than particular value, shields described address and adjusts signal.
Determine the corresponding different particular values of different parameters by described parameter with the count value described particular value relatively of described counter.
Described address set module is after receiving that signal is adjusted in effective described address, and with the most significant digit negate of the described write address of current binary representation, other invariant position is composed and given the described address of reading.
In the described address set module, after the described write address that the Gray code of storing in the delay register group is represented is converted to scale-of-two, add to obtain adjusting behind the time-delay beat number with current write address and read address signal, described adjustment is read to obtain the described numerical value that the address need be adjusted to of reading after the negate of address signal most significant digit.
By relatively finding; technical scheme difference with the prior art of the present invention is; the present invention can control the reading, writing address conflict range with parameter; a random access memory (Random Access Memory promptly can be provided; be called for short " RAM ") movable window; and the delay protection mechanism after a kind of reading, writing address conflict is provided simultaneously, after the reading, writing address conflict, does not export the Adjust signal in a period of time.
Difference on this technical scheme, brought comparatively significantly beneficial effect, that is, use the system of asynchronous clock domain conversion of the present invention, at first, can be by the movable window size of parameter change RAM, the conflict range of control reading, writing address makes when interface module is finished the asynchronous clock domain conversion flexibly, can control the scope of clock jitter flexibly, can farthest keep again importing, the fixing requirement of output timing time-delay, thereby the dirigibility that has improved interface module greatly; Secondly, because the present invention program's delay protection mechanism is not exported the Adjust signal in a period of time after the reading, writing address conflict, the reading, writing address that the level shake after therefore can avoiding once conflicting causes is repeatedly adjusted, and has improved the stability of system.
Description of drawings
Fig. 1 is the system's composition synoptic diagram according to the asynchronous data clock zone converting system of a preferred embodiment of the present invention;
Fig. 2 is the circuit diagram according to the delay register group 31 of the reading, writing address of a preferred embodiment of the present invention;
Fig. 3 is a circuit diagram of judging submodule 32 according to the conflict logic of a preferred embodiment of the present invention;
Fig. 4 is the circuit diagram according to the holding circuit module 40 of a preferred embodiment of the present invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
Ultimate principle of the present invention at first is described.The present invention program determines the movable window of RAM according to the parameter of setting, when reading that the address falls into the write address is to export effective address in the movable window of RAM at center the time to adjust signal (Adjust) and will read the address and adjust to 180 ° of phase places of write address, be about to the write address most significant digit negate of binary representation, other invariant position is composed to reading the address.Wherein, the size of the movable window of this RAM can be set according to hardware case by managerial personnel.In addition, the present invention program also is provided with holding circuit, behind the effective Adjust of output, falls the Adjust signal in a period of time inner screening and causes repeatedly address adjustment to avoid the primary address conflict.
System according to the asynchronous data clock zone converting system of a preferred embodiment of the present invention forms synoptic diagram as shown in Figure 1.
Asynchronous data clock zone converting system comprises: dual port RAM module 10, read/write address module 20, conflict judge module 30, holding circuit module 40 and address set module 50.
Dual port RAM module 10 is used to store data and carries out corresponding accessing operation according to reading, writing address.Dual port RAM module 10 is as well known to those skilled in the art, reads the data in the address when read operation, writes corresponding data to write address when write operation, does not describe in detail at this.
The address of needs when read/write address module 20 is used for storage read-write dual port RAM module 10.Wherein, read/write address module 10 is a notion in logic, and when specific implementation, read/write address is stored in respectively to be read clock zone and write in the clock zone.Need to prove that the reading, writing address initial value has 180 ° of phase differential when binary representation, promptly binary reading, writing address is opposite except most significant digit, and other position is all identical.In a preferred embodiment of the present invention, reading, writing address can be respectively the counter of two cycle counts, the degree of depth of its counting equals the storage depth of dual port RAM module 10, reads address counting when each read operation and adds 1, and write address counting when each write operation adds 1.For example, in a preferred embodiment of the present invention, the storage depth of dual port RAM module 10 is 2n, and then the count value of read/write address counter is 0～2n-1.
In a preferred embodiment of the present invention, conflict judge module 30 also comprises delay register group 31 and conflict logic is judged submodule 32.Wherein, delay register group 31 is converted to reading, writing address respectively behind the Gray code through the delay register buffer memory and generates the read/write address that Gray code with different delayed time is represented; Conflict logic judgement submodule 32 is obtained the reading, writing address with different delayed time that is converted to Gray code according to PARAMETER and is carried out logic determines from delay register group 31, when reading, writing address conflicts the Pre_Adjust signal is changed to effectively.
According to the physical circuit figure of the delay register group 31 of the reading, writing address of a preferred embodiment of the present invention as shown in Figure 2.Delay register group 31 comprises: the Gray code conversion module 311 and the d type flip flop 312 that is used for importing according to one bat of control clock delay that are used for the binary data of input is converted to Gray code.Clear in order to explain, the identical module of function that will handle read/write address among Fig. 2 is distinguished with R and W respectively, handles the identical module of function of reading the address or handling write address for being, and adds natural number (1,2......) and distinguished behind R or W.Wherein, W_add and R_add are respectively write address and read the address, and W_clk and R_clk are respectively and write clock and read clock, W_reg_n and be respectively Gray code conversion after read the address and write address time-delay n claps the data that are latched in the d type flip flop.Why need the Gray code time-delay is latched, be because Gray code is a non-weighted code, whether the comparison to Gray code can only get equal, can't directly calculate the difference of Gray code, so just can not subtract each other the difference that obtains read/write address, so the delay inequality value of the Gray code that the difference of read/write address just need be by read/write address obtains by direct Gray code.Those of ordinary skill in the art are appreciated that, the degree of depth of supposing dual port RAM is 2n, in order to produce the issuable difference of all read/write address, need latch W_reg_1～W_reg_n and R_reg_1～R_reg_ (2n-1) respectively, therefore d type flip flop 312 needs n in depositing reading the address time-delay, being respectively d type flip flop 312-R1～312Rn, needing 2n-1 in the write address time-delay is deposited, is respectively d type flip flop 312-W1～312-W (2n-1).In a preferred embodiment of the present invention, the read/write address after the Gray code conversion is transformed into reads clock zone, promptly the clock of all d type flip flops 312 all adopts R_clk, can avoid like this because the mistake of the difference of read-write clock zone when causing Gray code relatively.
Conflict logic judges that the read/write address that submodule 32 is represented the Gray code that latchs carries out the judgement of combinational logic; judge read/write address whether fallen into can conflict area by the PARAMETER setting range in, give holding circuit module 40 if then export effective Pre_Adjust signal.In a preferred embodiment of the present invention, reading, writing address conflict in the time of in reading the scope that the address falls into X the cycle before and after the write address, wherein, X=PARAMETER.In this preferred embodiment, dual port RAM module 10 storage depths are 2n, conflict logic is judged submodule input W_reg_1～W_reg_n and R_reg_1～R_reg_ (2n-1), generating P (i) by combinational circuit indicates as Adjust, wherein, i equals the value of PARAMETER, and those of ordinary skill in the art are appreciated that the read/write address of difference after smaller or equal to all Gray code conversion of i with the time-delay umber of beats compares and draw P (i).For example: during i=2, P (i)=((W_reg_3==R_reg_1) | (W_reg_3==R_reg_2) | (W_reg_3=R_reg_3) | (W_reg_3==R_reg_4) | (W_reg_3==R_reg_5)); During i=1, P (i)=((W_reg_2==R_reg_1) | (W_reg_2==R_reg_2) | (W_reg_2==R_reg_3)).Wherein ,==the equal computing of presentation logic, if two variablees are identical, value is 1, otherwise is 0; | the presentation logic exclusive disjunction.Those of ordinary skill in the art as can be seen, in this preferred embodiment, Pre_Adjust be changed to 1 o'clock effective.
Judge that according to the conflict logic of a preferred embodiment of the present invention the concrete circuit of submodule 32 realizes as shown in Figure 3, conflict logic is judged that submodule 32 comprises and is used to produce P (i) (combined circuit module 321 and a MUX 322 of selecting specific P (i) output with PARAMETER as control signal of i=0～n-1).Wherein, the storage depth of the dual port RAM module 10 of this preferred embodiment is 2n, combined circuit module 321 input W_reg_1～W_reg_n and R_reg_1～R_reg_ (2n-1), output P (i) (i=0～n-1); (i=0～n-1) the input control end is that PARAMETER MUX 322 is selected output P (i) (i=PARAMETER) with P (i).About the realization logic of P (i), can be with reference to following table.
Wherein, the time-delay umber of beats of the write address after the first behavior Gray code conversion, first classifies the time-delay umber of beats of reading the address after the Gray code conversion as, (i=0～n-1) is 1 in the reading, writing address phase isochronia of correspondence only to Pi, in the table all Pi values mutually or the result be the address of PARAMETER when being i and adjust signal, Dui Ying P (i) (i=0～n-1) just.Those of ordinary skill in the art can be easy to realize conflict logic judgement submodule 32 in view of the above.
According to the circuit diagram of the holding circuit module 40 of a preferred embodiment of the present invention as shown in Figure 4.Holding circuit module 40 comprises: three d type flip flops (using 401,402 and 403 expressions respectively), gather 410 (representing with 410-1 and 410-2 respectively) of rising edge module for two; counter 420; comparer 430, MUX 470, phase inverter 450 and logical and module 460.Wherein, all control clocks of this circuit adopt reads clock R_clk, d type flip flop 401 will output to d type flip flop 402 after the Pre_Adjust signal buffer memory one that conflict judge module 30 receives is clapped, the clear terminal signal of d type flip flop 402 is obtained through gathering rising edge module 410-1 by the output of comparer 430, the output of d type flip flop 402 is through gathering the input end that rising edge module 410-2 outputs to logical and module 460, the output signal of another input end input comparator 430 of logical and module 460, the output signal of logical and module 460 is exported to described address set module 50 as the Adjust signal after d type flip flop 403 buffer memorys one are clapped, simultaneously, the output signal of logical and module 460 is also as the reset signal of counter 420; The input end of counter 420 inserts R_clk, and Enable Pin inserts the negate of the output signal of comparer 430, and the output signal of counter 420 is an input signal of device 430 as a comparison; MUX 470 is selected the input end of input as Sign signal input comparator 430 according to PARAMETER; Comparer 430 is at the output of counter 420 output high level during more than or equal to the Sign signal.Need to prove, the Adjust signal of the data based last generation of input end of MUX 470 is the time-delay decision of real real-time collision signal relatively, for example, in a preferred embodiment of the present invention, produce the Adjust Signal off-set and take place to have delayed time 6 to read the clock period from conflict, then the input of MUX 470 is followed successively by 6,7,9,11......7+2* (n-1), promptly when PARAMETER=0, Sign=6; When PARAMETER=(1～(n-1)), Sign=7+2* (PARAMETER-1).Need to prove that counter 420 is a cycle count, when the storage depth of dual port RAM module 10 was 2n, count value was 0～8n-1.
Described address set module 50 is used for after receiving effective Adjust signal, sends address adjustment signal to read/write address module 20 and adjusts described reading, writing address.In the preferred embodiment of the present invention, when adopting the reading, writing address conflict, write address is constant, and adjust the mode of reading the address and make and read the position that 180 ° of write addresses are adjusted in the address, i.e. reading, writing address most significant digit difference, other are identical.Because reading, writing address is at different clock-domains, the asynchronous domain sampling exists uncertain, therefore in the preferred embodiment of the present invention, obtain reading the value that the address need be adjusted by a M signal R_adjust, R_adjust is equivalent to current write address and is reading the embodiment of clock zone, when Adjust was effective, to the negate of R_adjust signal most significant digit, other invariant positions got mode and obtain reading the address.Wherein, R_adjust=W_binary+5, W_binary is the data after W_reg_3 changes scale-of-two, be that write address is being read the embodiment of clock zone, 3 modes of clapping of delaying time are finished the clock zone conversion after why adopting the write address Gray code conversion, mainly are the metastable states that may occur in the sampling in order to eliminate.
Though by reference some preferred embodiment of the present invention, the present invention is illustrated and describes, but those of ordinary skill in the art should be understood that, can do various changes to it in the form and details, and the spirit and scope of the present invention that do not depart from appended claims and limited.
Claims (11)
1. the system of an asynchronous data clock zone conversion comprises the dual port random access memory module, and described dual port random access memory module is used for storing data and carries out corresponding accessing operation according to the address of read/write address module; It is characterized in that, also comprise: read/write address module, conflict judge module, holding circuit module and address set module;
Described read/write address module is used for storage and reading, writing address is provided;
Described conflict judge module is used for when the described reading, writing address of described read/write address module conflicts signal being adjusted in the address and is changed to effectively;
Described holding circuit module is used for receiving described address adjustment signal and to described address set module output, in a period of time after the effective described address adjustment signal of output is effective, shielding described address adjustment signal from described conflict judge module;
Described address set module is used for adjusting the reading, writing address in the described read/write address module receiving effective described address when adjusting signal.
2. the system of asynchronous data clock zone conversion according to claim 1 is characterized in that, described conflict judge module also is used for whether dropping on according to reading the address whether decision is changed to described address adjustment signal effectively in the forbidden zone of described write address front and back.
3. the system of asynchronous data clock zone conversion according to claim 2 is characterized in that, in the described conflict judge module, the size of the forbidden zone before and after the described write address can be passed through parameter setting.
4. the system of asynchronous data clock zone conversion according to claim 3 is characterized in that described conflict judge module also comprises: delay register group and conflict logic are judged submodule;
Described delay register group is used for reading, writing address is converted to behind the Gray code reading clock zone and generates the reading, writing address that Gray code with different delayed time is represented through a plurality of delay registers respectively;
Described conflict logic judges that the reading, writing address that submodule is used for representing with the Gray code with different delayed time that described delay register group generates is input, produces described address and adjusts signal.
5. the system of asynchronous data clock zone conversion according to claim 4 is characterized in that, described conflict logic judges that submodule also comprises: combined circuit module and MUX;
The reading, writing address that described combined circuit module is used for representing with the Gray code with different delayed time that described delay register group produces is as input, produces described address that institute might the parameter correspondence and adjusts signal and import as the multichannel of described MUX;
Described MUX as control signal, selects the described address of this parameter correspondence to adjust signal output with described parameter.
6. the system of asynchronous data clock zone conversion according to claim 4, it is characterized in that, described conflict logic is judged in the submodule, difference all reading, writing address centerings after smaller or equal to the Gray code conversion of described parameter of time-delay umber of beats, if having any a pair of identical then signal is adjusted in described address be changed to effectively.
7. the system of asynchronous data clock zone according to claim 1 conversion is characterized in that, in the described read/write address module binary representation described to read the initial value most significant digit of address and described write address opposite, other is identical.
8. the system of asynchronous data clock zone conversion according to claim 1; it is characterized in that; counter of set and begin counting when described holding circuit module is adjusted signal in the effective described address of output; when the count value of this counter during, shield described address and adjust signal less than particular value.
9. the system of asynchronous data clock zone conversion according to claim 8 is characterized in that and the count value described particular value relatively of described counter is determined by described parameter, the corresponding different particular values of different parameters.
10. the system of asynchronous data clock zone conversion according to claim 1, it is characterized in that described address set module is after receiving that signal is adjusted in effective described address, with the most significant digit negate of the described write address of current binary representation, other invariant position is composed and is given the described address of reading.
11. the system of asynchronous data clock zone conversion according to claim 10, it is characterized in that, in the described address set module, after the described write address that the Gray code of storing in the delay register group is represented is converted to scale-of-two, add to obtain adjusting behind the time-delay beat number with current write address and read address signal, described adjustment is read to obtain the described numerical value that the address need be adjusted to of reading after the negate of address signal most significant digit.
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| EP4075668A4 (en) * | 2019-12-09 | 2024-01-03 | Sanechips Technology Co., Ltd. | Data acquisition method, apparatus and device, and storage medium |
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| CN100465934C (en) * | 2006-05-09 | 2009-03-04 | 华为技术有限公司 | Device and method for transmitting data in asynchronous clock domain |
| CN102054536B (en) * | 2009-11-09 | 2012-10-03 | 上海华虹Nec电子有限公司 | Device for testing DP (Dual Port) SRAM (Static Random Access Memory) by utilizing ALPG tester |
| CN102708086B (en) * | 2012-05-10 | 2015-05-20 | 无锡华大国奇科技有限公司 | Elastic buffer structure and method applied to universal serial bus 3.0 (USB 3.0) |
| CN109062538B (en) * | 2018-07-10 | 2020-11-20 | 豪威科技(上海)有限公司 | Circular first-in first-out buffer and data transmission interface, system and method |
| CN110008157A (en) * | 2019-04-02 | 2019-07-12 | 北京工业大学 | A kind of hardware structure of deserializer |
| CN110059036B (en) * | 2019-04-15 | 2022-04-26 | 西安微电子技术研究所 | Access control device and method for multiple asynchronous interfaces in memory bank |
| CN111708483B (en) * | 2020-05-13 | 2023-07-25 | 北京无线电计量测试研究所 | Signal delay method and device |
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| EP4075668A4 (en) * | 2019-12-09 | 2024-01-03 | Sanechips Technology Co., Ltd. | Data acquisition method, apparatus and device, and storage medium |
| JP7442642B2 (en) | 2019-12-09 | 2024-03-04 | セインチップス テクノロジー カンパニーリミテッド | Data collection methods, equipment, devices and recording media |
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