CN102520761A - Arbitrary waveform generating system based on user-defined processor - Google Patents
Arbitrary waveform generating system based on user-defined processor Download PDFInfo
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Abstract
The invention discloses an arbitrary waveform generating system based on a user-defined processor. In a control portion, a waveform generating module generates various waveform segment data downloaded to a hardware portion through a waveform downloading module, a control program generating module receives an externally inputted instruction set, and the instruction set is downloaded to the hardware portion after compiling of a compiling module. In the hardware portion, a storage control logic module controls reading and writing of a waveform memory, the user-defined waveform processor receives and analyzes the instruction set, generates call instructions for corresponding waveform segments according to names of the waveform segments indicated by the instruction set, transmits the call instructions to the storage control logic module and receives the waveform segment data read by the storage control logic module, and analog signals are outputted after combined waveform segment data are conditioned according to the call sequence and the call frequency of the waveform segment indicated by the instruction set. By the aid of the arbitrary waveform generating system, data transmission time of the control portion and the hardware portion during waveform generation can be shortened.
Description
Technical field
The present invention relates to the AWG technical field, particularly relate to a kind of random waveform and produce system based on self-defined processor.
Background technology
AWG has experienced technical development for many years as one of common surveying instrument.The like product of promoting that is widely used on the market mainly is divided into desk-top instrument and bus type virtual instrument.Desk-top instrument independence is stronger, but its volume is bigger, and the environment for use scope is less, is realizing aspect the operated from a distance and the system integration certain limitation being arranged.And the bus type virtual instrument has original superiority aspect the system integration and the operated from a distance.
At present, the AWG based on bus has functions such as the reference waveform of generation, random waveform, arbitrary sequence.Yet present AWG is by computing machine all data according to demand generation random waveform, downloads in the waveform generation module through bus then, and waveform generation module is according to Wave data pointwise output analog waveform.But the mode speed of all Wave datas of the unified generation of this computing machine is slow, needs the transmission lot of data in the bus, can not realize the Real-Time Scheduling of random waveform.
In addition; The random waveform of AWG in the market and arbitrary sequence function are fairly simple; Simply be formed by connecting a plurality of random waveforms like arbitrary sequence, in some test, comparatively complicated random waveform or arbitrary sequence function can not be provided like this.
Summary of the invention
In view of this, the invention provides a kind of random waveform based on self-defined processor and produce system, can reduce the data transmission period of control section and hardware components in the waveform generation process, improve the real-time of generation random waveform;
Further, the present invention can provide comparatively complicated random waveform and arbitrary sequence function, to promote the function and the performance of AWG series products.
This scheme is achieved in that
A kind of random waveform based on self-defined processor produces system, comprising: the control section of AWG and hardware components; Wherein, said control section comprises waveform generation module, waveform download module, control program generation module, collector and first interface unit; Said hardware components comprises second interface unit, self-defined waveform processor, store control logic module, wave memorizer and signal condition module; The waveform download module all is connected first interface unit with collector, and self-defined waveform processor all is connected second interface unit with the store control logic module, and said control section and said hardware components carry out data interaction through interface unit separately;
Said waveform generation module is used to produce the waveform segment data in all kinds, length and cycle, and name respectively, sends to said waveform download module then;
Said waveform download module is used for the waveform segment data that received are downloaded to said hardware components through said first interface unit;
Said store control logic module, realize read-write control to wave memorizer: will from second interface unit receive from the waveform segment data storage of control section to wave memorizer; According to from the specified waveform segment of the call instruction of self-defined waveform processor, from wave memorizer, read and specify the waveform segment data to send to self-defined waveform processor;
Said control program generation module is used to receive the instruction set of outside input, and this instruction set has indicated the waveform segment title that forms required random waveform and need call, called order, call number, and this instruction set is sent to collector;
Said collector is used for said instruction set is compiled as the order code that AWG can be discerned, and downloads to said hardware components through said first interface unit;
Said self-defined waveform processor; Receive and resolve instruction set from control section; Produce the call instruction of respective waveforms section according to the waveform segment title of instruction set indication, send to the store control logic module, and receive the waveform segment data that the store control logic module reads; Call order and call number, said waveform segment data that combination obtains, and export to the signal condition module according to the waveform segment of instruction set indication;
Said signal condition module, the waveform that self-defined waveform processor is exported carries out digital-to-analog conversion and the output of conditioning back.
Wherein, said self-defined waveform processor comprises instruction cache module, instruction translation module;
Instruction cache module is used for the instruction set of buffer memory from second interface unit;
The instruction translation module is used for reading and carry out each bar instruction one by one from said instruction set, and said instruction comprises waveform generation instruction, loop control instruction, conditional branch instructions, wait instruction;
When instruction was instructed for waveform generation, the instruction translation module was extracted the waveform segment title from the waveform generation instruction, produce the call instruction of respective waveforms section, and send to the store control logic module; The waveform segment data that the store control logic module is read send to the signal condition module;
When instruction was loop control instruction, the instruction translation module was carried out the instruction of appointment according to loop control instruction named order and number of cycles;
When instruction was conditional branch instructions, the instruction translation module judged at first whether branch condition is set up, and under the situation that condition is set up, carried out the instruction of appointment;
When instruction was instructed for waiting for, the instruction translation module judged that constantly whether the wait termination condition of waiting for the instruction appointment satisfies, and under situation about satisfying, carries out next bar and instructs.
Wherein, said signal condition module comprises FIFO, waveshape monitor, D/A converter and conditioner;
FIFO is used for the waveform segment data that the self-defined waveform processor of buffer memory is sent;
Waveshape monitor when being used to detect said FIFO and being non-NULL, sends to D/A converter with the waveform segment data;
D/A converter is used for the waveform segment data are carried out digital-to-analog conversion, and the output analog waveform is given conditioner;
Conditioner is used for that waveform to D/A converter output amplifies, exports after decay and the bias operation.
Beneficial effect:
The waveform segment that the present invention will design in advance downloads in the wave memorizer of hardware components of AWG; When needs produce waveform; Control program is downloaded in the self-defined waveform processor through interface unit by computing machine; Call the waveform segment data that prestore by self-defined waveform processor according to the order of sequence according to control program, and layout becomes required random waveform to send, and layout is accomplished one section and is promptly sent one section.Because Wave data all is to be stored in the AWG hardware components in advance; Therefore in the waveform generation process, need not carry out the mass data transmission, only need transmitting very, the control program of smallest number gets final product; Reduce data transmission period greatly, improved the real-time that produces random waveform.
The invention provides several instructions, can realize complicated comparatively complicated random waveform and arbitrary sequence function, and programming is simple.
Description of drawings
Fig. 1 is the composition structural representation that produces system based on the random waveform of self-defined processor.
Embodiment
Below in conjunction with the accompanying drawing embodiment that develops simultaneously, describe the present invention.
The invention provides a kind of random waveform based on self-defined processor and produce system, as shown in Figure 1, this system comprises the control section and the hardware components of AWG.Wherein, control section comprises waveform generation module, waveform download module, control program generation module, collector and first interface unit.Hardware components comprises second interface unit, self-defined waveform processor, store control logic module, wave memorizer and signal condition module.The waveform download module all is connected first interface unit with collector, and self-defined waveform processor all is connected second interface unit with the store control logic module.First interface unit and second interface unit adopt the interface of same type; For example can adopt in USB, PCI (peripheral element extension interface), PXI (towards the PCI expansion of instrument system), PCIe (PCI-Express) and PXIe (PXI-Express) interface any one, control section and said hardware components carry out data interaction through interface unit separately.Wave memorizer can adopt any one in RAM (RAS), SDRAM (synchronous DRAM) and DDR2 (double data rate 2, the Double Data Rate 2) storer.
The waveform generation module is used for importing the waveform segment data that produce all kinds, length and cycle according to the user, and name respectively, sends to said waveform download module then.
The waveform download module is used for the waveform segment data that received are downloaded to said hardware components through first interface unit.
The control program generation module is used to receive the instruction set of outside input, and this instruction set has indicated the waveform segment title that forms required random waveform and need call, called order, call number, and this instruction set is sent to collector.
Collector is used for the instruction set of character string forms is compiled as the binary command sign indicating number that AWG can be discerned, and the binary command sign indicating number downloads to hardware components through first interface unit.
The store control logic module, realize read-write control to wave memorizer: will from second interface unit receive from the waveform segment data storage of control section to wave memorizer; According to from the specified waveform segment of the call instruction of self-defined waveform processor, from wave memorizer, read and specify the waveform segment data to send to self-defined waveform processor.
Self-defined waveform processor; Receive and resolve instruction set from control section; Produce the call instruction of respective waveforms section according to the waveform segment title of instruction set indication, send to the store control logic module, and receive the waveform segment data that the store control logic module reads; Call order and call number, said waveform segment data that combination obtains, and export to the signal condition module according to the waveform segment of instruction set indication.
This self-defined waveform processor comprises instruction cache module and instruction translation module:
Instruction cache module is used for the instruction set of buffer memory from second interface unit.
The instruction translation module is used for reading and carry out each bar instruction one by one from said instruction set.For realizing complicated random waveform control, instruction comprises waveform generation instruction, loop control instruction, conditional branch instructions, wait instruction.Specifically, when being resolved to different instructions, the instruction translation module is carried out following operation:
● when Generate wavename is instructed in instruction for waveform generation, from the waveform generation instruction, extract waveform segment title wavename, produce the call instruction of respective waveforms section, and send to the store control logic module; The waveform segment data load that the store control logic module is read is in the signal condition module.
● when instruction is loop control instruction Repeat Condition A, carry out the instruction of appointment according to loop control instruction named order and number of cycles; The Condition A here can be a digital N; Then circulation is carried out N time, and Condition A can also be a trigger condition Trigger, if trigger condition is effective; Then continue circulation or stop circulation, this trigger condition can be given to self-defined waveform processor by computing machine.
In the present embodiment, the form of loop control instruction can for:
The Repeat cycling condition
Instruction 1
...
Command M
end?Repeat
Wherein, instruction 1～command M is all chosen from instruction set.
● when instruction during for conditional branch instructions IF Condition A then X1～Xm else Y1～Yn, at first whether Rule of judgment Condition A sets up, and under the situation that condition is set up, carries out the instruction X1～Xm of appointment; Otherwise, execution command Y1～Yn.In order to reduce instruction type, Condition A also can adopt above-mentioned trigger condition Trigger.Self-defined waveform processor judges at first whether trigger condition Trigger is logic high, if then will instruct X1～Xm to carry out one time, otherwise will instruct Y1～Yn to carry out one time.
● when instruction is when waiting for Wait T instruction, judge constantly whether the wait termination condition T of wait instruction appointment satisfies, under situation about satisfying, carry out next bar instruction.Waiting for that termination condition T is the value N of a setting, perhaps is trigger condition Trigger.
When T is a setting value N; When self-defined waveform processor should be instructed in execution; To wait for delay counter assignment N; Each processor clock cycle should wait for that delay counter subtracted 1 and judge whether to be 0, if be not equal to 0 then continue to carry out and subtract 1 and decision operation, if equal 0 then carry out next bar instruction.
When T was Trigger, self-defined waveform processor did not stop to judge the value of Trigger signal, if be to hang down then rest on this wait to instruct always, if be high, then carried out next bar instruction.
The signal condition module, the waveform that self-defined waveform processor is exported carries out digital-to-analog conversion and the output of conditioning back.As shown in Figure 3, the signal condition module comprises FIFO, waveshape monitor, D/A converter and conditioner.The waveform segment data that the self-defined waveform processor of FIFO buffer memory is sent; Waveshape monitor when being used to detect the FIFO non-NULL, sends to D/A converter with the waveform segment data among the FIFO; D/A converter is used for the waveform segment data are carried out digital-to-analog conversion, and the output analog waveform is given conditioner; Conditioner, the waveform that is used for D/A converter output amplifies, export after decay and the bias operation; The multiple and the amount of bias of amplification multiple, decay are provided with by control section.
Preferably, said control section further comprises the information acquisition module, is used for being obtained from from hardware components through first interface unit running state information and the demonstration of definition waveform processor; Said self-defined waveform processor is further used for the running state information of self is sent to control section through second interface unit.
Lift an object lesson below.
At first control section production random waveform waveA, waveB ... waveN; Wherein waveAwaveB ... the waveform segment that waveN representative is different; Cycle, length all can be identical or different; Like waveA is that length is 1000 one-period sine wave, and waveB is two cycle triangular waves of length 2500, and waveB is the one-period sinc function (Singh's function) of length 8000.
Then, through interface unit through store control logic with waveA, waveB ... the Wave data of waveN downloads in the wave memorizer of hardware components.
Then, the user write to waveA, waveB ... the written-out program of waveN provides one section example below.Be control procedure at first exporting waveA, then repeat to export waveB totally 10 times, wait for 100 clock period, judge that then whether ConditionA satisfies, if satisfy then export waveN, otherwise, output waveA.It is thus clear that through control program, can realize the output of complicated random waveform, control is got up also comparatively flexible.
In sum, more than being merely preferred embodiment of the present invention, is not to be used to limit protection scope of the present invention.All within spirit of the present invention and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. the random waveform based on self-defined processor produces system, it is characterized in that, comprising: the control section of AWG and hardware components; Wherein, said control section comprises waveform generation module, waveform download module, control program generation module, collector and first interface unit; Said hardware components comprises second interface unit, self-defined waveform processor, store control logic module, wave memorizer and signal condition module; The waveform download module all is connected first interface unit with collector, and self-defined waveform processor all is connected second interface unit with the store control logic module, and said control section and said hardware components carry out data interaction through interface unit separately;
Said waveform generation module is used to produce the waveform segment data in all kinds, length and cycle, and name respectively, sends to said waveform download module then;
Said waveform download module is used for the waveform segment data that received are downloaded to said hardware components through said first interface unit;
Said store control logic module, realize read-write control to wave memorizer: will from second interface unit receive from the waveform segment data storage of control section to wave memorizer; According to from the specified waveform segment of the call instruction of self-defined waveform processor, from wave memorizer, read and specify the waveform segment data to send to self-defined waveform processor;
Said control program generation module is used to receive the instruction set of outside input, and this instruction set has indicated the waveform segment title that forms required random waveform and need call, called order, call number, and this instruction set is sent to collector;
Said collector is used for said instruction set is compiled as the order code that AWG can be discerned, and downloads to said hardware components through said first interface unit;
Said self-defined waveform processor; Receive and resolve instruction set from control section; Produce the call instruction of respective waveforms section according to the waveform segment title of instruction set indication, send to the store control logic module, and receive the waveform segment data that the store control logic module reads; Call order and call number, said waveform segment data that combination obtains, and export to the signal condition module according to the waveform segment of instruction set indication;
Said signal condition module, the waveform that self-defined waveform processor is exported carries out digital-to-analog conversion and the output of conditioning back.
2. the system of claim 1 is characterized in that, said self-defined waveform processor comprises instruction cache module, instruction translation module;
Instruction cache module is used for the instruction set of buffer memory from second interface unit;
The instruction translation module is used for reading and carry out each bar instruction one by one from said instruction set, and said instruction comprises waveform generation instruction, loop control instruction, conditional branch instructions, wait instruction;
When instruction was instructed for waveform generation, the instruction translation module was extracted the waveform segment title from the waveform generation instruction, produce the call instruction of respective waveforms section, and send to the store control logic module; The waveform segment data that the store control logic module is read send to the signal condition module;
When instruction was loop control instruction, the instruction translation module was carried out the instruction of appointment according to loop control instruction named order and number of cycles;
When instruction was conditional branch instructions, the instruction translation module judged at first whether branch condition is set up, and under the situation that condition is set up, carried out the instruction of appointment;
When instruction was instructed for waiting for, the instruction translation module judged that constantly whether the wait termination condition of waiting for the instruction appointment satisfies, and under situation about satisfying, carries out next bar and instructs.
3. the system of claim 1 is characterized in that, said first interface unit and second interface unit adopt the interface of same type, and this interface adopts any one in USB, PCI, PXI, PCIe and the PXIe interface.
4. the system of claim 1 is characterized in that, said wave memorizer adopts any one in RAM, SDRAM and the DDR2 storer.
5. the system of claim 1 is characterized in that, said signal condition module comprises FIFO, waveshape monitor, D/A converter and conditioner;
FIFO is used for the waveform segment data that the self-defined waveform processor of buffer memory is sent;
Waveshape monitor when being used to detect said FIFO and being non-NULL, sends to D/A converter with the waveform segment data;
D/A converter is used for the waveform segment data are carried out digital-to-analog conversion, and the output analog waveform is given conditioner;
Conditioner is used for that waveform to D/A converter output amplifies, exports after decay and the bias operation.
6. the system of claim 1 is characterized in that, said control section further comprises the information acquisition module, is used for being obtained from from hardware components through first interface unit running state information and the demonstration of definition waveform processor; Said self-defined waveform processor is further used for the running state information of self is sent to control section through second interface unit.
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| CN105005240A (en) * | 2015-07-08 | 2015-10-28 | 中国电子科技集团公司第四十一研究所 | Arbitrary wave generator based on off-line calculation |
| CN107436618A (en) * | 2017-08-08 | 2017-12-05 | 电子科技大学 | A kind of AWG based on instruction architecture |
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| CN110989766A (en) * | 2018-11-16 | 2020-04-10 | 苏州普源精电科技有限公司 | Method and device for constructing arbitrary wave function |
| CN111010178A (en) * | 2019-12-25 | 2020-04-14 | 山东浪潮人工智能研究院有限公司 | PXIe-based arbitrary waveform generator and output channel expansion method |
| CN111077354A (en) * | 2019-12-23 | 2020-04-28 | 中电科仪器仪表(安徽)有限公司 | Device and method for generating user-defined waveform based on FPGA |
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| CN114384288A (en) * | 2022-03-22 | 2022-04-22 | 中星联华科技（北京）有限公司 | Signal generating device |
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| CN108872902B (en) * | 2018-06-29 | 2021-05-28 | 上海东软医疗科技有限公司 | Waveform output method and apparatus |
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| CN111077354A (en) * | 2019-12-23 | 2020-04-28 | 中电科仪器仪表(安徽)有限公司 | Device and method for generating user-defined waveform based on FPGA |
| CN111010178A (en) * | 2019-12-25 | 2020-04-14 | 山东浪潮人工智能研究院有限公司 | PXIe-based arbitrary waveform generator and output channel expansion method |
| CN111010178B (en) * | 2019-12-25 | 2023-07-07 | 山东浪潮科学研究院有限公司 | PXIe-based arbitrary waveform generator and output channel expansion method |
| CN114268087A (en) * | 2021-12-14 | 2022-04-01 | 北京航天测控技术有限公司 | Power supply module and power supply method |
| CN114268087B (en) * | 2021-12-14 | 2023-12-01 | 北京航天测控技术有限公司 | Power supply module and power supply method |
| CN114384288A (en) * | 2022-03-22 | 2022-04-22 | 中星联华科技（北京）有限公司 | Signal generating device |
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Application publication date: 20120627 |