CN106980587B - General input/output time sequence processor and time sequence input/output control method - Google Patents
General input/output time sequence processor and time sequence input/output control method Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The invention relates to a general input/output time sequence processor and a time sequence input/output control method, which consists of a bus interface bridge, a processor register file, a time sequence control state machine, a time sequence generation counter, a time sequence RAM memory and a serial-parallel conversion controller, wherein the processor register file comprises a plurality of sequence control register groups. The beneficial effects of the invention are as follows: the method realizes a universal digital interface protocol, namely, supports the requirement of various digital port input and output time sequence changes and deals with various complicated and changeable digital interface protocols; the chip research and development period is reduced; the power consumption is lower.
Description
Technical Field
The invention relates to the technical field of processors, in particular to a general input/output time sequence processor and a time sequence input/output control method.
Background
In existing chips, if various digital interfaces are to be implemented, their controllers must be incorporated internally. For example, to implement an SPI interface, an SPI controller must be added, to add a UART interface, to add a UART controller, and to implement read and write access to off-chip SRAM, to add an SRAM controller. However, the application scenarios of these chips are not the same for different users. Some customers do not need SPI, but the chip is integrated; while some customers require an XXX interface, the chip is not integrated; some customers require 8-way PWM interfaces, while the chip integrates only 2 ways. The chip integrates the interfaces which are not needed by customers, so that the cost performance is reduced, and unnecessary power consumption is increased. And each interface is designed to be complex, so that the period of chip research, development and production is prolonged, and the cost is increased. Meanwhile, due to the addition of too many interfaces, the chip design is complex, the loopholes are too many, and the probability of error occurrence is increased.
Disclosure of Invention
In view of the foregoing deficiencies of the prior art, the present invention provides a general purpose input/output sequential processor.
The invention provides a general input/output time sequence processor and a time sequence input/output control method, which are realized by the following technical scheme:
a general purpose input output time sequence processor, which is composed of a bus interface bridge, a processor register file, a time sequence control state machine, a time sequence generation counter, a time sequence RAM memory and a serial-parallel conversion controller, wherein the processor register file comprises a plurality of sequence control register groups, and the general purpose input output time sequence processor comprises a plurality of sequence control register groups, wherein:
the bus interface bridge is respectively connected with the processor register file and the time sequence RAM memory, receives various commands of the CPU from the bus and transmits the commands to each register, thereby playing a role in converting a command format;
the processor register file is connected with the time sequence control state machine and is used for temporarily storing processing data of the processor;
the time sequence control state machine is connected with the time sequence generation counter and consists of an instruction fetching controller, a decoder and an executor, wherein the instruction fetching controller is used for reading control codes, the decoder is used for analyzing the codes and translating the codes into codes which are convenient for the executor to execute control, and the executor is used for executing control in cooperation with the counter;
the time sequence generation counter is connected with a time sequence RAM;
the sequential RAM memory is connected with the serial-parallel conversion controller group, the sequential RAM memory stores control codes of each sequence, and is convenient for reading of the sequential state machine and the serial-parallel conversion controller, and the serial-parallel conversion controller is used for completing bit width conversion, reading data from the sequential RAM memory and then sequentially conveying the data to a designated pin;
and each sequence control register group corresponds to 1 sequence control in the sequence control register group.
The serial-parallel controller is bi-directional and can read data from the pins currently set as inputs and write to designated locations of the memory.
A time sequence input/output control method adopts a mode of exchanging data between a chip pin and a RAM, and under the control of a controller, when the data is set as output, the data is read from the RAM and output to the chip pin; when set as input, the data is read from the chip pins and written into RAM. In fig. 2, there are two RAMs, and 1 RAM (data RAM) stores data of an input/output sequence. Data in the RAM is written to the chip pins when output. Data of the read chip pins are written into the RAM when input. The other 1 RAM (direction control RAM) stores an input/output direction selection control sequence of the sequences. Under the control of the controller, sequentially reading input/output direction selection registers of pins of an input/write chip in the RAM along with the occurrence of sequences, controlling the input/output direction of the chip, and simultaneously controlling whether the data RAM is currently read or written according to the direction;
storing one or more sequences in RAM, with only 1 sequence running or no sequence running at the same time; each sequence corresponds to 1 sequence control register group, at least 4 registers are arranged in the group, and the baud rate register is adopted to control the speed of the sequence;
the first address register of the sequence stores the address of the beginning place stored in the RAM of the sequence, and the last address register stores the address of the ending place stored in the RAM of the sequence; the control register indicates the properties of the sequence.
Common attributes are:
1. and (5) controlling the direction flexibility. The direction of the sequence can be controlled by adopting 1 special RAM storage like the one described above, so that the flexibility is high, and the direction can be switched at any time along with the sequence. But it can also be indicated by the attribute that the sequence is only input, only output, or both input and output. If only input or output is indicated, the directional control RAM will not read when this sequence occurs.
2. Serial-parallel conversion arrangement. Described above is a serial-parallel free arrangement. The 1 RAM 1 read or write may be 1 byte (8 bits), 2 bytes (16 bits) or 4 bytes (32 bits) etc. (1 byte is described herein as an example), each bit corresponding to 1 pin of the chip. But there are 1 kind of arrangement with serial-parallel conversion, namely 1 pin corresponds to 1 RAM data, when the pin is to be written into, need to change the data read by RAM each time from parallel to serial into bit stream, send into 1 pin of the chip sequentially; when the pins are to be read, the data on the pins are converted from serial to parallel data and then written into the RAM. When serial-parallel conversion is required, directional control of the sequence, if provided by RAM, is also required for parallel-to-serial conversion of data read out of the directional control RAM. And if provided by the control registers of the present sequence, is not required.
3. And (5) controlling the sequence starting conditions. There may be several sets of sequence control registers in the 1 controller to support multiple sequence occurrences. The starting conditions for each sequence included:
(1) When the designated chip pin has a rising edge;
(2) When the designated chip pin has a falling edge;
(3) When the rising edge or the falling edge occurs to the appointed chip pin;
(4) When the designated chip pin is equal to 0;
(5) When the designated chip pin is equal to 1;
(6) When the input/output time sequence processor receives other CPU commands to start;
(7) Starting when a certain sequence of the specified other input-output sequential processors (a plurality of input-output sequential processors can exist in 1 chip) is started simultaneously with the starting;
(8) Starting when a specified sequence ends;
4. and controlling the size end. Indicating whether the high order or low order bits in the byte were sent first at the time of serial transmission.
The beneficial effects of the invention are as follows:
1. the method realizes a universal digital interface protocol, namely, supports the requirement of various digital port input and output time sequence changes and deals with various complicated and changeable digital interface protocols;
2. each port only needs to support 1 general input/output time sequence processor, so that the chip research and development period is reduced;
3. the power consumption is lower;
4. can be applied to various chips with input and output digital interfaces. The sequential processors can also be classified for simplification according to application scenarios during the application process. For example, timing processors on some ports only support serial input (reading a value on a pin and serializing it into byte data to write it into RAM) or output (deserializing RAM byte data to a pin); some timing processors on ports only support parallel input (e.g., read data on 8 pins simultaneously, write to RAM as 1 byte) or output (e.g., read 1 byte from RAM and output to 8 pins in parallel), without serial-to-parallel conversion; the timing processors on some ports support parallel outputs, do not support parallel inputs, and so on. These are all categories that are designed to simplify the design according to the actual situation.
Drawings
FIG. 1 is a schematic diagram of a general purpose input/output sequential processor;
FIG. 2 is a schematic diagram of a timing input/output control method;
fig. 3 is a serial-parallel conversion arrangement schematic.
Detailed Description
The technical solutions of the present invention will be clearly and completely described below by means of examples, and it is obvious that the described examples are only some, but not all, examples of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
English abbreviations in the text are defined: CPU: a central processing unit; GPIO (general purpose input/output) the method comprises the following steps: a general purpose input/output port; a MUX: a multiplexer; IIC: an integrated circuit bus; UART: a universal asynchronous receiver transmitter; PWM: pulse width modulation; RAM: a random access memory; SPI: a serial peripheral interface; peripheral IP: in the reusable design methodology of integrated circuits, IP core, commonly known as intellectual property core (English: intellectual property core), refers to a reusable module provided by a party in the form of a logic unit, chip design.
Example 1:
a general-purpose input/output time sequence processor shown in figure 1 is composed of a bus interface bridge, a processor register file, a time sequence control state machine, a counter, a time sequence RAM memory and a serial-parallel conversion controller.
The bus interface bridge is used to receive various commands of the CPU from the bus and pass them to the various registers. Playing a role in command format conversion.
The processor register file internally comprises a plurality of sequence control register sets (each register set corresponds to 1 sequence control) for temporarily storing processing data of the processor. The sequence head address register records the start address of the memory access where the sequence is to occur and the sequence tail address register records the end address of the memory where the sequence is to occur. The sequence control register has directional flexibility control, serial-parallel conversion, starting condition, size end control, sequence length control, occurrence frequency control, bit enabling and the like.
The sequence length controls the length of the sequence to be generated and the number of times the sequence is generated. The maximum value of the sequence length is limited by the size of the memory, and the capacity of the time sequence memory is determined according to the application scene and the system specification. The larger the capacity, the larger the maximum value of the sequence length. The minimum sequence length is 1 bit. Note also that more than 1 sequence is stored in the memory, and that multiple sequences may be stored. The sequence and the times of each sequence can be controlled by a program.
The number of occurrences of each sequence ranges from only 1 to an infinite number (i.e., continuous occurrences). The conditions for each sequence start were: 1. is directly started under the control of a CPU; 2. when a certain sequence is ended or is started simultaneously with the certain sequence; 3. these conditions are preset by the CPU into the control registers when a specified rising edge, falling edge, edge (rising edge or falling edge), equal to 0 or equal to 1 occurs on the input pins. The sequence speed register controls the speed at which the sequence is run to occur, i.e., how many clock cycles each bit occupies. Supporting different speed settings per sequence.
The bit enable determines which pins are involved in this sequence.
The sequence generation control state machine is a central controller, determines each step of the sequence generation, and is implemented. The counter matched with the counter plays a role of timing auxiliary control. The sequencer control state machine consists of 3 controllers. The finger extractor is used for reading the control codes, and the decoder is used for analyzing the codes and translating the codes into codes which are convenient for the executor to execute control. And the executor is used for cooperating with the counter to implement control.
The sequential RAM memory stores control codes of each sequence, and is convenient for reading of a sequence state machine and a serial-parallel conversion controller. The CPU can access this RAM memory like it would access a normal RAM memory, so this RAM memory can be used as a normal memory for the CPU when the timing processor is not operating.
Because the bit widths of the data read from and written to the memory are fixed, the number of pins to which each sequence is applied is different, and the pin numbers are also different. For example, sequence A controls 4 pins, pins 0,1,2,3, respectively; sequence B controls 8 pins, pins 0,1,5,6,10,11,12,13, respectively. A serial-to-parallel controller is required to accomplish this conversion operation. The serial-parallel conversion controller is used for completing bit width conversion, and is decided by the central controller, reads data from the memory and then sequentially transmits the data to the formulated pins. Meanwhile, the serial-parallel conversion controller is bidirectional, reads data from a pin currently set as an input, and writes the data into a designated position of the memory.
Example 2
In a time sequence input/output control method shown in fig. 2, a mode of exchanging data between a chip pin and a RAM is adopted, and under the control of a controller, when the data is set as output, the data is read from the RAM and output to the chip pin; when the input is set to be an input, data is read from the chip pins and written into RAM. In fig. 2, there are two RAMs, and 1 RAM (data RAM) stores data of an input/output sequence. Data in the RAM is written to the chip pins when output. Data of the read chip pins are written into the RAM when input. The other 1 RAM (direction control RAM) stores an input/output direction selection control sequence of the sequences. Under the control of the controller, sequentially reading input/output direction selection registers of pins of an input/write chip in the RAM along with the occurrence of sequences, controlling the input/output direction of the chip, and simultaneously controlling whether the data RAM is currently read or written according to the direction;
storing one or more sequences in RAM, with only 1 sequence running or no sequence running at the same time; each sequence corresponds to 1 sequence control register group, at least 4 registers are arranged in the group, and the baud rate register is adopted to control the speed of the sequence;
the sequence first address register stores the beginning address of the sequence stored in RAM, the tail address register stores the end address of the sequence stored in the RAM; the control register indicates the properties of the sequence.
Common attributes are:
1. and (5) controlling the direction flexibility. The direction of the sequence can be controlled by adopting 1 special RAM storage like the one described above, so that the flexibility is high, and the direction can be switched at any time along with the sequence. But it can also be indicated by the attribute that the sequence is only input, only output, or both input and output. If only input or output is indicated, the directional control RAM will not read when this sequence occurs.
2. Serial-parallel conversion arrangement. Described above is a serial-parallel free arrangement. The 1 RAM 1 read or write may be 1 byte (8 bits), 2 bytes (16 bits) or 4 bytes (32 bits) etc. (1 byte is described herein as an example), each bit corresponding to 1 pin of the chip. But there are 1 kind of arrangement with serial-parallel conversion, namely 1 pin corresponds to 1 RAM data, when the pin is to be written into, need to change the data read by RAM each time from parallel to serial into bit stream, send into 1 pin of the chip sequentially; when the pins are to be read, the data on the pins are converted from serial to parallel data and then written into the RAM. When serial-to-parallel conversion is required, as shown in fig. 3, if directional control of the sequence is provided by the RAM, the data read out from the directional control RAM is also converted from parallel to serial. And if provided by the control registers of the present sequence, is not required.
3. And (5) controlling the sequence starting conditions. There may be several sets of sequence control registers in the 1 controller to support multiple sequence occurrences. The starting conditions for each sequence included:
(1) When the designated chip pin has a rising edge;
(2) When the designated chip pin has a falling edge;
(3) When the rising edge or the falling edge occurs to the appointed chip pin;
(4) When the designated chip pin is equal to 0;
(5) When the designated chip pin is equal to 1;
(6) When the input/output time sequence processor receives other CPU commands to start;
(7) Starting when a certain sequence of the specified other input-output sequential processors (a plurality of input-output sequential processors can exist in 1 chip) is started simultaneously with the starting;
(8) Starting when a specified sequence ends;
4. and controlling the size end. Indicating whether the high order or low order bits in the byte were sent first at the time of serial transmission.
The foregoing examples are merely illustrative of embodiments of the present invention and are described in more detail without limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention.
Claims (3)
1. A general purpose input output sequential processor, characterized by: the system consists of a bus interface bridge, a processor register file, a time sequence control state machine, a time sequence generation counter, a time sequence RAM memory and a serial-parallel conversion controller, wherein the processor register file comprises a plurality of sequence control register groups, and the system comprises the following components:
the bus interface bridge is respectively connected with the processor register file and the time sequence RAM memory, receives various commands of the CPU from the bus and transmits the commands to each register, thereby playing a role in converting a command format;
the processor register file is connected with the time sequence control state machine and is used for temporarily storing processing data of the processor;
the time sequence control state machine is connected with the time sequence generation counter and consists of an instruction fetching controller, a decoder and an executor, wherein the instruction fetching controller is used for reading control codes, the decoder is used for analyzing the codes and translating the codes into codes which are convenient for the executor to execute control, and the executor is used for executing control in cooperation with the counter;
the time sequence generation counter is connected with a time sequence RAM;
the sequential RAM memory is connected with the serial-parallel conversion controller group, the sequential RAM memory stores control codes of each sequence, and is convenient for reading of the sequential state machine and the serial-parallel conversion controller, and the serial-parallel conversion controller is used for completing bit width conversion, reading data from the sequential RAM memory and then sequentially transmitting the data to a designated pin.
2. The universal input output sequential processor of claim 1, wherein: and each sequence control register group corresponds to 1 sequence control in the sequence control register group.
3. The universal input output sequential processor of claim 1, wherein: the serial-parallel controller is bi-directional and can read data from the pins currently set as inputs and write to designated locations of the memory.
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| CN201418086Y (en) * | 2007-12-05 | 2010-03-03 | 中国科学院空间科学与应用研究中心 | Data communication protocol controller used for satellite-borne equipment |
| CN206975631U (en) * | 2017-05-12 | 2018-02-06 | 葛松芬 | A kind of universal input output timing processor |
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| CN201418086Y (en) * | 2007-12-05 | 2010-03-03 | 中国科学院空间科学与应用研究中心 | Data communication protocol controller used for satellite-borne equipment |
| CN206975631U (en) * | 2017-05-12 | 2018-02-06 | 葛松芬 | A kind of universal input output timing processor |
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