CN113824741A - IIC device communication method, apparatus, device, system and medium - Google Patents

IIC device communication method, apparatus, device, system and medium Download PDF

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Publication number
CN113824741A
CN113824741A CN202111389893.XA CN202111389893A CN113824741A CN 113824741 A CN113824741 A CN 113824741A CN 202111389893 A CN202111389893 A CN 202111389893A CN 113824741 A CN113824741 A CN 113824741A
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iic
data
master
protocol
equipment
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季冬冬
张广乐
王金友
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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Priority to CN202111389893.XA priority Critical patent/CN113824741A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/08—Protocols for interworking; Protocol conversion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)

Abstract

The invention discloses a communication method, a device, equipment, a system and a medium of IIC equipment; in the scheme, when the IIC controller is communicated with the IIC equipment, the IIC MUX is not required to be additionally arranged, the communication between the IIC controller and the IIC equipment can be realized only by converting data between the PCIe protocol and the IIC protocol through the FPGA equipment, and the mode can reduce hardware cost increase and layout pressure brought by the IIC MUX.

Description

IIC device communication method, apparatus, device, system and medium
Technical Field
The present invention relates to the field of data communication technologies, and in particular, to a communication method, apparatus, device, system, and medium for an IIC device.
Background
A CPLD (Complex Programmable Logic Device)/FPGA (Field Programmable Gate Array) is a semi-customized application-specific integrated circuit, has a series of advantages of flexible programming, fast response, high integration level, and the like, and is increasingly widely applied in the Field of development, verification, and control applications in the early stage. In the switch system, control logic is realized mainly through a CPLD, for example, the power-on and power-off sequence control, communication control, key detection, fan rotating speed control, SFP (Small Form-factor plug, optical module) lighting control, serial port switching and the like of the whole switch are controlled through a CPLD chip, and the CPLD controlled by the sequence is designed into a double mirror image, so that the reliable operation of the CPLD is ensured; high-speed data management, such as IIC (Inter-Integrated Circuit bus) device management and PHY (Physical Layer) management, is realized by the FPGA. The CPLD/FPGA management is realized by an MCU (Microcontroller Unit), so that management of downstream devices, such as VR (Virtual Reality) management, Sensor management, and FRU (Field replaceable Unit) management, is realized.
IIC equipment management is an important component of switch management and is a mature application design. In general design, a CPU (Central processing Unit)/BMC (Baseboard Management Controller) directly connects an IIC device through an IIC, and when IIC controllers such as the CPU or the BMC are limited, an IIC MUX (multiplexer) is connected to an IIC link, thereby realizing IIC link extension. It can be seen that currently when IIC controllers are limited, they must be implemented via IIC MUXs, which can result in increased hardware cost and increased Layout of Layout.
Disclosure of Invention
The invention aims to provide a communication method, a communication device, communication equipment, communication system and communication medium of IIC equipment, so as to realize the control of an IIC controller on a plurality of IIC equipment on the basis of reducing hardware cost and layout.
In order to achieve the above object, the present invention provides a communication method for an IIC device, including:
the FPGA equipment receives first data sent by the IIC controller through a PCIe protocol;
converting the first data into an IIC protocol and sending the IIC protocol to corresponding target IIC equipment;
acquiring second data returned by the target IIC equipment through an IIC protocol;
and converting the second data into a PCIe protocol and sending the PCIe protocol to the IIC controller.
The converting the first data into the IIC protocol and sending the IIC protocol to the corresponding target IIC device includes:
the FPGA equipment analyzes the first data through PCIe Endpoint and stores a generated analysis result to an IIC Master sending data register of the FPGA equipment; the analysis result comprises sending data;
and sending the sending data to the corresponding IIC Master, and sending the sending data to the corresponding IIC controller through the IIC Master through an IIC protocol.
Wherein the communication method further comprises:
if the analysis result comprises communication frequency data, storing the communication frequency data to an IIC Master frequency setting register so as to set the communication frequency of each C Master through the communication frequency data;
if the analysis result comprises enable data, storing the enable data to an IIC Master control register so as to set the enable state of each IIC Master through the enable data;
and if the analysis result comprises command data, storing the command data to an IIC Master command register so as to control each IIC Master to execute corresponding behavior operation through the command data.
The obtaining of the second data returned by the target IIC device through the IIC protocol includes:
and the FPGA equipment acquires second data returned by the target IIC equipment through the IIC protocol through the IIC Master.
Wherein converting the second data into a PCIe protocol and sending the PCIe protocol to the IIC controller includes:
and if the second data is return data, storing the return data to an IIC Master receiving data register of the FPGA equipment, so that the IIC controller obtains the return data by reading the IIC Master receiving data register.
Wherein the communication method further comprises:
and storing the state data of each IIC Master and the state data of each IIC Device into an IIC Master state register so that the IIC controller can obtain the state data of each IIC Master and the state data of each IIC Device by reading the IIC Master state register.
To achieve the above object, the present invention further provides a communication apparatus of an IIC device, including:
the receiving module is used for receiving first data sent by the IIC controller through a PCIe protocol through the FPGA equipment;
the first conversion module is used for converting the first data into an IIC protocol and sending the IIC protocol to corresponding target IIC equipment;
the acquisition module is used for acquiring second data returned by the target IIC equipment through an IIC protocol;
and the second conversion module is used for converting the second data into a PCIe protocol and sending the PCIe protocol to the IIC controller.
To achieve the above object, the present invention further provides an FPGA device, comprising: a memory for storing a computer program; a processor for implementing the steps of the communication method of the IIC device described above when executing the computer program.
In order to achieve the above object, the present invention further provides a communication system of an IIC device, including the above FPGA device, and an IIC controller and an IIC device connected to the FPGA device.
To achieve the above object, the present invention further provides a computer-readable storage medium having stored thereon a computer program that, when being executed by a processor, implements the steps of the communication method of the above IIC device.
According to the above scheme, the communication method for the IIC device provided by the embodiment of the present invention includes: the FPGA equipment receives first data sent by the IIC controller through a PCIe protocol; converting the first data into an IIC protocol, and sending the IIC protocol to corresponding target IIC equipment; acquiring second data returned by the target IIC equipment through the IIC protocol; and converting the second data into a PCIe protocol and sending the PCIe protocol to the IIC controller. Therefore, in the scheme, when the IIC controller is communicated with the IIC equipment, the IIC MUX is not required to be additionally arranged, the communication between the IIC controller and the IIC equipment can be realized only by converting data between the PCIe protocol and the IIC protocol through the FPGA equipment, and the hardware cost increase and the layout pressure brought by the IIC MUX can be reduced by the method; the invention also discloses a communication device, equipment, a system and a medium of the IIC equipment, and the technical effects can be realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a communication system of an IIC device according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a specific IIC device communication system according to an embodiment of the present invention;
fig. 3 is a flowchart illustrating a communication method of an IIC device according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a communication device of an IIC device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention discloses a communication method, a device, equipment, a system and a medium of IIC equipment, aiming at solving the communication problem that the IIC controller accesses the IIC equipment.
For the sake of clarity, the communication system of an IIC device provided in the present embodiment is described first. Referring to fig. 1, a schematic structural diagram of a communication system of an IIC device according to an embodiment of the present invention is provided, in this scheme, the communication system specifically includes: IIC controller 11, FPGA device 12 and IIC device 13. In this embodiment, the IIC controller may be specifically a CPU or a BMC, which is not specifically limited herein; the IIC controller is mainly communicated with the IIC device through the FPGA device, and therefore management and control over the IIC device are achieved. In this embodiment, the data that the IIC controller needs to send to the IIC device through the FPGA device is used as the first data, and the specific content of the first data is not limited in this embodiment, and may be any data that needs to be sent to the IIC device. In this embodiment, the IIC controller specifically sends the first data to the FPGA device through PCIe (peripheral component interconnect express).
It should be noted that PCIe communication needs to be implemented through a PCIe hard core, so that the FPGA device needs to support the PCIe hard core, and a user only needs to pay attention to data TLP information, and does not need to pay attention to the exchange of data in a physical layer, a data link layer, and a transport layer, which is convenient for user design, and the communication is more stable and reliable due to the hard core design. Therefore, in the scheme, a PCIe Endpoint (PCIe Endpoint) is implemented in the FPGA device through the hard core, so that PCIe communication between the CPU and the FPGA device is implemented. The function depends on the IO (Input Output) support of the FPGA device itself, that is, high-speed IO is realized. Many PCIe communication application occasions for realizing the CPU and the FPGA equipment are provided, and the aim is to realize the PCIe high-speed communication between the CPU and the FPGA equipment. Different hardmac configuration interfaces are provided for development tools of different manufacturers, but basic configuration items are the same, and the function also depends on whether the FPGA supports the hardware configuration interfaces.
Referring to fig. 2, a schematic structural diagram of a specific IIC device communication system according to an embodiment of the present invention is shown, in which an IIC controller is only taken as an example of a CPU. The central processing unit is provided with a Root node (PCIe Root, PCIe Root node), a field programmable gate array Device (FPGA Device) is provided with an Endpoint (PCIe Endpoint ), a total register (Registers) and a plurality of control nodes (IIC Master, IIC control node), and each control node is connected with corresponding Device (IIC Device ). After receiving the data sent by the CPU, the FPGA device accesses the driver IIC MASTER through the general register, and in this scheme, IIC MASTER design is implemented through a WishBone standard interface, which conforms to general design. Specifically, each Wishbone interface IIC MASTER is connected to the IIC Device interface through SCL (clock signal line) and SDA (bidirectional data line), and the signals of the Wishbone interface include: wb _ clk (Wishbone clock signal), wb _ rst (reset signal), wb _ cyc (transfer instruction signal), wb _ stb (core select signal), wb _ ack (response signal), wb _ addr (address signal), wb _ datain (input data), wb _ dataout (output data). After a single IIC Master is designed, the design is copied in the FPGA based on the parallel characteristic of the FPGA, so that a multi-IIC Master scheme is realized, and each IIC Master corresponds to one IIC device.
The CPU sends first data of a PCIe protocol to the FPGA equipment through PCIe, and the FPGA equipment converts the first data protocol of the PCIe protocol into IIC protocol data and then sends the IIC protocol data to the IIC equipment through the IIC Master, so that the CPU manages and controls the IIC equipment; the conversion between the PCIe protocol and the IIC protocol specifically means that the CPU accesses a general register of the FPGA device through PCIe, and the FPGA device controls the IIC Master behavior through the general register, thereby implementing communication between the CPU and the IIC device, and further implementing management control of the CPU on the IIC device. Namely: the CPU sends data to the PCIe Endpoint through the PCIe Root, the PCIe Endpoint is analyzed and then stored in Registers, the data stored in the Registers are sent to the corresponding IIC Master, and the data are sent to the corresponding IIC Device through the IIC Master.
Therefore, the communication between the CPU and the IIC equipment is realized through the FPGA equipment, so that on one hand, the hardware cost increase and the Layout pressure of the Layout of the CPU and the Layout of the; on the other hand, the unified PCIe design of the CPU end is convenient for the CPU to manage the IIC equipment, so that the design is more standard; moreover, the PCIe to IIC design realized through the FPGA device makes the design more flexible due to the programmable characteristic of the FPGA.
Referring to fig. 3, a schematic flow chart of a communication method of an IIC device provided in an embodiment of the present invention specifically includes the following steps:
s101, receiving first data sent by an IIC controller through a PCIe protocol by FPGA equipment, converting the first data into the IIC protocol, and sending the IIC protocol to corresponding target IIC equipment;
in the scheme, the IIC controller and the FPGA device realize communication through PCIE, so that first data sent to the FPGA device by the IIC controller is a PCIE protocol; the PCIe high-speed communication solves the problem that the CPU limits the speed, and meanwhile, the general PCIe communication enables the CPU to operate more conveniently.
Specifically, when the FPGA device receives first data sent by the IIC controller through the PCIe protocol through the PCIe Endpoint, converts the first data into the IIC protocol and sends the IIC protocol to the corresponding target IIC device, the FPGA device is required to analyze the first data through the PCIe Endpoint and store a generated analysis result to an IIC Master sending data register of the FPGA device; then sending the sending data to a corresponding IIC Master, and sending the sending data to a corresponding IIC controller through an IIC protocol through the IIC Master; the analysis result includes the sending data and an address, the address is specifically the address of the register in the IIC Master, and wb _ addr in the Wishbone interface has a corresponding relation with the address. Namely: the analysis result analyzed by the PCIe Endpoint includes an address and data, and the address can determine to which IIC Master the IIC controller specifically sends data, where the data may include sending data, communication frequency data, enable data, command data, and the like.
Such as: the general register comprises an IIC Master sending data register, the IIC Master sending data register stores sending data which needs to be sent to IIC equipment by an IIC controller, the IIC controller sets the register value through PCIe to set the sending data of the IIC Master, and the IIC Master sending data register and wb _ datain a Wishbone interface have a corresponding relation; the general register also comprises an IIC Master frequency setting register, the IIC Master frequency setting register is used for storing communication frequency data of the IIC Master, namely the frequency of the SCL, and the CPU sets the IIC Master frequency through the PCIe setting register value; the general register also comprises an IIC Master control register, the IIC Master control register is used for storing enabling data, whether the IIC Master is enabled or not and is enabled by interruption or not can be set through the enabling data, and the CPU specifically sets the IIC Master to be enabled and whether the IIC Master is allowed to be interrupted or not through the PCIe setting register value; the general register further comprises an IIC Master command register, the IIC Master command register stores command data and is used for controlling IIC Master behaviors, and the CPU specifically sets start, stop, read operation, write operation and ACK (Acknowledge character) signals of the IIC Master through PCIe setting register values.
Therefore, in the present application, if the analysis result includes communication frequency data, the communication frequency data is stored in the IIC Master frequency setting register, so as to set the communication frequency of each C Master through the communication frequency data; if the analysis result comprises enable data, storing the enable data to an IIC Master control register so as to set the enable state of each IIC Master through the enable data; if the analysis result comprises command data, the command data is stored in the IIC Master command register so as to control each IIC Master to execute corresponding behavior operation through the command data.
And S102, acquiring second data returned by the target IIC equipment through the IIC protocol, converting the second data into a PCIe protocol, and sending the PCIe protocol to the IIC controller.
In this embodiment, the FPGA device specifically obtains, through the IIC Master, second data returned by the target IIC device through the IIC protocol. In addition, in a manner similar to the manner of converting the first data into the IIC protocol, the IIC Master receiving data register for storing the return data is also arranged in the general register, the IIC Master receiving data register has a corresponding relationship with wb _ dataout in the Wishbone interface, the IIC Master receiving data register stores the return data of the IIC device, and the IIC controller obtains the return data of the IIC device by reading the register; therefore, in the present application, if the second data is the return data, the return data is stored in the IIC Master receiving data register of the FPGA device, so that the IIC controller obtains the return data by reading the IIC Master receiving data register.
Further, in this embodiment, the data returned by the IIC Device further includes state data of each IIC Device, and therefore in this solution, an IIC Master state register needs to be further set in the general register, the IIC Master state register has a corresponding relationship with wb _ ack in the Wishbone interface, and the IIC Master state register is used to store the state data of each IIC Master and/or the state data of each IIC Device, and therefore in this solution, the state data of each IIC Master and the state data of each IIC Device need to be stored in the IIC Master state register, so that the IIC controller obtains the state data of each IIC Master and the state data of each IIC Device by reading the IIC Master state register. The status data may indicate that the IIC Master/IIC Device is functioning properly.
In summary, in the scheme, the protocol conversion from PCIe to IIC can be realized based on the FPGA device, so that the management control of the CPU on the IICshebei is realized. From the performance aspect: the CPU only needs to manage PCIe interfaces, so that the CPU management is facilitated; in terms of hardware cost, the hardware cost increase caused by the use of the IIC MUX is avoided; from the Layout of the Layout, the Layout pressure brought by the use of the IIC MUX is reduced; from the aspect of flexibility, the FPGA belongs to a semi-customized special integrated chip, has the characteristics of programmability and the like, and is more flexible to use; moreover, the PCIe protocol conversion and the IIC protocol conversion realized based on the FPGA device of the programmable device and the IIC Master design based on the Wishbone enable the whole design to be more flexible and convenient.
The following describes a communication apparatus, a device, and a storage medium according to embodiments of the present invention, and the communication apparatus, the device, and the storage medium described below and the communication method described above may be referred to each other.
Referring to fig. 4, a schematic structural diagram of a communication apparatus of an IIC device provided in an embodiment of the present invention includes:
the receiving module 21 is configured to receive, through the FPGA device, first data sent by the IIC controller through a PCIe protocol;
the first conversion module 22 is configured to convert the first data into an IIC protocol, and send the IIC protocol to a corresponding target IIC device;
the obtaining module 23 is configured to obtain second data returned by the target IIC device through an IIC protocol;
and the second conversion module 24 is configured to convert the second data into a PCIe protocol, and send the PCIe protocol to the IIC controller.
Wherein the receiving module is specifically configured to: and receiving first data sent by the IIC controller through a PCIe protocol through a PCIe Endpoint of the FPGA device.
Wherein the first conversion module comprises:
the analyzing unit is used for analyzing the first data through PCIe Endpoint of the FPGA device;
the first storage unit is used for storing the generated analysis result to an IIC Master sending data register of the FPGA equipment; the analysis result comprises sending data;
and the sending unit is used for sending the sending data to the corresponding IIC Master and sending the sending data to the corresponding IIC controller through the IIC Master through an IIC protocol.
Wherein the communication device further comprises:
the first storage module is used for storing the communication frequency data to an IIC Master frequency setting register when the analysis result comprises the communication frequency data so as to set the communication frequency of each C Master through the communication frequency data;
the second storage module is used for storing the enabling data to an IIC Master control register when the analysis result comprises the enabling data so as to set the enabling state of each IIC Master through the enabling data;
and the third storage module is used for storing the command data to the IIC Master command register when the analysis result comprises the command data so as to control each IIC Master to execute corresponding behavior operation through the command data.
Wherein the obtaining module is specifically configured to: and acquiring second data returned by the target IIC equipment through an IIC protocol through the IIC Master of the FPGA equipment.
Wherein the second conversion module comprises:
and the second storage unit is used for storing the return data to an IIC Master receiving data register of the FPGA device when the second data is the return data, so that the IIC controller obtains the return data by reading the IIC Master receiving data register.
Wherein the communication device further comprises:
and the fourth storage module is used for storing the state data of each IIC Master and the state data of each IIC Device into the IIC Master state register so that the IIC controller can obtain the state data of each IIC Master and the state data of each IIC Device by reading the IIC Master state register.
The embodiment of the invention also provides a structural schematic diagram of the FPGA equipment, which comprises the following steps:
a memory for storing a computer program;
a processor for implementing the steps of the communication method of the IIC device described in the above method embodiments when executing the computer program.
The embodiment of the present invention further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the computer program implements the steps of the communication method of the IIC device in the above-mentioned method embodiment.
Wherein the storage medium may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A communication method of an IIC device, comprising:
the FPGA equipment receives first data sent by the IIC controller through a PCIe protocol;
converting the first data into an IIC protocol and sending the IIC protocol to corresponding target IIC equipment;
acquiring second data returned by the target IIC equipment through an IIC protocol;
and converting the second data into a PCIe protocol and sending the PCIe protocol to the IIC controller.
2. The communication method according to claim 1, wherein the converting the first data into the IIC protocol and transmitting the IIC protocol to a corresponding target IIC device comprises:
the FPGA equipment analyzes the first data through PCIe Endpoint and stores a generated analysis result to an IIC Master sending data register of the FPGA equipment; the analysis result comprises sending data;
and sending the sending data to the corresponding IIC Master, and sending the sending data to the corresponding IIC controller through the IIC Master through an IIC protocol.
3. The communication method according to claim 2, further comprising:
if the analysis result comprises communication frequency data, storing the communication frequency data to an IIC Master frequency setting register so as to set the communication frequency of each C Master through the communication frequency data;
if the analysis result comprises enable data, storing the enable data to an IIC Master control register so as to set the enable state of each IIC Master through the enable data;
and if the analysis result comprises command data, storing the command data to an IIC Master command register so as to control each IIC Master to execute corresponding behavior operation through the command data.
4. The communication method according to claim 1, wherein the obtaining of the second data returned by the target IIC device via the IIC protocol comprises:
and the FPGA equipment acquires second data returned by the target IIC equipment through the IIC protocol through the IIC Master.
5. The communication method of claim 4, wherein converting the second data to a PCIe protocol and sending the PCIe protocol to the IIC controller comprises:
and if the second data is return data, storing the return data to an IIC Master receiving data register of the FPGA equipment, so that the IIC controller obtains the return data by reading the IIC Master receiving data register.
6. The communication method according to any one of claims 1 to 5, characterized in that the communication method further comprises:
and storing the state data of each IIC Master and the state data of each IIC Device into an IIC Master state register so that the IIC controller can obtain the state data of each IIC Master and the state data of each IIC Device by reading the IIC Master state register.
7. A communication apparatus of an IIC device, comprising:
the receiving module is used for receiving first data sent by the IIC controller through a PCIe protocol through the FPGA equipment;
the first conversion module is used for converting the first data into an IIC protocol and sending the IIC protocol to corresponding target IIC equipment;
the acquisition module is used for acquiring second data returned by the target IIC equipment through an IIC protocol;
and the second conversion module is used for converting the second data into a PCIe protocol and sending the PCIe protocol to the IIC controller.
8. An FPGA device, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the communication method of the IIC device as claimed in any one of claims 1 to 6 when executing the computer program.
9. A communication system of an IIC device, comprising the FPGA device as claimed in claim 8, and an IIC controller and an IIC device connected to the FPGA device.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a computer program which, when being executed by a processor, realizes the steps of the communication method of the IIC device according to any one of claims 1 to 6.
CN202111389893.XA 2021-11-23 2021-11-23 IIC device communication method, apparatus, device, system and medium Pending CN113824741A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
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CN114443545A (en) * 2022-04-02 2022-05-06 飞腾信息技术有限公司 Interface expansion method, device, management system and related equipment
CN116627514A (en) * 2023-05-29 2023-08-22 合芯科技有限公司 I2c equipment management method, device, equipment and storage medium

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CN114443545A (en) * 2022-04-02 2022-05-06 飞腾信息技术有限公司 Interface expansion method, device, management system and related equipment
CN114443545B (en) * 2022-04-02 2022-07-08 飞腾信息技术有限公司 Interface expansion method, device, management system and related equipment
CN116627514A (en) * 2023-05-29 2023-08-22 合芯科技有限公司 I2c equipment management method, device, equipment and storage medium
CN116627514B (en) * 2023-05-29 2024-04-26 合芯科技有限公司 I2c equipment management method, device, equipment and storage medium

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