CN110765065A

CN110765065A - System on chip

Info

Publication number: CN110765065A
Application number: CN201910849550.3A
Authority: CN
Inventors: 崔明章; 刘锴; 马得尧; 李锋
Original assignee: Guangdong High Cloud Semiconductor Technologies Ltd Co
Current assignee: Guangdong High Cloud Semiconductor Technologies Ltd Co; Gowin Semiconductor Corp
Priority date: 2019-09-09
Filing date: 2019-09-09
Publication date: 2020-02-07

Abstract

The invention relates to the field of semiconductor chips and discloses a system on a chip, which comprises an MCU (microprogrammed control Unit) core, an FPGA (field programmable gate array) core and a system bus; the system bus is connected with the FPGA kernel and the MCU kernel and used for realizing interaction between the MCU kernel and the FPGA kernel; the FPGA kernel comprises an ADC analog-to-digital conversion unit connected with the system bus, and the ADC analog-to-digital conversion unit is used for receiving an analog signal provided by external equipment, converting the analog signal into a first digital signal and sending the first digital signal to the MCU kernel through the system bus. The system on chip provided by the invention has an analog-to-digital conversion function, can reduce the complexity of chip design, shortens the product development period and reduces the product development cost.

Description

System on chip

Technical Field

The invention relates to the field of semiconductor chips, in particular to a system on a chip.

Background

With the rapid development of information technology, it is increasingly difficult for a general-purpose processor to meet increasingly large and diversified data processing requirements in terms of computing performance. It has become a new trend to improve the computing performance by means of a system on chip (which may be expressed as a heterogeneous computing platform in some cases) composed of an FPGA (field programmable gate array) and an MCU (micro control unit). At present, an FPGA and an MCU in the same system on chip can exert the advantages which are not possessed by the traditional FPGA and CPU discrete devices, and meet the functional requirements of some systems, but aiming at the fields of industrial control and the like, the system on chip is often matched with a discrete analog-to-digital conversion unit for use, and then the corresponding industrial production requirements in the field of industrial control can be met. Therefore, in the prior art, a dedicated system-on-chip is often required to be designed for adapting the analog-to-digital conversion unit, or a dedicated analog-to-digital conversion unit is often required to be designed for adapting the system-on-chip. The scheme focuses on any one, the development period of the product can be greatly prolonged, and the development cost of the product is improved.

Disclosure of Invention

Therefore, it is necessary to provide a system on chip to integrate the analog-to-digital conversion function, reduce the design complexity of the special chip, shorten the product development cycle, and reduce the product development cost.

A system on chip comprises an MCU core, an FPGA core and a system bus;

the system bus is connected with the FPGA kernel and the MCU kernel and used for realizing interaction between the MCU kernel and the FPGA kernel;

the FPGA kernel comprises an ADC analog-to-digital conversion unit connected with the system bus, and the ADC analog-to-digital conversion unit is used for receiving an analog signal provided by external equipment, converting the analog signal into a first digital signal and sending the first digital signal to the MCU kernel through the system bus.

Optionally, the ADC analog-to-digital conversion unit includes an APB extension interface, an ADC interface, and an ADC controller, and the system bus includes an APB bus;

the ADC interface is connected with the ADC controller and used for outputting analog signals acquired from external equipment to the ADC controller;

the ADC controller is connected with the APB expansion interface and is used for converting the analog signal received by the ADC interface into a first digital signal and outputting the first digital signal to the APB expansion interface;

the APB extension interface is connected with the APB bus and used for outputting the first digital signal received from the ADC controller to the MCU core through the APB bus.

Optionally, the ADC controller comprises:

the APB slave device manager is connected with an external APB host through the APB interface and is used for realizing the interaction between the MCU kernel and the external APB host;

and the ADC analog-to-digital conversion control circuit is connected with the APB slave equipment manager and is used for converting the analog signal into a first digital signal according to preset configuration information.

Optionally, the system bus is arranged in the MCU core, and the MCU core includes a core circuit connected to the system bus; the system bus is used for realizing the interaction between the kernel circuit and the FPGA kernel;

and after the ADC analog-to-digital conversion unit converts an analog signal provided by external equipment into a first digital signal, the first digital signal is sent to the core circuit through the system bus.

Optionally, the FPGA core includes a clock unit and a reset unit;

the clock unit is connected with the MCU kernel and used for providing a time signal; the MCU core and the FPGA core share the time signal provided by the clock unit;

the reset unit is connected with the MCU kernel and used for providing a reset signal; the MCU core and the FPGA core share the reset signal provided by the reset unit.

Optionally, the system on chip comprises an on chip memory, the system bus comprises an AHB bus; the on-chip memory comprises a read-only memory and a random access memory;

the read-only memory is connected with the MCU kernel through the AHB bus and is used for realizing interaction and reading operation with the MCU kernel;

the random access memory is connected with the MCU kernel through the AHB bus and is used for realizing interaction with the MCU kernel, reading operation, writing operation and erasing operation.

Optionally, the MCU core includes a general input output interface, and the system bus includes an AHB bus connected to the general input output interface;

and the universal input and output interface is connected with the FPGA kernel and is used for realizing the interaction between the MCU kernel and the FPGA kernel.

Optionally, the MCU core includes a universal asynchronous transfer interface, and the system bus includes an APB bus connected to the universal asynchronous transfer interface;

and the universal asynchronous transmission interface is connected with the FPGA kernel and is used for realizing the interaction between the MCU kernel and the FPGA kernel.

Optionally, the system bus includes an APB bus and an AHB bus, the APB bus is used for mounting a low-speed external device, and the AHB bus is used for mounting a high-speed external device.

The invention provides a system on a chip, which comprises an MCU kernel, an FPGA kernel and a system bus; the system bus is connected with the FPGA kernel and the MCU kernel and used for realizing interaction between the MCU kernel and the FPGA kernel; the FPGA kernel comprises an ADC analog-to-digital conversion unit connected with the system bus, and the ADC analog-to-digital conversion unit is used for receiving an analog signal provided by external equipment, converting the analog signal into a first digital signal and sending the first digital signal to the MCU kernel through the system bus. The system on chip provided by the invention has an analog-to-digital conversion function, can reduce the complexity of chip design, shortens the product development period and reduces the product development cost.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.

FIG. 1 is a block diagram of a system on a chip according to an embodiment of the invention;

FIG. 2 is a block diagram of a system on a chip according to an embodiment of the invention;

FIG. 3 is a block diagram of a system on a chip according to an embodiment of the invention;

fig. 4 is a schematic structural diagram of an APB expansion interface and an ADC controller in a system on chip according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in fig. 1, the present invention provides a system on a chip, which includes an MCU core 10, an FPGA core 20, and a system bus 101; in this embodiment, the MCU core 10 refers to a microcontroller unit connected to the FPGA core 20 within a chip of the system on chip 1. The microcontroller unit, i.e. the single chip, has a good data processing capacity. The FPGA core 20 refers to a field programmable gate array that is connected on-chip with the MCU core 1010. An FPGA (Field-Programmable Gate Array) is a product of further development based on Programmable devices such as PAL (Programmable Array Logic), GAL (general Array Logic), CPLD (Complex Programmable Logic Device), and belongs to a semi-custom circuit.

The system bus 101 is connected with the FPGA core 20 and the MCU core 10, and is used for realizing interaction between the MCU core 10 and the FPGA core 20; the system bus 101 is an information channel to which the FPGA core 20 and the MCU core 10 are connected. The system bus 101 may enable data interaction between the MCU core 10 and the FPGA core 20. The information transferred over system bus 101 may include data information, address information, and control information.

The FPGA core 20 includes an ADC analog-to-digital conversion unit 201 connected to the system bus 101, where the ADC analog-to-digital conversion unit 201 is configured to receive an analog signal provided by an external device, convert the analog signal into a first digital signal, and send the first digital signal to the MCU core 10 through the system bus 101. That is, the MCU core 10 may receive and process the first digital signal provided by the ADC analog-to-digital conversion unit 201. In the ADC analog-to-digital conversion unit 201, a dedicated interface may be provided to receive an externally input analog signal, then a circuit inside the ADC analog-to-digital conversion unit 201 converts the analog signal into a corresponding first digital signal, and finally sends the first digital signal to the MCU core 10, and the MCU core 10 further processes the first digital signal.

Preferably, the ADC analog-to-digital conversion unit 201 may further connect an external ADC hard core outside the chip, where the external ADC hard core may convert an analog signal into a second digital signal and then transmit the second digital signal to the ADC analog-to-digital conversion unit 201, and at this time, the ADC analog-to-digital conversion unit 201 may send the second digital signal received from the external ADC hard core to the MCU core through the system bus.

In the above embodiment of the present invention, since the ADC analog-to-digital conversion unit 201 is embedded in the system on chip 1, when the system on chip 1 is used, it is not necessary to specially adapt the corresponding analog-to-digital conversion unit for analog-to-digital conversion, but the ADC analog-to-digital conversion unit 201 inside the system on chip 1 directly receives an analog signal provided by an external device, converts the analog signal into a first digital signal, and then sends the first digital signal to the MCU core 10 through the system bus 101 for processing the first digital signal.

In an embodiment, as shown in fig. 2, the system bus 101 is disposed in the MCU core 10, and the MCU core 10 includes a core circuit 102 connected to the system bus 101; the system bus 101 is used for realizing the interaction between the core circuit 102 and the FPGA core 20;

the ADC analog-to-digital conversion unit 201 converts an analog signal provided by an external device into a first digital signal, and then sends the first digital signal to the core circuit 102 through the system bus 101.

In this embodiment, a system bus 101 is disposed in the MCU core 10, and the system bus 101 is an information channel for connecting the core circuit 102 in the MCU core 10 to other devices. Here, the core circuit 102 may include a data processing module and a logic control module. The core circuit 102 disposed in the MCU core 10 may receive and process the first digital signal provided by the ADC analog-to-digital conversion unit 201. The circuit inside the ADC analog-to-digital conversion unit 201 converts the analog signal into a corresponding first digital signal, and finally sends the first digital signal to the core circuit 102, and the core circuit 102 further processes the first digital signal.

In one embodiment, as shown in fig. 3, the ADC analog-to-digital conversion unit 201 includes an APB extension interface 2011, an ADC interface 2013 and an ADC controller 2012, and the system bus 101 includes an APB bus. Here, the APB Bus is an abbreviation of advanced peripheral Bus, and chinese is a peripheral Bus. The APB bus may be used for connection between peripheral peripherals with low bandwidth, and here, is used for connecting the APB extension interface 2011 and the MCU core 10, so as to implement data interaction between the ADC analog-to-digital conversion unit 201 and the MCU core 10.

Specifically, the ADC interface 2013 is connected to the ADC controller 2012, and is configured to output an analog signal acquired from an external device to the ADC controller 2012. The ADC interface 2013 is a connection port between the ADC analog-to-digital conversion unit 201 and an external industrial device.

The ADC controller 2012 is connected to the APB extension interface 2011, and is configured to convert the analog signal received from the ADC interface 2013 into a first digital signal and output the first digital signal to the APB extension interface 2011. The ADC controller 2012 may be implemented by FPGA logic resources. Because the FPGA has the programmable characteristic, the application capability of the system on chip 1 can be improved by upgrading the FPGA on a software level. In other words, the system on chip 1 provided by this embodiment has a very strong adaptability to other industrial devices, and can adapt corresponding driving codes to the system on chip 1 according to the characteristics of the industrial devices. The APB extension interface 2011 is connected to the APB bus, and is configured to output the first digital signal received from the ADC controller 2012 to the MCU core 10 through the APB bus.

The ADC interface 2013 is connectable to an external device, receives an analog signal provided from the external device, and transmits the analog signal to the ADC controller 2012 connected thereto. The APB extension interface 2011 includes a plurality of pins, which are: clock signals, reset signals, address signals, write enable, write data bus, bus strobe, bus enable, end flag bit, read data bus.

In one embodiment, as shown in fig. 4, the ADC controller 2012 includes:

the APB slave device manager 20121 is connected to an external APB host through the APB interface, and is configured to implement interaction between the MCU core 10 and the external APB host. In this embodiment, the APB slave device manager 20121 is connected to the external APB host through the APB interface, thereby implementing interaction between the MCU core 10 and the external APB host. Herein, the external APB host includes, but is not limited to, an industrial motor, an industrial detector.

And the ADC analog-to-digital conversion control circuit 20122 is connected with the ADC interface 2013 and is used for converting the model signal into a first digital signal according to preset configuration information. The ADC analog-to-digital conversion control circuit 20122 is connected to the APB slave device manager 20121, acquires an analog signal from the APB slave device manager 20121, and converts the analog signal into a first digital signal according to preset configuration information. Because the ADC analog-to-digital conversion control circuit 20122 is realized by relying on FPGA resources and has the characteristic of being modifiable, under a certain condition, the adaptive capacity of the system on chip 1 for analog signals can be improved by modifying preset configuration information in the ADC analog-to-digital conversion control circuit 20122.

In one embodiment, as shown in fig. 3, the FPGA core 20 includes a clock unit 202 and a reset unit 203; the clock unit 202 is connected with the MCU core 10 and configured to provide a time signal; the MCU core 10 and the FPGA core 20 share the time signal provided by the clock unit 202. Here, the clock unit 202 may be a timing device implemented using FPGA logic resources, and may provide a time signal to the MCU core 10 and the FPGA core 20. Herein, clock unit 202 may refer to an FPGA core 20 time system.

The reset unit 203 is connected with the MCU core 10 and configured to provide a reset signal; the MCU core 10 and the FPGA core 20 share the reset signal provided by the reset unit 203. The reset unit 203 may be a reset device implemented using FPGA logic resources, and may provide a reset signal to the MCU core 10 and the FPGA core 20. Herein, the reset unit 203 may refer to a global reset system of the FPGA core 20.

In this embodiment, the clock unit 202 and the reset unit 203 are disposed in the FPGA core 20, so that the time signal and the reset signal are generated from the FPGA core 20 to be shared by the FPGA core 20, the MCU core 10, and an external device connected to the FPGA core.

In one embodiment, as shown in FIG. 3, the system on chip 1 includes an on chip memory 30, and the system bus 101 includes an AHB bus. In this embodiment, the system on chip 1 may be provided with an on chip memory 30. The on-chip memory 30 may include read only memory and random access memory. Read-Only Memory (often abbreviated ROM). The data stored in the rom is usually written into the memory in advance, and can only be read out during operation, but not be quickly and conveniently rewritten as in the case of the ram. But the data stored in the read-only memory is stable, and the stored data can not be changed after power failure; the structure is simple, and the reading is convenient. A Random Access Memory (RAM), also called a main Memory, which is an internal Memory capable of directly exchanging data with the MCU core 10. Random access memory (ram) can be read and written at any time (except when it is refreshed) and is fast and often used as a temporary data storage medium for operating systems or other programs that are running. The random access memory can write (store) or read (fetch) information from any one of the designated addresses at any time when operating. In the present embodiment, the on-chip memory 30 includes a read only memory and a random access memory.

The read-only memory is connected with the MCU kernel 10 through the AHB bus and is used for realizing interaction and reading operation with the MCU kernel 10; the random access memory is connected with the MCU core 10 through the AHB bus, and is configured to implement interaction with the MCU core 10, as well as read, write, and erase operations.

Here, the system Bus 101 includes an AHB Bus (an abbreviation of Advanced High Performance Bus, chinese Advanced High Performance Bus). The AHB bus includes some of the following characteristics: single clock edge operation; non-tri-state implementations; supporting burst transmission; supporting segmented transmission; supporting a plurality of master controllers; the width of a 32-128 bit bus can be configured; byte, halfword, and word transfers are supported. Here, the rom and the ram are connected to the MCU core 10 through the AHB bus, so as to implement the above-described operations such as reading and writing to the MCU core 10.

In some cases, the FPGA core 20 is also connected to on-chip memory 30. The on-chip memory 30 may be common to the MCU core 10 and the FPGA core 20, but at the same time the on-chip memory 30 may only be used for one of the cores. When the on-chip memory 30 is in the MCU enabling mode, the on-chip memory 30 is connected to the MCU core 10, and the on-chip memory 30 may store data and instructions of the MCU core 10. When the on-chip memory 30 is in the FPGA enabled mode, the on-chip memory 30 is connected to the FPGA core 20, and the on-chip memory 30 may store data and instructions of the FPGA core 20.

In one embodiment, as shown in fig. 3, the MCU core 10 includes a general purpose input/output interface 103, and the system bus 101 includes an AHB bus connected to the general purpose input/output interface 103; the general input/output interface 103 is connected to the FPGA core 20, and is configured to implement interaction between the MCU core 10 and the FPGA core 20. In this embodiment, the MCU core 10 includes a general purpose input/output interface 103 (i.e., GPIO interface). The general input/output interface 103 has low power loss and low cost. The general input/output interface 103 is an important interface for connecting the MCU core 10 to the FPGA core 20, and can realize data interaction between the MCU core 10 and the FPGA core 20.

In one embodiment, as shown in fig. 3, the MCU core 10 includes a universal asynchronous transfer interface 104, and the system bus 101 includes an APB bus connected to the universal asynchronous transfer interface 104; the universal asynchronous transmission interface 104 is connected to the FPGA core 20, and is configured to implement interaction between the MCU core 10 and the FPGA core 20. In this embodiment, the MCU core 10 includes a universal asynchronous transfer interface 104 (i.e., a UART interface). The UART 104 may convert data to be transmitted between serial and parallel communication, and may be used for asynchronous communication. The universal asynchronous transfer interface 104 is an important interface for connecting the MCU core 10 to the FPGA core 20, and can implement data interaction between the MCU core 10 and the FPGA core 20.

In one embodiment, the system bus 101 includes an APB bus for mounting a low-speed peripheral and an AHB bus for mounting a high-speed peripheral. In this embodiment, the system bus 101 may include an APB bus and an AHB bus. Specifically, the APB bus is used to mount a low-speed external device. The characteristics of the APB bus include: two clock cycles transmission; no waiting period and no response signal are needed; the control logic is simple and only has four control signals. The AHB bus is used to mount a high-speed external device, and is an important channel for connecting the MCU core 10 and the high-speed external device.

It will be appreciated by those of ordinary skill in the art that any reference to memory, storage, databases, or other media used in the embodiments provided herein can include non-volatile and/or volatile memory. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.

Claims

1. A system on a chip is characterized by comprising an MCU kernel, an FPGA kernel and a system bus;

2. The system on a chip of claim 1, wherein the ADC analog-to-digital conversion unit includes an APB expansion interface, an ADC interface, and an ADC controller, the system bus includes an APB bus;

3. The system-on-chip of claim 2, wherein the ADC controller comprises:

4. The system on a chip of claim 1, wherein the system bus is disposed in the MCU core, the MCU core including a core circuit connected to the system bus; the system bus is used for realizing the interaction between the kernel circuit and the FPGA kernel;

5. The system on a chip of claim 1, wherein the FPGA core comprises a clock unit and a reset unit;

6. The system on chip of claim 1, wherein the system on chip comprises an on chip memory, the system bus comprising an AHB bus; the on-chip memory comprises a read-only memory and a random access memory;

7. The system on a chip of claim 1, wherein the MCU core includes a general purpose input output interface, the system bus comprising an AHB bus connected with the general purpose input output interface;

8. The system on a chip of claim 1, wherein the MCU core includes a universal asynchronous transfer interface, the system bus comprising an APB bus connected to the universal asynchronous transfer interface;

9. The system on a chip of claim 1, wherein the system bus comprises an APB bus to mount a low speed peripheral and an AHB bus to mount a high speed peripheral.