CN111143259B

CN111143259B - Multi-line SPI flash controller

Info

Publication number: CN111143259B
Application number: CN201911405914.5A
Authority: CN
Inventors: 卢鼎; 雷海燕; 宋存杰
Original assignee: Datang Semiconductor Technology Co ltd
Current assignee: Datang Semiconductor Technology Co ltd
Priority date: 2019-12-31
Filing date: 2019-12-31
Publication date: 2021-09-17
Anticipated expiration: 2039-12-31
Also published as: CN111143259A

Abstract

The invention discloses a multi-line SPI flash controller, which comprises a bus interface module, a register file, a data buffer module, a state machine, an input/output control module, a Fill _ req interface and an RAM interface. The controller directly combines the flash command, the bus mode, the input length and the output length into the command, removes a decoding part, completely isolates multi-line control and command coding, has simple and clear structure, occupies less hardware resources and is convenient to realize; each transmission instruction is realized through software programming, so that the flexibility is high, and the expansibility is good; and various control/read-write instructions are realized by software, the access of flash chips of multiple manufacturers can be realized, and the compatibility is higher.

Description

Multi-line SPI flash controller

Technical Field

The invention relates to the technical field of SPI flash controllers, in particular to a multi-line SPI flash controller.

Background

At present, with the expansion of the external storage requirements of the internet of things and an embedded chip, an external multi-line SPI flash becomes a low-cost, high-speed and large-capacity implementation scheme. The chip can extend the storage to 4Mbit or more by externally connecting a special multi-line SPI flash chip. Compared with the built-in EFlash, the method is low in cost and can acquire enough storage resources. A plurality of Flash chip manufacturers define abundant interface instructions and transmission types, how to ensure the high performance and compatibility of the designed multi-line SPI Flash controller and become the problem to be solved urgently in the design of the multi-line SPI Flash controller.

The traditional SPI flash controller encodes commands of a plurality of multi-line SPI flash, then defines decoding logic, and the decoding logic transmits commands and performs read-write operation according to the mode (single-wire/double-wire/four-wire) and command encoding of the current SPI flash. The traditional multi-line SPI flash controller is implemented as shown in fig. 1, and as can be seen from fig. 1, the structure of a typical multi-line SPI flash controller includes the following parts:

a bus interface module: is responsible for interacting with a processor or a bus;

register file: defining a programming interface of the controller, and defining a plurality of registers including a command register, a state register, an address register, a mode register and the like;

data buffer: the buffer is responsible for reading and writing data;

a decoding section: responsible for the decoding of the order;

a state machine; the controller is responsible for state control of the whole controller;

the input and output control and serial-parallel conversion control module: and the device is responsible for interacting with an external multi-line SPI flash chip.

The working flow of the traditional multi-line SPI controller is as follows:

the method comprises the following steps that 1, a CPU configures commands, sets modes and addresses to a register file through a bus interface module, writes data to be written into a data Buffer (during writing commands), and finally enables transmission;

2. the decoding component reads a command register in the register file, drives a control state machine and starts to assemble a data packet according to a command format;

3. after the data packet is assembled, the data packet is sent to an input/output control and serial-parallel conversion control module and is converted into a format supported by an external multi-line SPI flash to realize a read-write command;

4. after the state machine judges that the reading and writing are finished, sending an interrupt to the bus interface module, and finally sending the interrupt to the CPU;

5. if the data read is performed, the read data can be acquired from the data Buffer, and if the data write is performed, the write is completed.

Traditional multi-thread SPI flash structure is clear, and the function is clear, however, has several great problems:

1. the flexibility is not enough: the fixed command codes determine that the implementation can only analyze and support the fixed multi-line SPI flash command, the newly added command needs to modify the design for expansion, the hardware responsibility is increased along with the increase of the commands, and frequent modification brings more risks;

2. compatibility risk: many multi-line SPI Flash manufacturers exist, commands supported by each Flash are different, and if the commands are not considered comprehensively during definition, the compatibility problem is easily caused;

3. the complexity is high: the multi-line SPI flash needs to be compatible with chips with multiple modes of single lines, double lines and four lines, the serial-parallel conversion component needs to perform different serial-parallel conversion according to different commands, the responsibility is high, and errors are easy to occur.

Therefore, how to provide an SPI flash controller with a simple structure, more flexibility and high compatibility is a problem that needs to be solved urgently by those skilled in the art.

Disclosure of Invention

In view of this, the present invention provides a multi-line SPI flash controller, which defines a flexible encoding scheme, directly combines a flash command, a bus mode, an input length, and an output length into a command, removes a decoding part, completely isolates multi-line control and command encoding, and achieves maximum flexibility. Meanwhile, various multi-line SPI flash instructions can be supported through software configuration, and the expansibility and the compatibility are optimal.

In order to achieve the purpose, the invention adopts the following technical scheme:

the invention provides a multi-line SPI flash controller, comprising:

a bus interface module that interacts with a processor or bus;

the register file directly combines a bus mode, whether the bus mode comprises an address ADDR _ INC, the number of input bytes, the number of output bytes, an operation code and sending enabling into a single command to be respectively transmitted;

the data buffer module buffers read-write data;

the state machine controls the data receiving and sending and sends codes according to a preset sequence;

the input and output control module interacts with an external multi-line SPI flash chip and controls the direction of a three-state port of a pin of the multi-line SPI flash chip according to the state of the state machine;

the Fill _ req interface is used for performing Fill _ req handshake and response with an external Cache controller;

and the RAM interface is used for exchanging and transmitting data between the data buffer module and an external RAM memory.

Further, the register file includes a command register and an address register;

the command register directly combines the bus mode, whether the address ADDR _ INC is included, the input byte number, the output byte number, the operation code and the sending enable into a single command;

the address register stores in real time address information of the memory location accessed by the current processor.

Furthermore, the Fill _ req interface directly responds to a data exchange request of the Cache controller without participation of a CPU (central processing unit);

the Fill _ req interface initiates a Fill _ req request command according to a defined time sequence by a Cache controller, wherein the request command comprises:

4) carrying source address Fill _ SADDR

5) Transport destination Address FILL _ DADDR

6) Conveying direction FILL _ DIR

The state machine responds to the Fill _ req request and realizes the exchange of data in the multi-line SPI Flash chip and data in the RAM memory;

and the state machine responds to a hardware request of the Cache controller through a Fill _ ack signal of the Fill _ req interface and informs the Cache controller of finishing data transportation.

According to the technical scheme, compared with the prior art, the controller directly combines the flash command, the bus mode, the input length and the output length into the command, removes a decoding component, completely isolates the multi-line control and the command coding, has a simple and clear structure, occupies less hardware resources, and is convenient to realize; the software programming realizes each transmission instruction, and the flexibility is high and the expansibility is good; the software realizes various control/read-write instructions, can realize the access of flash chips of a plurality of manufacturers, and has higher compatibility.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a diagram illustrating a structure of a conventional multi-line SPI flash controller;

FIG. 2 is a schematic diagram of an improved multi-line SPI flash controller according to the present invention;

FIG. 3 is a schematic diagram illustrating a position of a multi-line SPI Flash controller in a Soc system according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating a defined state of a Fill _ req interface according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a data transmission control flow of the multi-line SPI flash controller state machine in the embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 2, an embodiment of the present invention discloses a multi-line SPI flash controller, including:

the bus interface module 1 is used for interacting with a processor or a bus;

a register file 2, wherein the register file 2 directly combines a BUS MODE (BUS _ MODE), whether an address ADDR _ INC is included, an input byte number (IN _ LEN), an output byte number (OUT _ LEN), an operation code (OPCODE) and a sending enable (ST) into a single command to be respectively transmitted;

the data buffer module 3 buffers read-write data;

the state machine 4 controls the data to be transmitted and received, the data is not limited by operation codes (opcodes) to be transmitted and received, and the codes are transmitted according to a preset sequence;

the input and output control module 5 is used for interacting with an external multi-line SPI flash chip and controlling the direction of a three-state port of a pin of the multi-line SPI flash chip according to the state of the state machine 4;

the Fill _ req interface 6 is used for performing Fill _ req handshake and response with an external Cache controller;

and the RAM interface 7 is used for exchanging and transmitting data between the data buffer module 3 and an external RAM memory.

In particular, a tri-state port is a feature of a chip pin, that is, the pin may be input-output directional.

Specifically, fig. 3 shows the position of the multi-line SPI Flash controller disclosed in this embodiment in the Soc system. As can be seen from fig. 3:

the multi-line SPI Flash controller mainly comprises four external interfaces which are respectively as follows:

1) a Slave bus interface interconnected with the bus;

2) a multi-line SPI Flash interface interconnected with an external Flash chip;

3) a Fill _ req interface interconnected with the Cache controller;

4) a RAM interface interconnected with the RAM memory.

The Slave bus interface provides conventional multi-line Flash control and read-write operation, the multi-line SPI Flash interface provides external Flash chip interconnection, the Fill _ req interface is a special interface for the Cache controller to request data from the multi-line SPI controller in the embodiment, and the RAM interface is a target memory interface for the controller to carry data.

Specifically, in a system including a Cache, the multi-line SPI controller assumes the task of swapping in and out channels for data. The controller disclosed in this embodiment needs to automatically send out a multi-line flash read-write operation under the condition of a Fill _ req request, and move data in and out of the RAM memory according to a format.

The definition of the Fill _ req interface is shown in fig. 4. The main device of the Fill _ req interface is a cache controller, and the slave device is a multi-line Flash controller. When the cache controller needs data exchange, a data exchange request is initiated through the interface:

1. the switch source address FILL _ SADDR, the switch destination address FILL _ DADDR, the switch direction FILL _ DIR (high/low) are driven to the interface, noting that: the FILL _ DIR is low to convey the data of the Flash chip to the RAM, and is high to convey the data of the RAM to the Flash chip;

2. meanwhile, the FILL _ REQ is pulled up for 1 period, and the data carrying process of the multi-line SPI Flash is started;

3. after the designated transport is finished by the multi-line SPI Flash, pulling up FILL _ ACK to represent that the data exchange is finished;

in this embodiment, the Fill _ req interface is a completely hardware interface, and the CPU is not required to participate in the process of exchanging the request and the data. And the Cache controller directly drives the multi-line SPI Flash controller to exchange data. Flash read-write commands, formats and the like adopted by the multi-line SPI Flash controller are internally configured by a special register.

Specifically, the Fill _ req interface initiates a Fill _ req request command according to a defined time sequence by the Cache controller, and the request command includes:

1) carrying source address Fill _ SADDR

2) Transport destination Address FILL _ DADDR

3) Conveying direction FILL _ DIR

and the state machine responds to the hardware request of the Cache controller through a Fill _ ack signal of the Fill _ req interface and informs the Cache controller of finishing data transportation.

In a specific embodiment, the register file 2 comprises a command register 21 and an address register 22;

the command register 21 directly combines the bus mode, whether the address ADDR _ INC is included, the input byte number, the output byte number, the operation code, and the transmission enable into a single command instruction;

the address register 22 holds in real time the address information of the memory location accessed by the current processor.

In this embodiment, the command register 21 can directly combine the bus mode, whether the address ADDR _ INC is included, the input byte number, the output byte number, the operation code, and the issue enable into a single command instruction, and the single command access procedure has the following advantages:

1. the registers of the SPI controller are organized into a single command (the total length is controlled within 32 bits), the transmission operation can be triggered by writing the registers once, and the registers of other controllers are organized into a plurality of registers, so that the operation is started by configuring a plurality of registers, and the efficiency is low;

2. because the command is simple, the software interface design (conventional mode) and the hardware interface design (Cache scene) can be conveniently and simultaneously carried out, and the two interfaces can be internally unified;

3. the software application angle can trigger operation by single command access, the internal register file can be combined into an FIFO type and a linked list type, the commands can be cumulatively filled by multiple operations, the efficiency is high, and the operation is continuous.

In this embodiment, referring to fig. 5, the sequence in which the state machine 4 transmits the codes includes:

1) transmit operation code (OPCODE);

2) if the address ADDR _ INC is 1, the address is sent, otherwise, skipping;

3) if the output byte number OUT _ LEN is larger than 1, starting to send the bytes in the data cache module, and sending the output byte number minus 1(OUT _ LEN-1) bytes;

4) if the input byte number IN _ LEN is larger than 0, starting to receive byte data of the input byte number IN _ LEN into the data cache module;

5) and recovering to the idle state after the execution is finished.

The multi-line SPI flash controller disclosed by the embodiment defines a flexible coding scheme, directly combines a flash command, a bus mode, an input length and an output length into an instruction, removes a decoding part, completely isolates multi-line control and instruction coding, and achieves the maximum flexibility. Various multi-line SPI flash instructions can be supported through software configuration, and the expansibility and the compatibility are optimal. In this embodiment, the data transmission process of the multi-line SPI flash controller disclosed in the embodiments of the present invention is as follows:

dividing the multi-line SPI flash controller into a code segment, an address segment, a dummy field, a sending data segment and a receiving data segment, and respectively transmitting data;

directly taking the operation code field, the address field and the dummy field as common data for transmission;

and controlling the sent byte number and the received byte number respectively through corresponding instructions, and directly entering the next stage after receiving and sending the specified byte number.

The "next stage" referred to in this embodiment can be understood as follows: in this embodiment, the flash access is sequentially divided into: the sending code segment, the address segment, the dummy field, the sending data segment and the receiving data segment have five stages. The next stage refers to the next stage in which the code is increased by 1. If the data segment is currently being received, the transmission ends.

The encoding method of the instructions in the above embodiment is described below by taking a common multi-line SPI flash command as an example, as follows:

1. single byte command WRSR (06H):

and (3) encoding: BUS _ MODE is 0; ADDR _ INC ═ 0; IN _ LEN ═ 0; OUT _ LEN ═ 1; OPCODE ═ 0x06 transmits commands:

OPCODE[7:0]

2. read status register command RDSR (05H):

BUS_MODE＝0；ADDR_INC＝0；IN_LEN＝1；OUT_LEN＝1；OPCODE＝0x05

and (3) transmitting a command:

OPCODE[7:0]

Data[7:0]

3. READ data instruction READ (03H):

BUS _ MODE is 0; ADDR _ INC ═ 1; IN _ LEN ═ N (number of bytes that need to be read); OUT _ LEN ═ 4; OPCODE-0x03

And (3) transmitting a command:

OPCODE[7:0]

ADDR[23:0]

Data[(8N-1):0)

4. two-wire Read data instruction Fast Read (3 BH):

BUS _ MODE is 1; ADDR _ INC ═ 1; IN _ LEN ═ N (number of bytes that need to be read); OUT _ LEN ═ 5; OPCODE-0x3B

And (3) transmitting a command:

OPCODE[7:0]

ADDR[23:0]

Dummy[7:0]

Data[(8N-1):0](two-wire transmission)

5. Four-wire program QPP instruction (32H):

BUS _ MODE-2; ADDR _ INC ═ 1; IN _ LEN ═ 0; OUT _ LEN ═ 4+ N (number of bytes needed to write) transfer command:

OPCODE[7:0]

ADDR[23:0]

Data[(8N-1):0](four-wire transmission)

In summary, compared with the prior art, the multi-line SPI flash controller disclosed in the embodiments of the present invention has the following advantages:

1. the controller directly combines the flash command, the bus mode, the input length and the output length into the command, removes a decoding part, completely isolates multi-line control and command coding, has simple and clear structure, occupies less hardware resources and is convenient to realize;

2. the software programming realizes each transmission instruction, and the flexibility is high and the expansibility is good;

3. the CPU sends a single command to start the operation of the multi-line SPI flash chip once, so that the operation is more efficient;

4. the software realizes various control/read-write instructions, can realize the access of flash chips of a plurality of manufacturers, and has higher compatibility.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multi-wire SPI flash controller, comprising:

a bus interface module that interacts with a processor or bus;

the data buffer module buffers read-write data;

the RAM interface is used for data exchange and transmission between the data buffer module and an external RAM memory;

the Fill _ req interface directly responds to a data exchange request of the Cache controller without participation of a CPU (central processing unit);

1) carrying source address Fill _ SADDR

2) Transport destination Address FILL _ DADDR

3) Conveying direction FILL _ DIR

2. The multi-line SPI flash controller according to claim 1, wherein said register file comprises a command register and an address register;

the command register directly combines a bus mode, whether the bus mode comprises an address ADDR _ INC, an input byte number, an output byte number, an operation code and sending enable into a single command, the command length is less than or equal to 32 bits, and transmission can be initiated by writing the single register;