CN109522251A - A kind of high-speed synchronous serial port board and its working method based on PXIe bus - Google Patents
A kind of high-speed synchronous serial port board and its working method based on PXIe bus Download PDFInfo
- Publication number
- CN109522251A CN109522251A CN201811138490.6A CN201811138490A CN109522251A CN 109522251 A CN109522251 A CN 109522251A CN 201811138490 A CN201811138490 A CN 201811138490A CN 109522251 A CN109522251 A CN 109522251A
- Authority
- CN
- China
- Prior art keywords
- data
- unit
- gate array
- synchronous serial
- serial port
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
Abstract
A kind of high-speed synchronous serial port board based on PXIe bus, including FPGA gate array unit, DDR memory grain unit and serial ports transceiving chip unit；Its working method is to initialize, wait task status, corresponding data judgement is executed according to task status, reads data and data write-in；Realize the data write-in and synchronous serial interface output of DDR in board；The reception of synchronous serial interface data is realized, the data in DDR can be read after deposit DDR by PXIe bus；Realize the interaction of High Speed Serial Yu PXIe bus data.
Description
Technical field
The present invention relates to the technical fields of communication protocol converter, specifically a kind of to be based on PXIe(PCI express
Extensions for Instrumentation serial computer expansion bus) bus high-speed synchronous serial port board and its work
Method.
Background technique
PXIe is based on being Compact PCI standard, increases clock and synchronous Trigger Bus on its basis.PXIe is every
One equipment provides individual transmission channel, at the same it increased clock and synchronous triggering signal and possess special interface
Physical characteristic makes it possess bigger technical advantage in fields such as measurement, communication, industrial automations.PXIe is with respect to PXI(PCI
Express extensions for Instrumentation, the PCI extension towards instrument system) most significant improvement and excellent
Gesture is that the characteristics of it incorporates PCI Express, using serial transmission, the bus topolopy of point-to-point.PCI Express
Technology is desirably integrated into backboard, while maintaining and having the backwards compatibility that basic existing system is widely applied.In addition to x1,
Outside x4 and x8 link, system controller slot also supports the PCI Express link of up to x16, can provide for PXIe backboard
The bandwidth of highest 6GB/s.Using PCI Express technology, PXIe improves the available bandwidth in PXI more than 45 times, i.e., from
132MB/s is increased to 6GB/s；At the same time, it can also maintain and the software of PXI intermodule, hardware compatibility.
Synchronous data-link controls SDLC(Synchronous Data Link Control) agreement is a kind of IBM Corporation
The data link layer protocol of proposition is suitable for System Network Architecture.The synchronization RS-422 bus for executing SDLC agreement uses
Full duplex transmission mode realizes the communication of equipment between bus, and this communication modes were once once used in U.S.A. military affairs equipment,
China had also been developed to later, and had been widely applied in the military model task and test equipment of early stage.
Nowadays as the integration of system is higher and higher, system internally and externally needs interactive data volume increasing, with
Data throughput toward buses such as ISA, the PCI being commonly used has been unable to meet current system use.For current
High-speed synchronous serial port board, the board external communication bus rate limit communication speed of synchronous serial interface, however, PXIe conduct
The serial high-speed bus agreement for comparing mainstream at present, may be implemented the transmission of big data quantity, and high-speed synchronous serial ports is used in combination, can
To complete the demand of system high-speed data communication.
Summary of the invention
The purpose of the present invention is to provide a kind of high-speed synchronous serial port boards and its working method based on PXIe bus, it can
It is that a kind of structure is simple, the structure and method that are easily achieved with overcome the deficiencies in the prior art.
A kind of technical solution of the present invention: high-speed synchronous serial port board based on PXIe bus, it is characterised in that it includes
FPGA(Field-Programmable Gate Array, field programmable gate array) gate array unit, DDR(Double
Data Rate SDRAM, Double Data Rate synchronous DRAM) memory grain unit and serial ports transceiving chip unit；Institute
It states and is successively connected in bi-directional data between serial ports transceiving chip unit, FPGA gate array unit and DDR memory grain unit.
The FPGA gate array unit uses the XC7K325TFFG676 chip of Xilinx company production；It is described
XC7K325TFFG676 chip has common I/O interface and Memory control interface；The common I/O interface is for connecting FPGA gate array
Column unit and serial ports transceiving chip unit；The Memory control interface mounts for realizing outside FPGA gate array unit
DDR memory grain unit.
The XC7K325TFFG676 chip belt of the FPGA gate array unit be used for connect PXIe bus GTX interface and
Memory interface realizes number in data exchange and the DDR memory grain unit between FPGA gate array unit and PXIe bus
According to read-write；The GTX interface is PCIe interface.
The DDR memory grain unit uses the MT41K128M16JT-125IT chip of MICRON company；It is FPGA described
The MIG IP kernel of array element can be used as the memory I P core with DDR memory grain unit, for realizing the read-write control of DDR data
System and storage.
The serial ports transceiving chip unit uses the RS-422 electrical level transferring chip LTM2881 of ADI company, is a electric current
RS485/RS422 μM of odule transceiver of isolated form full duplex.
The serial ports transceiving chip unit is made of two electrical level transferring chip LTM2881；Each electrical level transferring chip
LTM2881 is in be bi-directionally connected with the common I/O interface in FPGA gate array unit.
A kind of working method of the high-speed synchronous serial port board based on PXIe bus, it is characterised in that it the following steps are included:
(1) the high-speed synchronous serial port board (hereinafter referred to as serial port board) based on PXIe bus is started to work, and after completing initialization, is entered
Task status is waited, if task is " FPGA gate array unit detects and reads synchronous serial interface signal ", operating procedure (2)-
(5)；When task is " PXIe bus read data ", then operating procedure (6)；When task is " it is required that PXIe bus control data
When output ", then operating procedure (7)；
(2) serial ports RS422 level signal is switched to Transistor-Transistor Logic level signal by serial ports transceiving chip unit, is introduced into FPGA gate array
In the common I/O port of the XC7K325TFFG676 chip of column unit, when FPGA gate array unit has detected that synchronous serial interface signal connects
Enter, and the task of serial port board is that this serial data is passed through FPGA gate array unit when reading synchronous serial interface signal at this time
The SDLC protocol procedure of internal composition is parsed, if data fit SDLC agreement, for valid data；
(3) effective rs 232 serial interface signal data are saved in DDR memory grain unit by FPGA gate array unit；
It (4), will be by the SDLC protocol procedure pair of FPGA gate array unit when serial port board receives external " sending data " instruction
The processing of synchronizing of data, and by treated, data are sent to synchronous serial interface, complete the work of serial port board；
(5) when serial port board is not received by external " sending data " instruction, then continue to access external equipment, until receiving
" sending data " instruction, repeats step (4)；
(6) when PXIe bus needs to be read out serial data, whether basis " receives PCIe number of buses to serial port board at this time
According to request ", it is operated；When a request is received, FPGA gate array unit will read from DDR memory grain unit and store
Data, and be transmitted in PXIe bus, complete the work of serial port board；
(7) PXIe bus signals are connected using the PCIe interface of FPGA gate array unit XC7K325TFFG676；When PXIe bus
When needing that synchrodata is written, at this point, DDR memory is written in the data that FPGA gate array unit inputs PCIe interface
Grain unit, while serial port board wants real time scan " whether receiving the external command for sending data ", if so, by FPGA gate array
The SDLC protocol procedure of unit handles the synchronizing of data that PCIe interface inputs, and is sent to synchronous serial interface, completes string
The work of mouth card；The same step of implementation procedure (4) and (5).
It is of the invention to be advantageous in that: to can be realized and DDR in board is write data by PXIe bus, and will be in DDR
Data exported by the synchronous serial interface of 4Mbps, while realizing the reception of synchronous serial interface data, PXIe can be passed through after being stored in DDR
Bus reads the data in DDR, to realize the interaction of High Speed Serial Yu PXIe bus data.
Detailed description of the invention
Fig. 1 is a kind of overall structure schematic block diagram of the high-speed synchronous serial port board based on PXIe bus involved by the present invention.
Fig. 2 is a kind of use gate array GTX interface company of the high-speed synchronous serial port board based on PXIe bus involved by the present invention
Connect the circuit theory schematic diagram of PCIe x4 bus.
Fig. 3 is a kind of flow diagram of the high-speed synchronous serial port board working method based on PXIe bus involved by the present invention.
Specific embodiment
Embodiment: a kind of high-speed synchronous serial port board based on PXIe bus, as shown in Figure 1, it is characterised in that it includes
FPGA gate array unit, DDR memory grain unit and serial ports transceiving chip unit；The serial ports transceiving chip unit, FPGA
It is successively connected in bi-directional data between array element and DDR memory grain unit.
The FPGA gate array unit uses the XC7K325TFFG676 chip of Xilinx company production；It is described
XC7K325TFFG676 chip has common I/O interface and Memory control interface；The common I/O interface is for connecting FPGA gate array
Column unit and serial ports transceiving chip unit；The Memory control interface mounts for realizing outside FPGA gate array unit
DDR memory grain unit.
The XC7K325TFFG676 chip belt of the FPGA gate array unit be used for connect PXIe bus GTX interface and
Memory interface realizes number in data exchange and the DDR memory grain unit between FPGA gate array unit and PXIe bus
According to read-write；The GTX interface is PCIe interface, as shown in Figure 2.
The DDR memory grain unit uses the MT41K128M16JT-125IT chip of MICRON company；It is FPGA described
The MIG IP kernel of array element can be used as the memory I P core with DDR memory grain unit, for realizing the read-write control of DDR data
System and storage.
The serial ports transceiving chip unit uses the RS-422 electrical level transferring chip LTM2881 of ADI company, is a electric current
RS485/RS422 μM of odule transceiver of isolated form full duplex.
The serial ports transceiving chip unit is made of two electrical level transferring chip LTM2881；Each electrical level transferring chip
LTM2881 is in be bi-directionally connected with the common I/O interface in FPGA gate array unit.
A kind of working method of the high-speed synchronous serial port board based on PXIe bus, as shown in Figure 3, it is characterised in that it includes
Following steps:
(1) the high-speed synchronous serial port board (hereinafter referred to as serial port board) based on PXIe bus is started to work, and after completing initialization, is entered
Task status is waited, if task is " FPGA gate array unit detects and reads synchronous serial interface signal ", operating procedure (2)-
(5)；When task is " PXIe bus read data ", then operating procedure (6)；When task is " it is required that PXIe bus control data
When output ", then operating procedure (7)；
(2) serial ports RS422 level signal is switched to Transistor-Transistor Logic level signal by serial ports transceiving chip unit, is introduced into FPGA gate array
In the common I/O port of the XC7K325TFFG676 chip of column unit, when FPGA gate array unit has detected that synchronous serial interface signal connects
Enter, and the task of serial port board is that this serial data is passed through FPGA gate array unit when reading synchronous serial interface signal at this time
The SDLC protocol procedure of internal composition is parsed, if data fit SDLC agreement, for valid data；
(3) effective rs 232 serial interface signal data are saved in DDR memory grain unit by FPGA gate array unit；
It (4), will be by the SDLC protocol procedure pair of FPGA gate array unit when serial port board receives external " sending data " instruction
The processing of synchronizing of data, and by treated, data are sent to synchronous serial interface, complete the work of serial port board；
(5) when serial port board is not received by external " sending data " instruction, then continue to access external equipment, until receiving
" sending data " instruction, repeats step (4)；
(6) when PXIe bus needs to be read out serial data, whether basis " receives PCIe number of buses to serial port board at this time
According to request ", it is operated；When a request is received, FPGA gate array unit will read from DDR memory grain unit and store
Data, and be transmitted in PXIe bus, complete the work of serial port board；
(7) PXIe bus signals are connected using the PCIe interface of FPGA gate array unit XC7K325TFFG676；When PXIe bus
When needing that synchrodata is written, at this point, DDR memory is written in the data that FPGA gate array unit inputs PCIe interface
Grain unit, while serial port board wants real time scan " whether receiving the external command for sending data ", if so, by FPGA gate array
The SDLC protocol procedure of unit handles the synchronizing of data that PCIe interface inputs, and is sent to synchronous serial interface, completes string
The work of mouth card；The same step of implementation procedure (4) and (5).
Below with reference to embodiment and its attached drawing, the present invention is described in more detail.
A kind of structural block diagram for high-speed synchronous serial port board based on PXIe bus that the present invention designs is as shown in Figure 1, equipment
It mainly include high-performance FPGA gate array unit, DDR memory grain unit and High Speed Serial transceiving chip unit.
FPGA gate array unit uses the XC7K325TFFG676 of Xilinx company production, this chip is that Xilinx company pushes away
It is a in Kintex-7 series out.Its performance is one times of Virtex-6, and power consumption but reduces half.The series is supported completely
2.0 standard of PCI Express, serial high speed input and output SRIO bus is provided by HDMI interface to be stablized, reliably passes at a high speed
Movement Capabilities provide great convenience for the rapid shaping of product.
DDR memory grain unit uses the MT41K128M16JT -125 IT chip of MICRON company.
Serial ports transceiving chip unit uses the LTM2881 of ADI company, this chip is that a completely to be galvanically isolated type entirely double
RS485/RS422 μM of odule transceiver of work., without using outer member, single power supply is integrated by one, is isolated, low noise for it
Sound, the two sides that efficient 5V output DC/DC converter is interface power.The highest transmission rate of this chip is up to 20Mbps.
As seen from Figure 1, RS-422 level signal is switched to Transistor-Transistor Logic level signal by LTM2881 and is introduced by system
In common IO mouthfuls of FPGA gate array XC7K325TFFG676, while being controlled in the Memory of gate array XC7K325TFFG676
Carry DDR chip MT41K128M16JT-125IT in interface.It is connected using the PCIe interface of gate array XC7K325TFFG676
PXIe bus signals.By using PCIe the and MIG IP kernel that Xilinx company provides, board be may be implemented and PXIe bus
Data are handed over and the read-write to DDR data.Solution protocol procedure is compiled by using SDLC agreement, may be implemented to synchronous serial interface data
It writes and parses.Fig. 2 show the circuit diagram using gate array GTX interface connection PCIe x4 bus, meets GTX in figure
The RX and TX signal of mouth are introduced directly into PCIe connector, and the CLK signal in PCIe is introduced into GTX.
Fig. 3 show board system work flow diagram.Firstly, initialized first after system starts, it is laggard
Enter wait state, after the FPGA of board receives RS-422 synchronous serial interface data enter branch 2. in, pass through FPGA gate array
The parsing of the SDLC agreement of internal composition, if the data fit SDLC agreement received, gate array store communication data
Into DDR.When PXIe bus needs to be read out data, 3. system enters branch's process, and FPGA control will store in DDR
Reading data come out, be transferred in PXIe bus later.When the output of PXIe bus control data, system enters branch's process
1. FPGA first by the data write-in DDR memory of PCIe input, then by the SDLC protocol procedure of gate array internal to data into
Row synchronization process, is finally sent in synchronous serial interface.
Above embodiments be only to a kind of concrete application example of the high-speed synchronous serial port board based on PXIe bus of the present invention,
Not, the claim of this application is limited.All modifications carried out in the claim of this application technical solution and non-intrinsically safe improve
, within the claim of this application protection scope.
The present invention does not address place and is suitable for the prior art.
Claims (7)
1. a kind of high-speed synchronous serial port board based on PXIe bus, it is characterised in that it includes FPGA gate array unit, DDR memory
Particulate units and serial ports transceiving chip unit；The serial ports transceiving chip unit, FPGA gate array unit and DDR memory grain list
It is successively connected in bi-directional data between member.
2. a kind of high-speed synchronous serial port board based on PXIe bus according to claim 1, it is characterised in that FPGA described
Array element uses the XC7K325TFFG676 chip of Xilinx company production；The XC7K325TFFG676 chip has common IO
Interface and Memory control interface；The common I/O interface is for connecting FPGA gate array unit and serial ports transceiving chip unit；
The Memory control interface is for realizing the mounting DDR memory grain unit outside FPGA gate array unit.
3. a kind of high-speed synchronous serial port board based on PXIe bus according to claim 2, it is characterised in that FPGA described
The XC7K325TFFG676 chip belt of array element is used to connect the GTX interface and Memory interface of PXIe bus, realizes
Reading and writing data in data exchange and DDR memory grain unit between FPGA gate array unit and PXIe bus；The GTX interface
As PCIe interface.
4. a kind of high-speed synchronous serial port board based on PXIe bus according to claim 1, it is characterised in that the DDR memory
Particulate units use the MT41K128M16JT-125IT chip of MICRON company；The MIG IP kernel of the FPGA gate array unit
It can be used as the memory I P core with DDR memory grain unit, Read-write Catrol and storage for realizing DDR data.
5. a kind of high-speed synchronous serial port board based on PXIe bus according to claim 1, it is characterised in that the serial ports is received
The RS-422 electrical level transferring chip LTM2881 that chip unit uses ADI company is sent out, is a to be galvanically isolated type full duplex RS485/
RS422 μM of odule transceiver.
6. a kind of high-speed synchronous serial port board based on PXIe bus according to claim 5, it is characterised in that the serial ports is received
Hair chip unit is made of two electrical level transferring chip LTM2881；Each electrical level transferring chip LTM2881 and FPGA gate array
Common I/O interface in column unit is in be bi-directionally connected.
7. a kind of working method of the high-speed synchronous serial port board based on PXIe bus, it is characterised in that it the following steps are included:
(1) the high-speed synchronous serial port board (hereinafter referred to as serial port board) based on PXIe bus is started to work, and after completing initialization, is entered
Task status is waited, if task is " FPGA gate array unit detects and reads synchronous serial interface signal ", operating procedure (2)-
(5)；When task is " PXIe bus read data ", then operating procedure (6)；When task is " it is required that PXIe bus control data
When output ", then operating procedure (7)；
(2) serial ports RS422 level signal is switched to Transistor-Transistor Logic level signal by serial ports transceiving chip unit, is introduced into FPGA gate array
In the common I/O port of the XC7K325TFFG676 chip of column unit, when FPGA gate array unit has detected that synchronous serial interface signal connects
Enter, and the task of high-speed synchronous serial port board is that when reading synchronous serial interface signal, this serial data is passed through FPGA at this time
The SDLC protocol procedure of array element internal composition is parsed, if data fit SDLC agreement, for valid data；
(3) effective rs 232 serial interface signal data are saved in DDR memory grain unit by FPGA gate array unit；
(4) it when high-speed synchronous serial port board receives external " sending data " instruction, will be assisted by the SDLC of FPGA gate array unit
The processing of agenda ordered pair synchronizing of data, and by treated, data are sent to synchronous serial interface, complete high-speed synchronous serial port board
Work；
(5) when high-speed synchronous serial port board is not received by external " sending data " instruction, then continue to access external equipment, until
" sending data " instruction is received, is repeated step (4)；
(6) when PXIe bus needs to be read out serial data, whether basis " receives high-speed synchronous serial port board at this time
PCIe bus data request ", is operated；When a request is received, FPGA gate array unit will be from DDR memory grain unit
Stored data are read, and are transmitted in PXIe bus, the work of high-speed synchronous serial port board is completed；
(7) PXIe bus signals are connected using the PCIe interface of FPGA gate array unit XC7K325TFFG676；When PXIe bus
When needing that synchrodata is written, at this point, DDR memory is written in the data that FPGA gate array unit inputs PCIe interface
Grain unit, while high-speed synchronous serial port board wants real time scan " whether receiving the external command for sending data ", if so, by
The SDLC protocol procedure of FPGA gate array unit handles the synchronizing of data that PCIe interface inputs, and is sent to synchronous string
Mouthful, complete the work of high-speed synchronous serial port board；The same step of implementation procedure (4) and (5).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811138490.6A CN109522251A (en) | 2018-09-28 | 2018-09-28 | A kind of high-speed synchronous serial port board and its working method based on PXIe bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811138490.6A CN109522251A (en) | 2018-09-28 | 2018-09-28 | A kind of high-speed synchronous serial port board and its working method based on PXIe bus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109522251A true CN109522251A (en) | 2019-03-26 |
Family
ID=65771492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811138490.6A Withdrawn CN109522251A (en) | 2018-09-28 | 2018-09-28 | A kind of high-speed synchronous serial port board and its working method based on PXIe bus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109522251A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109947376A (en) * | 2019-04-04 | 2019-06-28 | 上海威固信息技术股份有限公司 | A kind of multi-protocol interface solid-state memory system realized based on FPGA |
| CN111124987A (en) * | 2019-12-30 | 2020-05-08 | 京信通信系统（中国）有限公司 | PCIE-based data transmission control system and method |
| CN114116563A (en) * | 2021-10-25 | 2022-03-01 | 天津市英贝特航天科技有限公司 | High-speed synchronous serial port module based on PCIE bus |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103279437A (en) * | 2013-06-03 | 2013-09-04 | 北京无线电测量研究所 | Real-time data recording device based on PXI express (PCI extensions for instrumentation) bus |
| CN103324132A (en) * | 2013-05-31 | 2013-09-25 | 陕西海泰电子有限责任公司 | Multichannel dynamic signal acquisition card based on PXI bus |
| CN207867496U (en) * | 2018-02-06 | 2018-09-14 | 西安凌北电子科技有限公司 | A kind of multi-channel serial port card based on PXIe buses |
-
2018
- 2018-09-28 CN CN201811138490.6A patent/CN109522251A/en not_active Withdrawn
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103324132A (en) * | 2013-05-31 | 2013-09-25 | 陕西海泰电子有限责任公司 | Multichannel dynamic signal acquisition card based on PXI bus |
| CN103279437A (en) * | 2013-06-03 | 2013-09-04 | 北京无线电测量研究所 | Real-time data recording device based on PXI express (PCI extensions for instrumentation) bus |
| CN207867496U (en) * | 2018-02-06 | 2018-09-14 | 西安凌北电子科技有限公司 | A kind of multi-channel serial port card based on PXIe buses |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109947376A (en) * | 2019-04-04 | 2019-06-28 | 上海威固信息技术股份有限公司 | A kind of multi-protocol interface solid-state memory system realized based on FPGA |
| CN109947376B (en) * | 2019-04-04 | 2024-02-09 | 上海威固信息技术股份有限公司 | Multi-protocol interface solid-state storage system based on FPGA |
| CN111124987A (en) * | 2019-12-30 | 2020-05-08 | 京信通信系统（中国）有限公司 | PCIE-based data transmission control system and method |
| CN111124987B (en) * | 2019-12-30 | 2021-06-22 | 京信通信系统（中国）有限公司 | PCIE-based data transmission control system and method |
| CN114116563A (en) * | 2021-10-25 | 2022-03-01 | 天津市英贝特航天科技有限公司 | High-speed synchronous serial port module based on PCIE bus |
| CN114116563B (en) * | 2021-10-25 | 2023-08-29 | 天津市英贝特航天科技有限公司 | High-speed synchronous serial port module based on PCIE bus |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6353867B1 (en) | Virtual component on-chip interface | |
| US9424214B2 (en) | Network interface controller with direct connection to host memory | |
| US20040054864A1 (en) | Memory controller | |
| CN109189716A (en) | A kind of data transmission system and transmission method based on FPGA | |
| CN105468547A (en) | AXI bus based convenient configurable frame data access control system | |
| CN109522251A (en) | A kind of high-speed synchronous serial port board and its working method based on PXIe bus | |
| JPH02227766A (en) | Data transfer apparatus for digital computer | |
| CN102023956A (en) | Serial peripheral slave device interface structure in integrated circuit chip and data reading and writing method | |
| US20100064083A1 (en) | Communications device without passive pullup components | |
| CN111338996B (en) | Composite bus controller supporting multiple protocols | |
| CN116841932A (en) | Flexibly-connectable portable high-speed data access equipment and working method thereof | |
| CN102169470A (en) | Conversion bridge from advanced high performance bus (AHB) to basic virtual component interface (BVCI) | |
| CN109840233B (en) | 60X bus bridging system, method and medium based on FPGA | |
| CN110990310B (en) | Device side SD controller, control method and electronic device | |
| US6662258B1 (en) | Fly-by support module for a peripheral bus | |
| CN110008162B (en) | Buffer interface circuit, and method and application for transmitting data based on buffer interface circuit | |
| CN104598404A (en) | Computing equipment extending method and device as well as extensible computing system | |
| CN218068843U (en) | Bridging circuit structure for converting AXI master port into APB slave port and SOC system | |
| US20040064660A1 (en) | Multiplexed bus with multiple timing signals | |
| US7047385B1 (en) | High-speed memory for use in networking systems | |
| CN115982071A (en) | DDR3 controller-oriented network-on-chip conversion interface | |
| US20070131767A1 (en) | System and method for media card communication | |
| CN108228517A (en) | I3C circuit arrangements, system and communication means | |
| US11789884B2 (en) | Bus system and method for operating a bus system | |
| CN112835834B (en) | Data transmission system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20190326 |
|
| WW01 | Invention patent application withdrawn after publication |