CN111124987A - PCIE-based data transmission control system and method - Google Patents
PCIE-based data transmission control system and method Download PDFInfo
- Publication number
- CN111124987A CN111124987A CN201911399134.4A CN201911399134A CN111124987A CN 111124987 A CN111124987 A CN 111124987A CN 201911399134 A CN201911399134 A CN 201911399134A CN 111124987 A CN111124987 A CN 111124987A
- Authority
- CN
- China
- Prior art keywords
- data
- interface
- pcie
- module
- writing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
Abstract
The application provides a PCIE-based data transmission control system and a PCIE-based data transmission control method, which comprise the following steps: the PCIE data reading module, the PCIE data writing module and the PCIE control module are respectively connected with the PCIE transmission module; the transmission module is used for transmitting data to be read and/or data to be written; the data reading module is used for sequentially writing first information when a first interface connected with the data reading module is at a low level, and sequentially reading data to be read according to the writing sequence and the number of times of the first information when a second interface connected with the data reading module is at a high level; the data writing module is used for sequentially writing second information when a third interface connected with the data writing module is at a low level, and writing data to be written into the corresponding storage space according to the writing sequence and the writing times of the second information when a fourth interface connected with the data writing module is at a high level; the control module is used for modifying the level of each interface connected with the data reading module and/or the data writing module according to the read and/or write data.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a data transmission control system and method based on PCIE.
Background
In a communication system, as the amount of data to be transmitted increases, the requirement for the transmission speed of the amount of data is higher, and at present, in order to increase the speed of data transmission, a PCIE bus for high-speed transmission is increasingly applied in the communication system, and when data is transmitted between the PCIE bus and a computer, a Direct Memory Access (DMA) control transmission mode is usually adopted to increase the speed of data transmission, but in the existing DMA control, the encapsulation is very independent and the DMA-controlled address is relatively fixed, so that the address of reading data or the address of writing data is relatively fixed, and the flexibility is insufficient, and thus, the PCIE resource cannot be efficiently utilized for transmission.
Disclosure of Invention
The application provides a PCIE-based data transmission control system and a PCIE-based data transmission control method, which are used for improving the utilization rate of PCIE resources.
In one aspect, a PCIE-based data transmission control system is provided, including:
the PCIE data reading module, the PCIE data writing module and the PCIE control module are respectively connected with the PCIE transmission module;
the PCIE transmission module is used for transmitting data to be read and/or data to be written;
the PCIE data reading module is configured to sequentially write in first information corresponding to each data packet in the obtained data to be read when a first interface connected to the PCIE data reading module is at a low level, and sequentially read data corresponding to each data packet in the data to be read according to the writing times and the writing order of the first information when a second interface connected to the PCIE data reading module is at a high level, where the first information includes a storage header address and a data length of each data packet in the data to be read;
the PCIE write data module is configured to sequentially write second information of each data packet in the obtained data to be written when a third interface connected to the PCIE write data module is at a low level, and sequentially write data corresponding to each data packet in the data to be written into a corresponding storage space according to the writing times and the writing order of the second information when a fourth interface connected to the PCIE write data module is at a high level, where the second information includes a storage head address and a data length of each data packet in the data to be written;
the PCIE control module is configured to control, according to data reading and/or data writing, to modify the level of each interface connected to the PCIE data reading module, and/or control to modify the level of each interface connected to the PCIE data writing module.
In one possible design, the PCIE read data module includes a first submodule and a second submodule, where:
the first sub-module is configured to store first information corresponding to each data packet in the data to be read, which is written in sequence, when a first interface connected to the PCIE data reading module is at a low level;
and the second sub-module is configured to receive, when a second interface connected to the PCIE data reading module is at a high level, data corresponding to each data packet in the data to be read, which is sequentially read according to the writing times and the writing order of the first information.
In one possible design, the first interface and the second interface are interfaces in the PCIE transmission module, the first interface includes a first transmission valid interface and a first valid value indication interface, and when a level of the first transmission valid interface is a low level, the first interface is a low level;
the second interface comprises a second transmission effective interface and a second effective value indicating interface, and when the second transmission effective interface and the second effective value indicating interface are both at a high level, the second interface is at a high level;
the first transmission effective interface and the second transmission effective interface are used for indicating the transmission state of the PCIE transmission module, the high level is transmission permission, and the low level is transmission waiting; the first effective value indicating interface is used for indicating the writing state of the first information, and the high level is writing permission; the low level is waiting for writing, the second effective value indicating interface is used for indicating the state of reading the data to be read, the high level is allowed to be read, and the low level is waiting for reading.
In one possible design, the PCIE write data module includes: a third sub-module and a fourth sub-module, wherein:
the third sub-module is configured to store second information of each data packet in the to-be-written data that is written in sequence when the third interface connected to the PCIE data writing module is at a low level;
the fourth sub-module is configured to receive, when the fourth interface connected to the PCIE data writing module is at a high level, data corresponding to each data packet in the to-be-written data that is written according to the writing times and the writing order of the second information.
In one possible design, the third interface includes a third transmission active interface and a third valid value indication interface, and when the third transmission active interface is at a low level, the third interface is at a low level;
the fourth interface comprises a fourth transmission effective interface and a fourth effective value indicating interface, and when the fourth transmission effective interface and the fourth effective value indicating interface are both at a high level, the fourth interface is at a high level;
the third transmission effective interface and the fourth transmission effective interface are used for indicating the transmission state of the PCIE transmission module, where a high level is transmission permission, and a low level is transmission waiting; the third effective value indicating interface is used for indicating the writing state of the second information, and the high level is writing permission; the low level is waiting for writing, the fourth effective value indicates that the interface is used for indicating the state of writing the data to be written, the high level is allowed to be written, and the low level is waiting for writing.
In a possible design, the PCIE read data module is further connected to a first burst mode setting interface in the PCIE transmission module;
the first burst mode interface is used for indicating a mode for reading data corresponding to each data packet in the data to be read, and when the first burst mode interface is set to be at a high level, the first burst mode interface characterizes that the data is read in batches according to the data storage head address and the data length of each data packet in the data to be read;
the PCIE control module is further configured to configure the first burst mode setting interface to a high level, so that a reading mode of the data to be read is adjusted to be batch read data.
In a possible design, the PCIE write data module is further connected to a second burst mode interface in the PCIE transmission module;
the second burst mode interface is used for indicating a mode of writing data corresponding to each data packet in the data to be written; when the second burst mode setting interface is in a high level, writing data in batches according to the data head address and the data length of each data packet in the data to be written;
the PCIE control module is further configured to configure the second burst mode setting interface to a high level, so that the writing manner of the data to be written is adjusted to be batch writing data.
In a second aspect, an embodiment of the present application provides a PCIE-based data transmission control method, where the method is applied to the PCIE-based data transmission control system, where the system includes a PCIE transmission module, a PCIE read data module, a PCIE write data module, and a PCIE control module, which are connected in sequence, and the method includes:
obtaining a data operation instruction, and determining first information corresponding to each data packet in data to be read or second information corresponding to each data packet in the data to be written according to the data operation instruction, wherein the first information comprises a storage head address and a data length of each data packet in the data to be read, and the second information comprises a storage head address and a data length of each data packet in the data to be written;
determining the level states of a first interface and a second interface connected with the PCIE data reading module, or determining the level states of a third interface and a fourth interface connected with the PCIE data writing module;
when the first interface is at a low level, sequentially writing first information corresponding to each data packet in the obtained data to be read into the PCIE data reading module, and when the second interface is at a high level, sequentially reading data corresponding to each data packet in the data to be read by using the PCIE data reading module according to the writing times and the writing order of the first information;
and when the third interface is at a low level, writing the obtained second information of each data packet in the data to be written into the PCIE data writing module in sequence, and when the fourth interface is at a high level, writing the data corresponding to each data packet in the data to be written into the corresponding storage space in sequence according to the writing times and the writing sequence of the second information.
In one possible design, the first interface includes a first transport-active interface and a first-active-value-indicating interface, and when the level of the first transport-active interface is low, the first interface is low; the second interface comprises a second transmission valid interface and a second valid value indication interface; and when the second transmission effective interface and the second effective value indicating interface are both in a high level, the second interface is in a high level.
If the data operation instruction is an instruction for reading data, after the data operation instruction is obtained, the method further includes:
configuring the first transmission effective interface and the first effective value indicating interface to be high level, and configuring the second transmission effective interface and the second effective value indicating interface to be high level, so that the PCIE transmission module transmits the first information corresponding to each data packet in the data to be read, and transmits the data to be read.
In one possible design, the third interface includes a third transmission active interface and a third valid value indication interface, and when the third transmission active interface is at a low level, the third interface is at a low level; the fourth interface comprises a fourth transmission effective interface and a fourth effective value indicating interface, and when the fourth transmission effective interface and the fourth effective value indicating interface are both at a high level, the fourth interface is at a high level;
if the data operation instruction is an instruction for writing data, after the data operation instruction is obtained, the method further includes:
configuring the third transmission effective interface and the third effective value indication interface to be high level, and configuring the fourth transmission effective interface and the fourth effective value indication interface to be high level, so that the PCIE transmission module transmits the second information corresponding to each data packet in the data to be written, and transmits the data to be written.
The data transmission control system based on the PCIE provided in the embodiment of the present application includes a PCIE data reading module, a PCIE data writing module, and a PCIE control module, which are respectively connected to the PCIE transmission module; the PCIE transmission module is used for transmitting data to be read and/or data to be written; the PCIE data reading module is configured to sequentially write first information corresponding to each data packet in the obtained data to be read when a first interface connected to the PCIE data reading module is at a low level, and sequentially read data corresponding to each data packet in the data to be read according to the writing times and the writing order of the first information when a second interface connected to the PCIE data reading module is at a high level, where the first information includes a storage header address and a data length of each data packet in the data to be read; the PCIE write data module is configured to sequentially write second information of each data packet in the obtained data to be written when a third interface connected to the PCIE write data module is at a low level, and sequentially write data corresponding to each data packet in the data to be written into a corresponding storage space according to the writing times and the writing order of the second information when a fourth interface connected to the PCIE write data module is at a high level, where the second information includes a storage head address and a data length of each data packet in the data to be written; and the PCIE control module is used for controlling and modifying the level of each interface connected with the PCIE data reading module and/or the level of each interface connected with the PCIE data writing module according to the reading of data and/or the writing of data.
In other words, the system in the embodiment of the present application may determine, according to the level state of the first interface, whether to need to obtain the first information of each data packet in the data to be read, and continuously write the first information into the PCIE data reading module or send the first information to the CPU corresponding to the system, so as to determine whether to read the data to be read according to the level state of the second interface; or whether second information of each data packet in the data to be written needs to be continuously written into the PCIE data writing module according to the level state of the third interface, and then whether the data to be read can be written according to the level state of the fourth interface, so that flexibility of data transmission control can be improved, the utilization rate of PCIE resources is improved, and meanwhile, the data reading or writing efficiency can also be improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application.
Fig. 1 is a schematic structural diagram of a PCIE-based data transmission control system according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of another PCIE-based data transmission control system according to an embodiment of the present application;
fig. 3 is a flowchart of a PCIE-based data transmission control method according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments, but not all embodiments, of the technical solutions of the present application. All other embodiments obtained by a person skilled in the art without any inventive step based on the embodiments described in the present application are within the scope of the protection of the present application.
The terms "first" and "second" in the description and claims of the present application and the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the term "comprises" and any variations thereof, which are intended to cover non-exclusive protection. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus. The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
In the embodiments of the present application, "a plurality" may mean at least two, for example, two, three, or more, and the embodiments of the present application are not limited.
Referring to fig. 1, a schematic structural diagram of a PCIE-based data transmission control system according to an embodiment of the present application is shown in fig. 1, where the PCIE-based data transmission control system (hereinafter, referred to as a system) may include a PCIE read data module, a PCIE write data module, and a PCIE control module, which are respectively connected to a PCIE transmission module. Wherein:
the PCIE transmission module may be configured to transmit data to be read or data to be written.
The PCIE data reading module may be configured to, when a first interface connected to the PCIE data reading module is at a low level, sequentially write first information corresponding to each data packet in the obtained data to be read, that is, write a storage header address and a data length of each data packet in the data to be read, and when a second interface connected to the PCIE data reading module is at a high level, sequentially read data corresponding to each data packet in the data to be read according to the writing times and the writing order of the first information.
In this embodiment of the application, when a first interface connected to the PCIE data reading module is at a low level, the obtained data storage head addresses of a plurality of data packets to be read and the data length to be read may be written into the PCIE data reading module continuously, and data corresponding to the plurality of data packets to be written may be used as data to be read. When the first interface is at a high level, the storage head address of data corresponding to each data packet in the data to be read and the data length of each data packet may be sent to a Central Processing Unit (CPU) corresponding to the system through the PCIE transmission module, and then the CPU may feed back the corresponding data to the PCIE transmission module according to the received data head address and data length in the data to be read, so that when the second interface connected to the PCIE read data module is at a high level, the PCIE read data module may sequentially read the data to be read that is fed back to the PCIE transmission module according to the write-in sequence of the storage head address and data length of the data corresponding to each data packet in the data to be read.
The PCIE write data module may be configured to, when a third interface connected to the PCIE write data module is at a low level, sequentially write second information of each data packet in the obtained data to be written, that is, a storage head address and a data length of data corresponding to each data packet, and when a fourth interface connected to the PCIE write data module is at a high level, sequentially write data corresponding to each data packet in the data to be written into the corresponding storage space according to the writing times and the writing order of the second information.
In this embodiment of the application, when the third interface connected to the PCIE data writing module is at a low level, the storage head addresses and the data lengths of the obtained data corresponding to the multiple data packets to be written may be continuously written to the PCIE data reading module, where the data corresponding to the multiple data packets to be written is the data to be written. When a third interface connected with the PCIE data writing module is at a high level, a storage head address of data corresponding to each data packet in the to-be-written data and a data length of each data packet may be sent to a CPU corresponding to the system through the PCIE transmission module to notify the CPU of the address of data writing and the length of each packet of data.
The PCIE control module may be configured to control, according to reading of data and/or writing of data, to modify the level of each interface connected to the PCIE data reading module, and/or control to modify the level of each interface connected to the PCIE data writing module.
In specific implementation, the system may respectively perform data reading or data writing, or may simultaneously perform data reading and data writing, and then the PCIE control module may modify and adjust the level state of each interface in the PCIE transmission module connected to the PCIE data reading module and/or modify and adjust the level state of each interface of the PCIE transmission module connected to the PCIE data writing module according to the data reading and/or writing performed by the system, so that the PCIE data reading module can normally read data, and the PCIE data writing module can normally write data.
In the embodiment of the application, the system can transmit read data and write data in a differentiated manner, and can sequentially write first information of data corresponding to each data packet in the obtained data to be read into the PCIE data reading module when a first interface connected to the PCIE data reading module is at a low level, that is, when the PCIE transmission module does not satisfy the transmission condition. The data to be read can be composed of data packets to be read, which are obtained for multiple times, so that the data to be read can correspond to at least one piece of first information, and further, when the PCIE transmission module meets the condition, the at least one piece of first information can be sequentially transmitted to the CPU, so that the data corresponding to the at least one data packet can be sequentially obtained according to the at least one piece of first information. Therefore, compared with the related art in which the storage head address of the data corresponding to the data packet to be read cannot be written when the transmission condition is not satisfied, the control method is more flexible, and the utilization rate of the PCIE resource can be improved and the transmission efficiency can be improved.
Similarly, when a first interface connected to the PCIE write data module is at a high level, second information corresponding to each data packet in the obtained data to be written may be sequentially written into the PCIE write module, because the data to be written may be composed of a plurality of obtained data packets to be written, at least one piece of second information corresponding to the data to be written may also be written, and further when the PCIE transmission module satisfies the transmission condition, the at least one piece of second information may be sequentially transmitted to the CPU, so that the CPU may know an address of data write and a data length of each write, and the data length determines how many data are written and how many registers are occupied. Therefore, when there are a plurality of second information and the storage first address corresponding to each second information is different, that is, the amount of data to be written generated by the CPU is large and needs to be stored in a plurality of different storage spaces, the data to be written can be sequentially written into the corresponding storage spaces according to the obtained writing sequence of the plurality of second information, so as to implement continuous writing of the data, thereby improving the writing efficiency of the data and improving the utilization rate of PCIE resources.
Referring to the specific schematic diagram of the data transmission control system based on PCIE shown in fig. 2, as shown in fig. 2, the PCIE transmission module has three sets of aix interfaces, and the PCIE read data module, the PCIE write data module, and the PCIE control module can be respectively connected through the three sets of interfaces.
In a specific implementation, the first interface and the second interface in the PCIE read data module may be part of interfaces (hereinafter, simply referred to as the first group aix interfaces) in the interfaces connected to the PCIE read data module, among the three groups of receiving aix interfaces of the PCIE transmission module. As shown in fig. 2, the PCIE data reading module may include a first sub-module and a second sub-module, where the first sub-module may also be referred to as a read data address transmission module, is connected to the first interface, and may be configured to store first information corresponding to each data packet in the data to be read that is written into the PCIE data reading module in sequence when the first interface is at a low level; the second sub-module, which may also be referred to as a data reading module, is connected to the second interface, and may be configured to receive, when the second interface is at a high level, data corresponding to each data packet in the data to be read, which is sequentially read by the PCIE data reading module according to the writing times and the writing order of the first information.
The first interface comprises a first transmission effective interface and a first effective value indicating interface, wherein the first transmission effective interface is used for indicating the transmission state of the PCIE transmission module, the PCIE transmission module is in the transmission state at a high level, and the PCIE transmission module is in the transmission state at a low level; the first effective value indicating interface is used for indicating the writing state of the first information, and the representation is in the writing state at high level; low level indicates a wait for write condition. If the first transmission active interface is at a low level, the level of the first interface may be considered as a low level, that is, when the first transmission active interface is at a low level, the first interface may be considered as a low level regardless of whether the first active value indicates that the interface is at a high level or a low level; when both the first transport-active interface and the first active value indicate that the interfaces are high, the first interface may be considered high.
Specifically, when the system starts to read data, the PCIE control module may configure the first effective value indication interface to be a high level, so that the first information corresponding to each data packet in the obtained data to be read may be written into the first sub-module in real time, and when the first transmission effective interface is waiting for the high level, the first information corresponding to each data packet in the data to be read may be sequentially sent to the CPU corresponding to the system according to the writing order, so as to improve the transmission efficiency of the first information.
The second interface comprises a second transmission effective interface and a second effective value indicating interface, the second transmission effective interface is used for indicating the transmission state of the PCIE transmission module, the transmission state is in the high level state, and the transmission state is waited in the low level state; the second effective value indicating interface is used for indicating the state of reading data to be read, the high level is the reading state, and the low level is the waiting reading state. When the second transmission valid interface and the second valid value indication interface are both at a high level, the second interface may be regarded as a high level, so that the data to be read may be read according to the aforementioned sequence and number of times of writing the first information.
Further, the PCIE read data module may further be connected to a first burst mode setting interface in the first group aix of the PCIE transmission module, where the first burst mode setting interface may be used to indicate a manner of reading data corresponding to each data packet in the data to be read. When the first burst mode setting interface is at a high level, batch reading can be represented according to the data storage head address and the data length of each data packet in the data to be read; when the first burst mode setting interface is in a low level, the data corresponding to each data packet in the data to be read can be read sequentially one by one according to the storage address of each data packet.
Preferably, in this embodiment of the application, before the PCIE read data module reads data, or when the system starts to read data, the PCIE control module configures the first burst mode setting module to a high level, so as to read the data to be read in batch according to a storage head address and a data length of data corresponding to each data packet in the data to be read, thereby improving the data reading efficiency.
Further, the PCIE read data module may further connect a first transmission data length interface and a first transmission end indication interface in the first group aix of the PCIE transmission module, where the first transmission data length interface may be used to set a data length that the PCIE transmission module can transmit at each time. The first transmission end indication interface may be configured to indicate whether reading of the data to be read is completed, and specifically, if the first transmission end indication interface is at a high level, it is characterized that reading of the data to be read is completed, and if the first transmission end indication interface is at a low level, it is characterized that reading of the data to be read is not completed, so whether reading of the data to be read is completed may be determined according to a level state of the interface.
In this embodiment of the application, the third interface and the fourth interface in the PCIE write data module may be part of interfaces (hereinafter, simply referred to as the second group aix interfaces) in the interfaces connected to the PCIE write data module in the three groups aix interfaces of the PCIE transmission module. As shown in fig. 2, the PCIE write data module includes a third sub-module and a fourth word module, where the third sub-module may also be referred to as a write data address transmission module, is connected to the third interface, and may be configured to store second information corresponding to each data packet in the data to be written that is written in sequence when the third interface is at a low level; the third sub-module, which may also be referred to as a data writing module, is connected to the fourth interface, and is configured to receive, when the fourth interface is at a high level, data corresponding to each data packet in the to-be-written data that is written in sequence according to the writing times and the writing order of the second information.
Wherein the third interface may include a third transport-valid interface and a third-valid-value-indication interface. The third transmission effective interface is used for indicating the transmission state of the PCIE transmission module, and the representation is in the transmission state at the high level and the representation is in the transmission waiting state at the low level; the third effective value indicating interface is used for indicating the writing state of the second information, and the writing state is represented at high level; low level characterizes the wait for write state. The third interface may be considered low when the third transport-active interface is low, i.e. the third interface may be considered low when the third transport-active interface is low, regardless of whether the third active value indicates that the interface is high or low.
Specifically, when the system starts to write data, the PCIE control module may configure the third effective value indication interface to be at a high level, so that second information corresponding to each data packet in the obtained data to be written may be written in the third sub-module in real time, and when waiting for the third transmission effective interface to be at the high level, the second information corresponding to each data packet in the data to be written may be sequentially sent to the CPU corresponding to the system according to the writing sequence, thereby improving the transmission efficiency of the second information.
The fourth interface may include a fourth transmission effective interface and a fourth effective value indication interface, where the fourth transmission effective interface is used to indicate a transmission state of the PCIE transmission module, and represents that the PCIE transmission module is in a transmission state at a high level and represents that the PCIE transmission module is in a transmission waiting state at a low level; the fourth effective value indicating interface is used for indicating the state of writing data to be written, wherein the high level is in a writing state, and the low level is in a writing waiting state. When the fourth transmission effective interface and the fourth effective value indicate that the interfaces are both at a high level, the fourth interface can be regarded as the high level, so that the data to be written can be written according to the writing sequence and the writing times of the second information; when any one of the fourth transmission effective interface and the fourth effective value indication interface is at a low level, the fourth interface may be regarded as a low level, and when both the fourth transmission effective interface and the fourth effective value indication interface are at a high level, data starts to be written.
Further, the PCIE write data module may further be connected to a second burst mode setting interface in a second group of aix interfaces in the PCIE transmission module, where the second burst mode setting interface may be configured to indicate a manner of writing data corresponding to each data packet in the to-be-written data into the storage space corresponding to the second information. When the second burst mode setting interface is in a high level, representing that data are written in batches according to the data head address and the data length of each data packet in the data to be written; when the second burst mode sets the interface to be at a low level, the data corresponding to each data packet in the data to be written can be characterized according to the storage address of each data packet one by one.
Preferentially, in the embodiment of the present application, before the PCIE write data module writes data, or when the system starts to write data, the PCIE control module configures the second burst mode setting interface to be a high level, so as to write data to be written in batch according to a storage head address and a data length corresponding to each data packet in the data to be written, thereby improving the data writing efficiency.
Further, the PCIE write data module may further be connected to a second transmission data length interface and a second transmission end indication interface in the second group aix interfaces of the PCIE transmission module, where the second transmission data length interface may be used to set a length of data transmitted by the PCIE transmission module each time when data is written by the system, so as to determine the number of data written and how many registers the written data needs to occupy. The second transmission end indication interface may be configured to indicate whether the data to be written is completely written, indicate that the data to be written is completely written if the second transmission end indication interface is at a high level, and indicate that the data to be written is not completely written if the second transmission end indication interface is at a low level, so that whether the data to be written is completely written may be determined according to a level state of the interface.
Referring to fig. 3, based on the same inventive concept, an embodiment of the present application further provides a PCIE-based data transmission control method, where the method is applicable to the PCIE-based data transmission control system, and the PCIE-based data transmission control system includes a PCIE transmission module, a PCIE read data module, a PCIE write data module, and a PCIE control module, and the method includes:
step 301: obtaining a data operation instruction, and determining first information corresponding to each data packet in data to be read or second information corresponding to each data packet in the data to be written according to the data operation instruction, wherein the first information comprises a storage head address and a data length of each data packet in the data to be read, and the second information comprises a storage head address and a data length of each data packet in the data to be written;
in this embodiment of the present application, the data operation instruction may include two instructions, that is, a data reading instruction and a data writing instruction, and if the data operation instruction is data reading, the data operation instruction may carry first information corresponding to each data packet in the data to be read, where the first information includes a storage head address and a data length of data in the data packet; if the data operation instruction is write data, the data operation instruction may carry second information corresponding to each data packet in the data to be written, where the second information may include a storage head address and a data length included in each data packet in the data to be written, in other words, when the data operation instruction may carry a storage space in which the data to be written is to be written, a storage head address of first data in each data packet in the storage space and a length of data in each redemption packet.
Step 302: and judging the level states of a first interface and a second interface connected with the PCIE data reading module, or judging the level states of a third interface and a fourth interface connected with the PCIE data writing module.
In this embodiment of the present application, the first interface includes a first transmission valid interface and a first valid value indication interface, and when the first transmission valid interface is at a low level, the level of the first interface may be regarded as a low level; when both the first transport-active interface and the first active value indicate that the interfaces are high, the first interface may be considered high. The second interface comprises a second transmission effective interface and a second effective value indicating interface, and when the second transmission effective interface and the second effective value indicating interface are both at a high level, the second interface can be regarded as a high level; the second interface may be considered low when the second transport-active interface and the second active value indicate that the level of either interface is low.
The third interface may include a third transport-active interface and a third-active-value-indicating interface, and when the third transport-active interface is low, the third interface may be considered low; when the third transfer active interface and the third active value indicate that the interfaces are both high, the first interface may be considered high. The fourth interface may include a fourth transmission effective interface and a fourth effective value indication interface, and when both the fourth transmission effective interface and the fourth effective value indication interface are at a high level, the fourth interface may be regarded as a high level, and when either one of the fourth transmission effective interface and the fourth effective value indication interface is at a low level, the fourth interface may be regarded as a low level.
Since the functions of the interfaces are described in the system section, the description is omitted here. After step 302 is performed, step 303 or step 304 may be continued.
Step 303: when the first interface is at a low level, writing first information corresponding to each data packet in the obtained data to be read into the PCIE data reading module in sequence, and when the second interface is at a high level, reading data corresponding to each data packet in the data to be read in sequence by using the PCIE data reading module according to the writing times and the writing sequence of the first information.
In this embodiment of the application, when it is determined that the first interface is at a low level, that is, the first transmission effective interface is at a low level, the storage head address of each data packet in the obtained data to be read and the length of the data to be read may be written into the PCIE data reading module continuously, that is, at least one piece of first information may be written into the PCIE data reading module continuously. That is to say, the first information corresponding to each data packet to be read can be written into the PCIE data reading module when the first interface is at the low level, and then can be sequentially sent to the CPU corresponding to the system according to the at least one first information writing sequence and the number of times when the first interface is at the high level, so that the transmission efficiency of the first information is improved, the occurrence of situations of missed writing or repeated writing is avoided, and the utilization rate of PCIE resources is improved.
Furthermore, the CPU may feed back the corresponding data to the PCIE transmission module according to the first address and the data length of the data to be read, and when the second interface is at a high level, the PCIE read data module may sequentially read the plurality of data packets in the data to be read that are fed back to the PCIE transmission module according to the write-in order of the first address and the data length of the data corresponding to each data packet in the data to be read, thereby completing reading of the data to be read.
Preferentially, when the instruction of the reading data is obtained, the first transmission effective interface and the first effective value indicating interface are configured to be at a high level, so that the PCIE transmission module can transmit the first information corresponding to each data packet in the data to be read to the CPU, and the second transmission effective interface and the second effective value indicating interface are configured to be at a high level, so that the PCIE transmission module can transmit the data to be read, thereby improving the efficiency of reading the data to be read.
Step 304: and when the third interface is at a low level, writing the second information of each data packet in the obtained data to be written into the PCIE data writing module in sequence, and when the fourth interface is at a high level, writing the data corresponding to each data packet in the data to be written into the corresponding storage space in sequence according to the writing times and the writing sequence of the second information.
In this embodiment of the application, when the third interface is at a low level, that is, the third transmission effective interface is at a low level, the storage head address and the data length of the obtained corresponding data of the at least one to-be-written data packet may be continuously written into the PCIE data reading module, that is, the obtained at least one second information is continuously written into the corresponding data. When the third interface is at a high level, the second information can be sequentially sent to the CPU corresponding to the system according to the writing sequence and the number of times of the at least one second information, so as to inform the CPU of the address of data writing and the length of each packet of data, thereby improving the transmission efficiency of the first information, avoiding the occurrence of missed writing or repeated writing, and improving the utilization rate of PCIE resources.
Further, when the CPU generates data to be written, the data to be written may be fed back to the PCIE transmission module, and when a fourth interface connected to the PCIE data writing module is at a high level, the PCIE data writing module writes the data to be written transmitted by the PCIE transmission module, and sequentially writes the data to be written into the corresponding storage space for storage according to a writing sequence of a storage head address and a data length of data corresponding to each data packet in the data to be written. The storage space may be a space that can be used for storing data, such as a register, a memory, and a flash memory.
Preferably, when the instruction for writing data is obtained, the first transmission valid interface and the first valid value indication interface may be configured to be at a high level, so that the PCIE transmission module may transmit the first information corresponding to each data packet in the data to be read to the CPU, and the fourth transmission valid interface and the fourth valid value indication interface are configured to be at a high level, so that the PCIE transmission module may transmit the data to be written. Thereby improving the efficiency of writing data to be written.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
1. A data transmission control system based on a PCIE peripheral device interconnection bus is characterized by comprising:
the PCIE data reading module, the PCIE data writing module and the PCIE control module are respectively connected with the PCIE transmission module; wherein:
the PCIE transmission module is used for transmitting data to be read and/or data to be written;
the PCIE data reading module is configured to sequentially write in first information corresponding to each data packet in the obtained data to be read when a first interface connected to the PCIE data reading module is at a low level, and sequentially read data corresponding to each data packet in the data to be read according to the writing times and the writing order of the first information when a second interface connected to the PCIE data reading module is at a high level, where the first information includes a storage header address and a data length of each data packet in the data to be read;
the PCIE write data module is configured to sequentially write second information of each data packet in the obtained data to be written when a third interface connected to the PCIE write data module is at a low level, and sequentially write data corresponding to each data packet in the data to be written into a corresponding storage space according to the writing times and the writing order of the second information when a fourth interface connected to the PCIE write data module is at a high level, where the second information includes a storage head address and a data length of each data packet in the data to be written;
the PCIE control module is configured to control, according to data reading and/or data writing, to modify the level of each interface connected to the PCIE data reading module, and/or control to modify the level of each interface connected to the PCIE data writing module.
2. The system of claim 1, wherein the PCIE read data module includes a first sub-module and a second sub-module, wherein:
the first sub-module is configured to store first information corresponding to each data packet in the data to be read, which is written in sequence, when a first interface connected to the PCIE data reading module is at a low level;
and the second sub-module is configured to receive, when a second interface connected to the PCIE data reading module is at a high level, data corresponding to each data packet in the data to be read, which is sequentially read according to the writing times and the writing order of the first information.
3. The system according to claim 1 or 2, wherein the first interface and the second interface are interfaces in the PCIE transport module, the first interface includes a first transport-active interface and a first active-value-indicating interface, and when a level of the first transport-active interface is a low level, the first interface is a low level;
the second interface comprises a second transmission effective interface and a second effective value indicating interface, and when the second transmission effective interface and the second effective value indicating interface are both at a high level, the second interface is at a high level;
the first transmission effective interface and the second transmission effective interface are used for indicating the transmission state of the PCIE transmission module, the high level is transmission permission, and the low level is transmission waiting; the first effective value indicating interface is used for indicating the writing state of the first information, and the high level is writing permission; the low level is waiting for writing, the second effective value indicating interface is used for indicating the state of reading the data to be read, the high level is allowed to be read, and the low level is waiting for reading.
4. The system of claim 1, wherein the PCIE write data module comprises: a third sub-module and a fourth sub-module, wherein:
the third sub-module is configured to store second information of each data packet in the to-be-written data that is written in sequence when the third interface connected to the PCIE data writing module is at a low level;
the fourth sub-module is configured to receive, when the fourth interface connected to the PCIE data writing module is at a high level, data corresponding to each data packet in the to-be-written data that is written according to the writing times and the writing order of the second information.
5. The system of claim 1 or 4, wherein the third interface comprises a third transport-active interface and a third valid value indication interface, the third interface being low when the third transport-active interface is low;
the fourth interface comprises a fourth transmission effective interface and a fourth effective value indicating interface, and when the fourth transmission effective interface and the fourth effective value indicating interface are both at a high level, the fourth interface is at a high level;
the third transmission effective interface and the fourth transmission effective interface are used for indicating the transmission state of the PCIE transmission module, where a high level is transmission permission, and a low level is transmission waiting; the third effective value indicating interface is used for indicating the writing state of the second information, and the high level is writing permission; the low level is waiting for writing, the fourth effective value indicates that the interface is used for indicating the state of writing the data to be written, the high level is allowed to be written, and the low level is waiting for writing.
6. The system of claim 1, wherein the PCIE read data module is further connected to a first burst mode setting interface in the PCIE transmission module;
the first burst mode interface is used for indicating a mode for reading data corresponding to each data packet in the data to be read, and when the first burst mode interface is set to be at a high level, the first burst mode interface characterizes that the data is read in batches according to the data storage head address and the data length of each data packet in the data to be read;
the PCIE control module is further configured to configure the first burst mode setting interface to a high level, so that a reading mode of the data to be read is adjusted to be batch read data.
7. The system of claim 1, wherein the PCIE write data module is further connected to a second burst mode interface in the PCIE transmit module;
the second burst mode interface is used for indicating a mode of writing data corresponding to each data packet in the data to be written; when the second burst mode setting interface is in a high level, writing data in batches according to the data head address and the data length of each data packet in the data to be written;
the PCIE control module is further configured to configure the second burst mode setting interface to a high level, so that the writing manner of the data to be written is adjusted to be batch writing data.
8. A data transmission control method based on PCIE peripheral equipment interconnection bus is characterized in that the method is applied to a PCIE-based data transmission control system, the system comprises a PCIE transmission module, a PCIE data reading module, a PCIE data writing module and a PCIE control module which are connected in sequence, and the method comprises the following steps:
obtaining a data operation instruction, and determining first information corresponding to each data packet in data to be read or second information corresponding to each data packet in the data to be written according to the data operation instruction, wherein the first information comprises a storage head address and a data length of each data packet in the data to be read, and the second information comprises a storage head address and a data length of each data packet in the data to be written;
determining the level states of a first interface and a second interface connected with the PCIE data reading module, or determining the level states of a third interface and a fourth interface connected with the PCIE data writing module;
when the first interface is at a low level, sequentially writing first information corresponding to each data packet in the obtained data to be read into the PCIE data reading module, and when the second interface is at a high level, sequentially reading data corresponding to each data packet in the data to be read by using the PCIE data reading module according to the writing times and the writing order of the first information;
and when the third interface is at a low level, writing the obtained second information of each data packet in the data to be written into the PCIE data writing module in sequence, and when the fourth interface is at a high level, writing the data corresponding to each data packet in the data to be written into the corresponding storage space in sequence according to the writing times and the writing sequence of the second information.
9. The method of claim 8, wherein the first interface comprises a first transport-active interface and a first-active-value-indicating interface, the first interface being low when the level of the first transport-active interface is low; the second interface comprises a second transmission valid interface and a second valid value indication interface; when both a second transmission active interface and the second effective value indication interface are at a high level, the second interface is at a high level;
if the data operation instruction is an instruction for reading data, after the data operation instruction is obtained, the method further includes:
configuring the first transmission effective interface and the first effective value indicating interface to be high level, and configuring the second transmission effective interface and the second effective value indicating interface to be high level, so that the PCIE transmission module transmits the first information corresponding to each data packet in the data to be read, and transmits the data to be read.
10. The method of claim 8, wherein the third interface comprises a third transport-active interface and a third valid value indication interface, the third interface being low when the third transport-active interface is low; the fourth interface comprises a fourth transmission effective interface and a fourth effective value indicating interface, and when the fourth transmission effective interface and the fourth effective value indicating interface are both at a high level, the fourth interface is at a high level;
if the data operation instruction is an instruction for writing data, after the data operation instruction is obtained, the method further includes:
configuring the third transmission effective interface and the third effective value indication interface to be high level, and configuring the fourth transmission effective interface and the fourth effective value indication interface to be high level, so that the PCIE transmission module transmits the second information corresponding to each data packet in the data to be written, and transmits the data to be written.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911399134.4A CN111124987B (en) | 2019-12-30 | 2019-12-30 | PCIE-based data transmission control system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911399134.4A CN111124987B (en) | 2019-12-30 | 2019-12-30 | PCIE-based data transmission control system and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111124987A true CN111124987A (en) | 2020-05-08 |
| CN111124987B CN111124987B (en) | 2021-06-22 |
Family
ID=70505581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911399134.4A Active CN111124987B (en) | 2019-12-30 | 2019-12-30 | PCIE-based data transmission control system and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111124987B (en) |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100286102B1 (en) * | 1997-12-29 | 2001-04-16 | 윤종용 | Multi contact control apparatus using computer system |
| US20120017025A1 (en) * | 2010-07-15 | 2012-01-19 | Betty Luk | System and Method for Accessing Resources of a PCI Express Compliant Device |
| CN102339266A (en) * | 2011-10-28 | 2012-02-01 | 中国兵器工业集团第二一四研究所苏州研发中心 | Single data line bidirectional dual voltage communication interface circuit |
| CN103488600A (en) * | 2013-10-08 | 2014-01-01 | 江苏物联网研究发展中心 | Universal auxiliary machine synchronous serial interface circuit |
| US20150089106A1 (en) * | 2013-09-23 | 2015-03-26 | Hon Hai Precision Industry Co., Ltd. | Expansion card having two switchable connectors |
| CN105468547A (en) * | 2015-11-18 | 2016-04-06 | 哈尔滨工业大学 | AXI bus based convenient configurable frame data access control system |
| CN106776428A (en) * | 2016-12-06 | 2017-05-31 | 广州视源电子科技股份有限公司 | Terminal device, read-write equipment, data transmission system and hardware initialization method |
| CN108536614A (en) * | 2018-03-30 | 2018-09-14 | 天津麒麟信息技术有限公司 | A kind of direct random write implementation method of Flash, device and storage medium |
| CN108595350A (en) * | 2018-01-04 | 2018-09-28 | 深圳开阳电子股份有限公司 | A kind of data transmission method and device based on AXI |
| CN109471824A (en) * | 2018-11-22 | 2019-03-15 | 青岛方寸微电子科技有限公司 | Data transmission system and method based on AXI bus |
| CN109471816A (en) * | 2018-11-06 | 2019-03-15 | 西安微电子技术研究所 | A kind of PCIE bus dma controller and data transfer control method based on descriptor |
| CN109522251A (en) * | 2018-09-28 | 2019-03-26 | 天津市英贝特航天科技有限公司 | A kind of high-speed synchronous serial port board and its working method based on PXIe bus |
-
2019
- 2019-12-30 CN CN201911399134.4A patent/CN111124987B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100286102B1 (en) * | 1997-12-29 | 2001-04-16 | 윤종용 | Multi contact control apparatus using computer system |
| US20120017025A1 (en) * | 2010-07-15 | 2012-01-19 | Betty Luk | System and Method for Accessing Resources of a PCI Express Compliant Device |
| CN102339266A (en) * | 2011-10-28 | 2012-02-01 | 中国兵器工业集团第二一四研究所苏州研发中心 | Single data line bidirectional dual voltage communication interface circuit |
| US20150089106A1 (en) * | 2013-09-23 | 2015-03-26 | Hon Hai Precision Industry Co., Ltd. | Expansion card having two switchable connectors |
| CN103488600A (en) * | 2013-10-08 | 2014-01-01 | 江苏物联网研究发展中心 | Universal auxiliary machine synchronous serial interface circuit |
| CN105468547A (en) * | 2015-11-18 | 2016-04-06 | 哈尔滨工业大学 | AXI bus based convenient configurable frame data access control system |
| CN106776428A (en) * | 2016-12-06 | 2017-05-31 | 广州视源电子科技股份有限公司 | Terminal device, read-write equipment, data transmission system and hardware initialization method |
| CN108595350A (en) * | 2018-01-04 | 2018-09-28 | 深圳开阳电子股份有限公司 | A kind of data transmission method and device based on AXI |
| CN108536614A (en) * | 2018-03-30 | 2018-09-14 | 天津麒麟信息技术有限公司 | A kind of direct random write implementation method of Flash, device and storage medium |
| CN109522251A (en) * | 2018-09-28 | 2019-03-26 | 天津市英贝特航天科技有限公司 | A kind of high-speed synchronous serial port board and its working method based on PXIe bus |
| CN109471816A (en) * | 2018-11-06 | 2019-03-15 | 西安微电子技术研究所 | A kind of PCIE bus dma controller and data transfer control method based on descriptor |
| CN109471824A (en) * | 2018-11-22 | 2019-03-15 | 青岛方寸微电子科技有限公司 | Data transmission system and method based on AXI bus |
Non-Patent Citations (2)
| Title |
|---|
| W. YU: ""High Performance PCIe Interface for the TPCM Based on Linux Platfor"", 《2015 8TH INTERNATIONAL SYMPOSIUM ON COMPUTATIONAL INTELLIGENCE AND DESIGN (ISCID》 * |
| 赵珊珊: ""PCIE高速数据传输系统设计"", 《电脑知识与技术》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111124987B (en) | 2021-06-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109688058B (en) | Message processing method and device and network equipment | |
| US7433977B2 (en) | DMAC to handle transfers of unknown lengths | |
| WO2016127552A1 (en) | Direct memory access (dma) controller and data transmission method | |
| US20090119460A1 (en) | Storing Portions of a Data Transfer Descriptor in Cached and Uncached Address Space | |
| US5978865A (en) | System for performing DMA transfers where an interrupt request signal is generated based on the value of the last of a plurality of data bits transmitted | |
| KR100919159B1 (en) | Multimedia card interface method, computer program product and apparatus | |
| CN112947857B (en) | Data moving method, device, equipment and computer readable storage medium | |
| CN114138700A (en) | Flow control method, device, equipment and storage medium for serial port data transmission | |
| CN112181887B (en) | Data transmission method and device | |
| CN113157465B (en) | Message sending method and device based on pointer linked list | |
| KR102303424B1 (en) | Direct memory access control device for at least one processing unit having a random access memory | |
| CN111124987B (en) | PCIE-based data transmission control system and method | |
| US20080147906A1 (en) | DMA Transferring System, DMA Controller, and DMA Transferring Method | |
| CN111427806A (en) | Method for sharing serial port by dual-core AMP system, storage medium and intelligent terminal | |
| CN115934625A (en) | Doorbell knocking method, device and medium for remote direct memory access | |
| US20140052879A1 (en) | Processor, information processing apparatus, and interrupt control method | |
| CN111371799B (en) | Method, device and equipment for controlling data receiving and transmitting of MCTP (Multi-channel media Port) controller | |
| CN105022707B (en) | Interface unit device | |
| EP2413248A1 (en) | Direct memory access device for multi-core system and operating method of the same | |
| CN114327882A (en) | Data forwarding method, device and system | |
| CN104850517A (en) | Method and apparatus for transmitting packet data using DMA | |
| US11240178B2 (en) | Data transmission method and data transmission system | |
| US20090313393A1 (en) | Method of increasing efficiency of end point memory in usb devices | |
| CN116756075A (en) | Data transmission method, device, storage medium and equipment | |
| JP4969054B2 (en) | Information processing device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 510663 Shenzhou Road, Guangzhou Science City, Guangzhou economic and Technological Development Zone, Guangdong, 10 Patentee after: Jingxin Network System Co.,Ltd. Address before: 510663 Shenzhou Road, Guangzhou Science City, Guangzhou economic and Technological Development Zone, Guangdong, 10 Patentee before: Comba Telecom System (China) Ltd. |
|
| CP01 | Change in the name or title of a patent holder |