WO2016127552A1 - Direct memory access (dma) controller and data transmission method - Google Patents

Direct memory access (dma) controller and data transmission method Download PDF

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Publication number
WO2016127552A1
WO2016127552A1 PCT/CN2015/083289 CN2015083289W WO2016127552A1 WO 2016127552 A1 WO2016127552 A1 WO 2016127552A1 CN 2015083289 W CN2015083289 W CN 2015083289W WO 2016127552 A1 WO2016127552 A1 WO 2016127552A1
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cpu
data
item
dma controller
active
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PCT/CN2015/083289
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French (fr)
Chinese (zh)
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牟崧友
安康
王志忠
刘衡祁
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深圳市中兴微电子技术有限公司
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Publication of WO2016127552A1 publication Critical patent/WO2016127552A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Definitions

  • the present invention relates to Direct Memory Access (DMA) technology, and more particularly to a DMA controller and a method for data transmission.
  • DMA Direct Memory Access
  • direct memory access DMA technology is widely used in chip design. It is a data exchange mode that directly accesses data from memory without going through the CPU, and is an important technology for solving data interaction between memory and external chips.
  • the DMA controller can move data from one address space to another, and the transfer action itself is implemented and completed by the DMA controller, which saves the CPU's data bus bandwidth.
  • the corresponding DMA controller is usually implemented for different application scenarios, so that the implemented DMA controller mode is fixed and not flexible enough, so that multiple data transmission modes cannot share the DMA controller, which is not conducive to Save chip area.
  • an embodiment of the present invention provides a DMA controller and a data transmission method.
  • an embodiment of the present invention provides a DMA controller, where the DMA controller includes: a passive transmission unit, an active transmission unit, a DMA scheduling unit, and a shortcut external device interconnection PCIe unit, where
  • the passive transmission unit is configured to complete a data uploading and sending operation between the external chip and the CPU initiated by the CPU according to a transmission parameter configured by a CPU of the CPU;
  • the active transmission unit is configured to complete data between the external chip and the CPU initiated by an external chip by using a BD table and a data cache space that are set in the memory by the CPU and including at least one cache description BD item. Send and deliver operations;
  • the DMA scheduling unit is configured to avoid contention caused by data uploading and sending operations between the external chip and the CPU by means of arbitration;
  • the PCIe unit is configured to provide a PCIe interface for information interaction between the CPU and the DMA controller.
  • the passive transmission unit is specifically configured to:
  • the external chip source address preset by the CPU After receiving the uploading start command of the CPU configuration, the external chip source address preset by the CPU reads the data to be sent in the external chip memory to be passively sent according to the uplink data length preset by the CPU. Cache; and,
  • the CPU After the data to be sent is completely written to the memory destination address preset by the CPU, the CPU is notified to complete the writing.
  • the passive transmission unit is specifically configured to:
  • the memory source address preset by the CPU After receiving the sending start command of the CPU configuration, the memory source address preset by the CPU reads the to-be-distributed data in the memory to the passive sending buffer according to the issued data length preset by the CPU. ;as well as,
  • the CPU After the data to be delivered is completely written to the destination address of the external chip memory preset by the CPU, the CPU is notified to complete the delivery.
  • the active transmission unit is specifically configured as:
  • the feature information of the table wherein the feature information of the active BD table includes: a threshold value of the number of BD items in the BD table, and a first address and an end address stored in the BD table;
  • the content of the BD item in the BD table is: a valid indication of the BD item, an in-memory data block size corresponding to the BD item, and an in-memory data start address corresponding to the BD item;
  • the valid indication of the BD item is 0, the data to be sent in the active uplink buffer is transmitted to an in-memory data start address corresponding to the BD item, and the BD item is valid.
  • the indication is changed to 1, and the number of valid BD items saved by the active transmission unit itself is increased by one;
  • the active transmission unit is further configured to: receive the read completion information sent by the CPU after reading the data to be sent in the in-memory data start address corresponding to the BD item, and The number of valid BD items saved by the active transmission unit itself is reduced by one.
  • the active transmission unit is specifically configured as:
  • an embodiment of the present invention provides a data transmission method, where the method is applied to a DMA controller, and the method includes:
  • the DMA controller performs data uploading and sending between the external chip and the CPU initiated by an external chip by using a BD table and a data cache space of the CPU, which is set in the memory, including at least one cache description BD item. Send operation
  • the DMA controller avoids competition caused by data uploading and sending operations between the external chip and the CPU by means of arbitration, wherein information interaction between the CPU and the DMA controller is passed The PCIe interface is performed.
  • the DMA controller completes the data upload operation between the external chip and the CPU initiated by the CPU according to the transmission parameter configured by the CPU, including:
  • the external chip source address preset by the CPU reads the data to be sent in the external chip memory according to the uplink data length preset by the CPU. Take the passive send cache;
  • the DMA controller writes the data to be sent in the passive uplink buffer to the memory destination address preset by the CPU;
  • the DMA controller notifies the CPU that the writing is completed after the data to be sent is completely written to the memory destination address preset by the CPU.
  • the DMA controller completes the data delivery operation between the external chip and the CPU initiated by the CPU according to the transmission parameter configured by the CPU, including:
  • the memory source address preset by the CPU reads the data to be sent in the memory according to the length of the data sent by the CPU. To passively send the cache;
  • the DMA controller notifies the CPU that the delivery is completed after the data to be sent is completely written to the destination address of the external chip memory preset by the CPU.
  • the DMA controller completes data between the external chip and the CPU initiated by an external chip by using a BD table and a data cache space set by the CPU in the memory including at least one cache description BD item.
  • Upload operation including:
  • the DMA controller receives the feature information of the active delivery BD table that is sent by the CPU after the initialization completes the active delivery of the BD table, where the feature information of the active delivery BD table includes: the active delivery a threshold of the number of BD items in the BD table, the first address and the end address stored in the BD table; the content of the BD item in the active delivery BD table includes: a valid indication of the BD item, the BD The in-memory data block size corresponding to the item, and the in-memory data start address corresponding to the BD item;
  • the DMA controller receives the data to be sent sent by the external chip, and stores the data to be sent into the active upload cache in the DMA controller;
  • the DMA controller stores the BD table according to the active delivery The first address and the end address read the BD item;
  • the DMA controller transmits the data to be sent in the active uplink buffer to the in-memory data start address corresponding to the BD item, and the BD is The effective indication of the item is changed to 1, and the number of valid BD items saved by the active transmission unit itself is increased by one;
  • the DMA controller reads the next BD item of the BD item in the BD table according to the first address and the end address stored in the active delivery BD table.
  • the method further includes:
  • the DMA controller completes data between the external chip and the CPU initiated by an external chip by using a BD table and a data cache space set by the CPU in the memory including at least one cache description BD item. Delivery operations, including:
  • the DMA controller After receiving the active delivery start command sent by the CPU, the DMA controller reads the active delivery BD item according to the first address and the end address of the active delivery BD item;
  • the DMA controller transmits the data to be delivered in the memory space indicated by the active delivery BD item to the active delivery buffer, and transmits the data in the active delivery buffer to the memory of the external chip;
  • the DMA controller sends an active delivery completion response to the CPU.
  • Embodiments of the present invention provide a DMA controller and a data transmission method, which enable a plurality of data transmission modes to share the DMA controller through a DMA controller suitable for different application scenarios, which is highly versatile and saves CPU and external chip read and write data time, and can save chip area.
  • FIG. 1 is a schematic structural diagram of a DMA controller according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a memory space according to an embodiment of the present invention.
  • FIG. 3 is a schematic flowchart diagram of a method for data transmission according to an embodiment of the present invention.
  • the DMA controller 10 may include: a passive transmission unit 101, an active transmission unit 102, a DMA scheduling unit 103, and a shortcut external device.
  • a PCIe (Peripheral Component Interconnect Express) unit 104 wherein
  • the passive transmission unit 101 is configured to complete data uploading and sending operations between the external chip and the CPU initiated by the CPU according to the transmission parameters configured by the CPU;
  • the active transmission unit 102 is configured to complete data between the external chip and the CPU initiated by the external chip by using a BD table and a data cache space that are set in the memory by the central processing unit CPU and including at least one BD (Buffer Descriptor) item. Send and send operations;
  • the DMA scheduling unit 103 is configured to avoid competition caused by data uploading and sending operations between the external chip and the CPU by means of arbitration;
  • the PCIe unit 104 is configured to provide a PCIe interface for information interaction between the CPU and the DMA controller.
  • active and passive are relative to an external chip, that is, data transmission initiated by an external chip is referred to as “active”; data transmission initiated by the CPU is called It is “passive”; "uploading” and “sending” are relative to the CPU, that is, the data transmission direction is “upward” from the external chip to the CPU, and the data transmission direction is from the CPU to the external chip. "Issued”. Therefore, both the passive transmission unit 101 and the active transmission unit 102 in the DMA controller 10 need to complete data transmission in both the "up” and “send” directions.
  • the passive transmission unit 101 is specifically configured as follows:
  • the external chip source address preset by the CPU After receiving the uploading start command of the CPU configuration, the external chip source address preset by the CPU reads the data to be sent in the external chip memory to the passive uploading buffer according to the uplink data length preset by the CPU;
  • the CPU configuration of the uploading start command may be implemented by the CPU configuring the write start register in the passive transfer unit 101, for example, when the write start register is set by the CPU, indicating that the passive transfer unit 101 starts passively sending;
  • the preset uplink data length can be implemented by the CPU pre-configuring the uplink data length register in the passive transmission unit 101.
  • the unit of the register is 128 bits; the external chip source address preset by the CPU can pass through the CPU.
  • the external chip internal source address register in the passive transfer unit 101 is pre-configured to be implemented; the memory preset address of the CPU can be implemented by the CPU configuring the memory destination address register in the passive transfer unit 101; the passive transfer unit 101 will be passively sent.
  • the data to be sent in the cache is written to the memory preset address of the CPU.
  • the passive transmission unit 101 can move the data to be sent in the passive uplink buffer to the memory through the PCIe interface provided by the PCIe unit 104.
  • the passive transmission unit 101 notifies
  • the CPU write completion can set the upload completion register through the passive transfer unit 101, and issue it in the middle. , So that the CPU can send a complete passive transmission by reading the register unit 101 receives an interrupt or two ways, the determination process is complete passive feeding.
  • the passive transmission unit 101 is specifically configured to:
  • the memory source address preset by the CPU After receiving the sending start command of the CPU configuration, the memory source address preset by the CPU reads the data to be sent in the memory to the passive sending cache according to the length of the data sent by the CPU;
  • the CPU startup command of the CPU configuration may be implemented by the CPU configuring the read enable register in the passive transfer unit 101.
  • the passive transfer unit 101 starts to be passively sent;
  • the pre-configured data length can be implemented by the CPU pre-configuring the delivery length register in the passive transmission unit 101.
  • the unit of the length register is 32 bits; the memory source address preset by the CPU can be pre-processed by the CPU.
  • the memory source address register in the passive transmission unit 101 is configured to be implemented; the passive transmission unit 101 notifies the CPU that the completion of the delivery can be set by the passive transmission unit 101, and an interrupt is generated, so that the CPU can passively transmit by reading.
  • the completion register is received or the interrupt is received, and it is determined whether the passive delivery is completed.
  • the active transmission unit 102 is specifically configured to:
  • Receiving, by the CPU, the feature information of the BD table that is sent by the BD table after the initialization is completed, and the feature information of the BD table that is actively sent to the BD table includes: The first address and the end address of the BD table are stored; and the content of the BD item in the BD table may be: the valid indication of the BD item, the in-memory data block size corresponding to the BD item, and the in-memory data corresponding to the BD item. Starting address; and,
  • the active upload buffer satisfies the preset condition and the active transmission unit 102 saves itself
  • the BD item is read according to the first address and the end address stored in the BD table.
  • the data to be sent in the active upload buffer is transmitted to the in-memory data start address corresponding to the BD item, and the valid indication of the BD item is changed to 1, and the active transmission unit is The number of valid BD items saved by 102 itself is increased by one;
  • the next BD item of the BD item in the BD table is read according to the first address and the end address stored in the active delivery BD table.
  • the CPU may initialize the active uplink BD entry in the memory, and may include: setting the valid field val of the BD item to 0, the valid field may be an implementation form of the valid indication of the BD item, and the memory space pointed by the BD item.
  • the first address field indicates the in-memory data start address corresponding to the BD item, and the length field and the reserved field of the BD item do not need to be assigned.
  • the CPU also needs to open up the memory space pointed to by the BD entry, and the memory space pointed by each BD is not less than the maximum transmission data length. As shown in FIG. 2, the content of the BD item in the memory space is as shown on the right side of FIG.
  • the active upload cache may be a FIFO buffer, and the active upload cache satisfies the preset condition by one of two conditions: (1) the cached data in the FIFO reaches the configured length; (2) the data in the FIFO exceeds the set. The maximum waiting time.
  • the number of valid BD items held by the active transmission unit 102 itself may be a valid BD counter in the active transmission unit 102.
  • the active transmission unit 102 is further configured to: receive the read completion information sent by the CPU after reading the data to be sent in the in-memory data start address corresponding to the BD item, and save the active transmission unit 102 itself.
  • the number of valid BD items is reduced by one. Specifically, after reading one BD item, the CPU writes the valid field val field of the BD to 0, and writes 32'h1234_5678 to the read BD pulse register of the active transmission unit 102. After the active transmission unit 102 receives the pulse, it will Effective BD counter minus 1
  • the active transmission unit 102 is specifically configured to:
  • the BD item is actively delivered according to the first address and the end address of the BD item being actively delivered;
  • the CPU initializes the active delivery BD entry in the memory.
  • the initial content includes the message valid field val is 0, the BD item corresponding to the memory first address field is the memory address that the CPU stores the data to be delivered, and the BD item length field and the reserved field do not need to be assigned.
  • the CPU needs to send data, store the data in the memory address pointed to by the BD item, set the val of the BD item to 1, and write the data length into the length field of the BD item.
  • the active sending start command sent by the CPU may be implemented by the CPU writing 32'h1234_5678 to the write BD pulse number register of the active transfer unit 102. When the active transfer unit 102 determines that the write BD pulse number register is greater than 0, the memory is read.
  • the active transfer unit 102 then moves the data of the memory to the memory of the external chip according to the BD item returned by the read.
  • the active transmission unit 102 sends an active delivery completion response to the CPU. Specifically, the active transmission unit 102 sets the val signal of the BD item to 0 and sends an interrupt. Therefore, the CPU can determine whether the data pointed to by the current BD item is delivered by the val bit or interrupt of the BD item.
  • the arbitration mode can be configured, and can be configured as a polling scheduling or a strict priority scheduling.
  • the protocol layer part of the PCIe includes six groups of ports, the P message (no need to return the message that completes the completion response packet) is sent/received, and the NP message (request needs to return the message that completes the completion response packet) ) Transmission/reception, CPL message (complete completion response packet message) transmission/reception, developed entirely according to the PCIe protocol. Therefore, the control information interface between the DMA controller 10 and the CPU is realized by the PCIe interface provided by the PCIe unit 104.
  • the DMA controller 10 provided in this embodiment can support the data transmission in the active mode and the passive mode at the same time, and avoids the competition between the active mode and the passive mode by using the arbitration mode, which has strong versatility and saves.
  • the method is applied to a direct memory access DMA controller, and the method may include:
  • the DMA controller completes the data uploading and sending operation between the external chip and the CPU initiated by the CPU according to the transmission parameter configured by the CPU of the central processing unit;
  • the DMA controller completes the data uploading and sending operation between the external chip initiated by the external chip and the CPU by using the BD table and the data buffer space set by the CPU in the memory including at least one cache description BD item;
  • S303 The DMA controller avoids competition caused by data uploading and sending operations between the external chip and the CPU by means of arbitration;
  • the information interaction between the CPU and the DMA controller is performed through the PCIe interface.
  • the DMA controller completes the data upload operation between the external chip and the CPU initiated by the CPU according to the transmission parameters configured by the CPU, including:
  • the DMA controller After the DMA controller receives the CPU configuration of the send start command, the external core preset from the CPU
  • the source address of the chip reads the data to be sent in the external chip memory to the passive upload buffer according to the length of the data sent by the CPU;
  • the DMA controller writes the data to be sent in the passive uplink buffer to the memory destination address preset by the CPU;
  • the DMA controller notifies the CPU that the writing is completed after the data to be sent is completely written to the memory preset address of the CPU.
  • the DMA controller completes the data delivery operation between the external chip and the CPU initiated by the CPU according to the transmission parameters configured by the CPU, including:
  • the DMA controller After receiving the sending start command of the CPU configuration, the DMA controller reads the data to be sent in the memory to the passive sending buffer according to the data length of the CPU preset by the CPU.
  • the DMA controller writes the data to be sent in the passive delivery buffer into the destination address of the external chip memory preset by the CPU;
  • the DMA controller After the DMA controller completely writes the data to the destination address of the external chip memory preset by the CPU, the DMA controller notifies the CPU that the delivery is completed.
  • the DMA controller completes the data upload operation between the external chip and the CPU initiated by the external chip by the BD table and the data cache space of the CPU including the at least one cache description BD item set in the memory, including:
  • the DMA controller receives the feature information of the active BD table sent by the CPU after the initialization completes the BD table, and the feature information of the BD table that is actively sent to the BD table includes: Actively uploading the first address and the ending address of the BD table; and actively uploading the content of the BD item in the BD table may include: a valid indication of the BD item, an in-memory data block size corresponding to the BD item, and a corresponding BD item The starting address of the data in the memory;
  • the DMA controller receives the data to be sent sent by the external chip, and stores the data to be sent into the active upload cache in the DMA controller;
  • the DMA controller reads the BD item according to the first address and the end address stored in the BD table. ;
  • the DMA controller transfers the data to be sent in the cache to the in-memory data start address corresponding to the BD item, and changes the valid indication of the BD item to 1, and The number of valid BD items saved by the active transmission unit itself is increased by one;
  • the DMA controller reads the next BD item of the BD item in the BD table according to the first address and the end address stored in the BD table.
  • the method further comprises:
  • the DMA controller receives the read completion information sent by the CPU after reading the data to be sent in the data start address corresponding to the BD item, and reduces the number of valid BD items saved by the active transmission unit by one.
  • the DMA controller completes the data delivery operation between the external chip and the CPU initiated by the external chip by using the BD table and the data cache space of the CPU, which is set in the memory, including at least one cache description BD item, including:
  • the DMA controller receives the first address and the end address of the active delivery BD item sent by the CPU after the initialization completes the active delivery of the BD item;
  • the DMA controller After receiving the active sending start command sent by the CPU, the DMA controller actively releases the BD item according to the first address and the end address of the BD item.
  • the DMA controller transmits the data to be delivered in the memory space indicated by the BD item to the active delivery buffer, and transmits the data in the active delivery buffer to the memory of the external chip;
  • the DMA controller sends an active delivery completion response to the CPU.
  • the data transmission method provided in this embodiment can support the data transmission in the active mode and the passive mode at the same time, and avoids the competition between the active mode and the passive mode of the multi-path data by means of arbitration, and has high versatility and saves.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

Abstract

A DMA controller and a data transmission method. The DMA controller (10) comprises a passive transmission unit (101), an active transmission unit (102), a DMA scheduling unit (103), and a PCIe unit (104). The passive transmission unit (101) is configured to implement, according to a transmission parameter configured by the CPU, data submission and delivery operations that are triggered by a CPU and that are between an external chip and the CPU. The active transmission unit (102), configured to implement, by means of a BD table that is set by a CPU in a memory and that comprises at least one buffer description (BF) item as well as data buffer space, data submission and delivery operations that are triggered by the external chip and that are between the external chip and the CPU. The DMA scheduling unit (103), configured to avoid, in a manner of arbitration, contention caused by the data submission and delivery operations between the external chip and the CPU. The PCIe unit (104), configured to provide a PCIe interface for information interaction between the CPU and the DMA controller (10).

Description

一种直接内存存取DMA控制器及数据传输的方法Direct memory access DMA controller and data transmission method 技术领域Technical field
本发明涉及直接内存存取(DMA，Direct Memory Access)技术，尤其涉及一种DMA控制器及数据传输的方法。The present invention relates to Direct Memory Access (DMA) technology, and more particularly to a DMA controller and a method for data transmission.
背景技术Background technique
目前，直接内存存取DMA技术被广泛应用于芯片设计中，是一种不经过CPU而直接从内存存取数据的数据交换模式，是解决内存和外部芯片之间数据交互的重要技术。At present, direct memory access DMA technology is widely used in chip design. It is a data exchange mode that directly accesses data from memory without going through the CPU, and is an important technology for solving data interaction between memory and external chips.
DMA控制器可以将数据从一个地址空间搬移到另外一个地址空间，传输动作本身是由DMA控制器来实行和完成的，这样节省了CPU的数据总线带宽。而在具体的实现过程中，通常是针对不同应用场景来实现相应的DMA控制器，从而使得实现的DMA控制器的模式固定，不够灵活，导致多种数据传输模式无法共用DMA控制器，不利于节省芯片面积。The DMA controller can move data from one address space to another, and the transfer action itself is implemented and completed by the DMA controller, which saves the CPU's data bus bandwidth. In the specific implementation process, the corresponding DMA controller is usually implemented for different application scenarios, so that the implemented DMA controller mode is fixed and not flexible enough, so that multiple data transmission modes cannot share the DMA controller, which is not conducive to Save chip area.
发明内容Summary of the invention
有鉴于此，为解决现有技术存在的技术问题，本发明实施例提供一种DMA控制器及数据传输的方法。In view of this, in order to solve the technical problem existing in the prior art, an embodiment of the present invention provides a DMA controller and a data transmission method.
本发明实施例的技术方案是这样实现的：The technical solution of the embodiment of the present invention is implemented as follows:
第一方面，本发明实施例提供了一种DMA控制器，所述DMA控制器包括：被动传输单元、主动传输单元、DMA调度单元和快捷外部设备互连PCIe单元，其中，In a first aspect, an embodiment of the present invention provides a DMA controller, where the DMA controller includes: a passive transmission unit, an active transmission unit, a DMA scheduling unit, and a shortcut external device interconnection PCIe unit, where
所述被动传输单元，配置为根据中央处理器CPU配置的传输参数完成由所述CPU发起的所述外部芯片与所述CPU之间的数据上送和下发操作； The passive transmission unit is configured to complete a data uploading and sending operation between the external chip and the CPU initiated by the CPU according to a transmission parameter configured by a CPU of the CPU;
所述主动传输单元，配置为通过所述CPU在内存中设置的包括至少一个缓存描述BD项的BD表及数据缓存空间完成由外部芯片发起的所述外部芯片与所述CPU之间的数据上送和下发操作；The active transmission unit is configured to complete data between the external chip and the CPU initiated by an external chip by using a BD table and a data cache space that are set in the memory by the CPU and including at least one cache description BD item. Send and deliver operations;
所述DMA调度单元，配置为通过仲裁的方式避免所述外部芯片与所述CPU之间的数据上送和下发操作所引起的竞争；The DMA scheduling unit is configured to avoid contention caused by data uploading and sending operations between the external chip and the CPU by means of arbitration;
所述PCIe单元，配置为为所述CPU和所述DMA控制器之间的信息交互提供PCIe接口。The PCIe unit is configured to provide a PCIe interface for information interaction between the CPU and the DMA controller.
较佳地，所述被动传输单元，具体配置为：Preferably, the passive transmission unit is specifically configured to:
接收所述CPU配置的上送启动指令后，从所述CPU预置的外部芯片源地址按照所述CPU预置的上送数据长度将外部芯片存储器中的待上送数据读取至被动上送缓存；以及，After receiving the uploading start command of the CPU configuration, the external chip source address preset by the CPU reads the data to be sent in the external chip memory to be passively sent according to the uplink data length preset by the CPU. Cache; and,
将所述被动上送缓存中的待上送数据写入所述CPU预置的内存目的地址中；以及，Writing the data to be sent in the passive uplink buffer to the memory destination address preset by the CPU; and
当所述待上送数据完全写入所述CPU预置的内存目的地址后，通知所述CPU写入完成。After the data to be sent is completely written to the memory destination address preset by the CPU, the CPU is notified to complete the writing.
较佳地，所述被动传输单元，具体配置为：Preferably, the passive transmission unit is specifically configured to:
接收所述CPU配置的下发启动指令后，从所述CPU预置的内存源地址按照所述CPU预置的下发数据长度将所述内存中的待下发数据读取至被动下发缓存；以及，After receiving the sending start command of the CPU configuration, the memory source address preset by the CPU reads the to-be-distributed data in the memory to the passive sending buffer according to the issued data length preset by the CPU. ;as well as,
将所述被动下发缓存中的待下发数据写入所述CPU预置的外部芯片存储器的目的地址中；以及，Writing the data to be delivered in the passive sending buffer to the destination address of the external chip memory preset by the CPU; and
当所述待下发数据完全写入所述CPU预置的外部芯片存储器的目的地址后，通知所述CPU下发完成。After the data to be delivered is completely written to the destination address of the external chip memory preset by the CPU, the CPU is notified to complete the delivery.
较佳地，所述主动传输单元，具体配置为：Preferably, the active transmission unit is specifically configured as:
接收所述CPU在初始化完成主动上送BD表后发送的所述主动上送BD 表的特征信息；其中，所述主动上送BD表的特征信息包括：所述主动上送BD表中BD项的个数阈值，所述主动上送BD表存放的首地址和结束地址；所述主动上送BD表中BD项的内容包括：所述BD项的有效指示，所述BD项对应的内存中数据块大小及所述BD项对应的内存中数据起始地址；Receiving the active delivery BD sent by the CPU after initializing the completion of the active delivery of the BD table The feature information of the table, wherein the feature information of the active BD table includes: a threshold value of the number of BD items in the BD table, and a first address and an end address stored in the BD table; The content of the BD item in the BD table is: a valid indication of the BD item, an in-memory data block size corresponding to the BD item, and an in-memory data start address corresponding to the BD item;
以及，接收外部芯片发送的待上送数据，并将所述待上送数据存入所述DMA控制器中的主动上送缓存；And receiving the data to be sent sent by the external chip, and storing the data to be sent into the active upload cache in the DMA controller;
以及，当所述主动上送缓存满足预设条件时且所述主动传输单元自身保存的有效BD项数小于所述BD项的个数阈值时，根据所述主动上送BD表存放的首地址和结束地址读取所述BD项；And when the active uplink buffer meets the preset condition and the number of valid BD items saved by the active transmission unit itself is less than the threshold number of the BD item, according to the first address stored in the active delivery BD table. And reading the BD item with the end address;
以及，当所述BD项的有效指示为0时，将所述主动上送缓存中的待上送数据传输至所述BD项对应的内存中数据起始地址，并将所述BD项的有效指示更改为1，且将所述主动传输单元自身保存的有效BD项数加一；And when the valid indication of the BD item is 0, the data to be sent in the active uplink buffer is transmitted to an in-memory data start address corresponding to the BD item, and the BD item is valid. The indication is changed to 1, and the number of valid BD items saved by the active transmission unit itself is increased by one;
以及，根据所述主动上送BD表存放的首地址和结束地址读取所述BD项在所述BD表中的下一个BD项。And reading the next BD item of the BD item in the BD table according to the first address and the end address stored in the active delivery BD table.
较佳地，所述主动传输单元还配置为：接收所述CPU在读取完所述BD项对应的内存中数据起始地址中的待上送数据后发送的读取完毕信息，并将所述主动传输单元自身保存的有效BD项数减一。Preferably, the active transmission unit is further configured to: receive the read completion information sent by the CPU after reading the data to be sent in the in-memory data start address corresponding to the BD item, and The number of valid BD items saved by the active transmission unit itself is reduced by one.
较佳地，所述主动传输单元，具体配置为：Preferably, the active transmission unit is specifically configured as:
接收所述CPU在初始化完成主动下发BD项后发送的所述主动下发BD项的首地址和结束地址；以及，Receiving, by the CPU, a first address and an end address of the active delivery BD item that are sent after the initial completion of the initial delivery of the BD item by the CPU;
接收所述CPU发送的主动下发起始指令后，根据所述主动下发BD项的首地址和结束地址读取所述主动下发BD项；以及，After receiving the active delivery start command sent by the CPU, reading the active delivery BD item according to the first address and the end address of the active delivery BD item; and
根据所述主动下发BD项指示的内存空间中的待下发数据传输至主动下发缓存，并将所述主动下发缓存中的数据传输至所述外部芯片的存储器；以及， Transmitting the data to be delivered in the memory space indicated by the active delivery of the BD item to the active delivery buffer, and transmitting the data in the active delivery buffer to the memory of the external chip;
向所述CPU发送主动下发完成响应。Sending an active delivery completion response to the CPU.
第二方面，本发明实施例提供了一种数据传输的方法，所述方法应用于一DMA控制器，所述方法包括：In a second aspect, an embodiment of the present invention provides a data transmission method, where the method is applied to a DMA controller, and the method includes:
所述DMA控制器根据中央处理器CPU配置的传输参数完成由所述CPU发起的所述外部芯片与所述CPU之间的数据上送和下发操作；Determining, by the DMA controller, a data uploading and sending operation between the external chip and the CPU initiated by the CPU according to a transmission parameter configured by a CPU of the CPU;
所述DMA控制器通过所述CPU在内存中设置的包括至少一个缓存描述BD项的BD表及数据缓存空间完成由外部芯片发起的所述外部芯片与所述CPU之间的数据上送和下发操作；The DMA controller performs data uploading and sending between the external chip and the CPU initiated by an external chip by using a BD table and a data cache space of the CPU, which is set in the memory, including at least one cache description BD item. Send operation
所述DMA控制器通过仲裁的方式避免所述外部芯片与所述CPU之间的数据上送和下发操作所引起的竞争，其中，所述CPU和所述DMA控制器之间的信息交互通过PCIe接口进行。The DMA controller avoids competition caused by data uploading and sending operations between the external chip and the CPU by means of arbitration, wherein information interaction between the CPU and the DMA controller is passed The PCIe interface is performed.
较佳地，所述DMA控制器根据CPU配置的传输参数完成由所述CPU发起的所述外部芯片与所述CPU之间的数据上送操作，包括：Preferably, the DMA controller completes the data upload operation between the external chip and the CPU initiated by the CPU according to the transmission parameter configured by the CPU, including:
所述DMA控制器接收所述CPU配置的上送启动指令后，从所述CPU预置的外部芯片源地址按照所述CPU预置的上送数据长度将外部芯片存储器中的待上送数据读取至被动上送缓存；After the DMA controller receives the uploading instruction of the CPU configuration, the external chip source address preset by the CPU reads the data to be sent in the external chip memory according to the uplink data length preset by the CPU. Take the passive send cache;
所述DMA控制器将所述被动上送缓存中的待上送数据写入所述CPU预置的内存目的地址中；The DMA controller writes the data to be sent in the passive uplink buffer to the memory destination address preset by the CPU;
所述DMA控制器当所述待上送数据完全写入所述CPU预置的内存目的地址后，通知所述CPU写入完成。The DMA controller notifies the CPU that the writing is completed after the data to be sent is completely written to the memory destination address preset by the CPU.
较佳地，所述DMA控制器根据CPU配置的传输参数完成由所述CPU发起的所述外部芯片与所述CPU之间的数据下发操作，包括：Preferably, the DMA controller completes the data delivery operation between the external chip and the CPU initiated by the CPU according to the transmission parameter configured by the CPU, including:
所述DMA控制器接收所述CPU配置的下发启动指令后，从所述CPU预置的内存源地址按照所述CPU预置的下发数据长度将所述内存中的待下发数据读取至被动下发缓存； After the DMA controller receives the issued start command of the CPU, the memory source address preset by the CPU reads the data to be sent in the memory according to the length of the data sent by the CPU. To passively send the cache;
所述DMA控制器将所述被动下发缓存中的待下发数据写入所述CPU预置的外部芯片存储器的目的地址中；Writing, by the DMA controller, the data to be sent in the passive sending buffer to the destination address of the external chip memory preset by the CPU;
所述DMA控制器当所述待下发数据完全写入所述CPU预置的外部芯片存储器的目的地址后，通知所述CPU下发完成。The DMA controller notifies the CPU that the delivery is completed after the data to be sent is completely written to the destination address of the external chip memory preset by the CPU.
较佳地，所述DMA控制器通过所述CPU在内存中设置的包括至少一个缓存描述BD项的BD表及数据缓存空间完成由外部芯片发起的所述外部芯片与所述CPU之间的数据上送操作，包括：Preferably, the DMA controller completes data between the external chip and the CPU initiated by an external chip by using a BD table and a data cache space set by the CPU in the memory including at least one cache description BD item. Upload operation, including:
所述DMA控制器接收所述CPU在初始化完成主动上送BD表后发送的所述主动上送BD表的特征信息；其中，所述主动上送BD表的特征信息包括：所述主动上送BD表中BD项的个数阈值，所述主动上送BD表存放的首地址和结束地址；所述主动上送BD表中BD项的内容包括：所述BD项的有效指示，所述BD项对应的内存中数据块大小，所述BD项对应的内存中数据起始地址；The DMA controller receives the feature information of the active delivery BD table that is sent by the CPU after the initialization completes the active delivery of the BD table, where the feature information of the active delivery BD table includes: the active delivery a threshold of the number of BD items in the BD table, the first address and the end address stored in the BD table; the content of the BD item in the active delivery BD table includes: a valid indication of the BD item, the BD The in-memory data block size corresponding to the item, and the in-memory data start address corresponding to the BD item;
所述DMA控制器接收外部芯片发送的待上送数据，并将所述待上送数据存入所述DMA控制器中的主动上送缓存；The DMA controller receives the data to be sent sent by the external chip, and stores the data to be sent into the active upload cache in the DMA controller;
当所述主动上送缓存满足预设条件时且所述主动传输单元自身保存的有效BD项数小于所述BD项的个数阈值时，所述DMA控制器根据所述主动上送BD表存放的首地址和结束地址读取所述BD项；When the active uplink buffer meets the preset condition and the number of valid BD items saved by the active transmission unit itself is less than the threshold number of the BD item, the DMA controller stores the BD table according to the active delivery The first address and the end address read the BD item;
当所述BD项的有效指示为0时，所述DMA控制器将所述主动上送缓存中的待上送数据传输至所述BD项对应的内存中数据起始地址，并将所述BD项的有效指示更改为1，且将所述主动传输单元自身保存的有效BD项数加一；When the valid indication of the BD item is 0, the DMA controller transmits the data to be sent in the active uplink buffer to the in-memory data start address corresponding to the BD item, and the BD is The effective indication of the item is changed to 1, and the number of valid BD items saved by the active transmission unit itself is increased by one;
所述DMA控制器根据所述主动上送BD表存放的首地址和结束地址读取所述BD项在所述BD表中的下一个BD项。The DMA controller reads the next BD item of the BD item in the BD table according to the first address and the end address stored in the active delivery BD table.
较佳地，所述方法还包括： Preferably, the method further includes:
所述DMA控制器接收所述CPU在读取完所述BD项对应的内存中数据起始地址中的待上送数据后发送的读取完毕信息，并将所述主动传输单元自身保存的有效BD项数减一。Receiving, by the DMA controller, the read completion information sent by the CPU after reading the data to be sent in the in-memory data start address corresponding to the BD item, and saving the active transmission unit itself The number of BD items is reduced by one.
较佳地，所述DMA控制器通过所述CPU在内存中设置的包括至少一个缓存描述BD项的BD表及数据缓存空间完成由外部芯片发起的所述外部芯片与所述CPU之间的数据下发操作，包括：Preferably, the DMA controller completes data between the external chip and the CPU initiated by an external chip by using a BD table and a data cache space set by the CPU in the memory including at least one cache description BD item. Delivery operations, including:
所述DMA控制器接收所述CPU在初始化完成主动下发BD项后发送的所述主动下发BD项的首地址和结束地址；Receiving, by the DMA controller, a first address and an end address of the active delivery BD item that are sent by the CPU after the initial completion of the initial delivery of the BD item;
所述DMA控制器接收所述CPU发送的主动下发起始指令后，根据所述主动下发BD项的首地址和结束地址读取所述主动下发BD项；After receiving the active delivery start command sent by the CPU, the DMA controller reads the active delivery BD item according to the first address and the end address of the active delivery BD item;
所述DMA控制器根据所述主动下发BD项指示的内存空间中的待下发数据传输至主动下发缓存，并将所述主动下发缓存中的数据传输至所述外部芯片的存储器；The DMA controller transmits the data to be delivered in the memory space indicated by the active delivery BD item to the active delivery buffer, and transmits the data in the active delivery buffer to the memory of the external chip;
所述DMA控制器向所述CPU发送主动下发完成响应。The DMA controller sends an active delivery completion response to the CPU.
本发明实施例提供了一种DMA控制器及数据传输的方法，通过一种适用于不同应用场景的DMA控制器来使得多种数据传输模式均能够共用该DMA控制器，通用性强，节省了CPU与外部芯片的读写数据时间，而且能够节省芯片面积。Embodiments of the present invention provide a DMA controller and a data transmission method, which enable a plurality of data transmission modes to share the DMA controller through a DMA controller suitable for different application scenarios, which is highly versatile and saves CPU and external chip read and write data time, and can save chip area.
附图说明DRAWINGS
图1为本发明实施例提供的一种DMA控制器的结构示意图；1 is a schematic structural diagram of a DMA controller according to an embodiment of the present invention;
图2为本发明实施例提供的一种内存空间的示意图；2 is a schematic diagram of a memory space according to an embodiment of the present invention;
图3为本发明实施例提供的一种数据传输的方法的流程示意图。FIG. 3 is a schematic flowchart diagram of a method for data transmission according to an embodiment of the present invention.
具体实施方式detailed description
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进 行清楚、完整地描述。The technical solution in the embodiment of the present invention will be further described below with reference to the accompanying drawings in the embodiments of the present invention. Clearly and completely described.
参见图1，其示出了本发明实施例提供的一种DMA控制器10的结构，该DMA控制器10可以包括：被动传输单元101、主动传输单元102、DMA调度单元103和快捷外部设备互连(PCIe，Peripheral Component Interconnect Express)单元104，其中，Referring to FIG. 1, a structure of a DMA controller 10 according to an embodiment of the present invention is shown. The DMA controller 10 may include: a passive transmission unit 101, an active transmission unit 102, a DMA scheduling unit 103, and a shortcut external device. a PCIe (Peripheral Component Interconnect Express) unit 104, wherein
被动传输单元101，配置为根据CPU配置的传输参数完成由CPU发起的外部芯片与CPU之间的数据上送和下发操作；The passive transmission unit 101 is configured to complete data uploading and sending operations between the external chip and the CPU initiated by the CPU according to the transmission parameters configured by the CPU;
主动传输单元102，配置为通过中央处理器CPU在内存中设置的包括至少一个缓存描述(BD，Buffer Descriptor)项的BD表及数据缓存空间完成由外部芯片发起的外部芯片与CPU之间的数据上送和下发操作；The active transmission unit 102 is configured to complete data between the external chip and the CPU initiated by the external chip by using a BD table and a data cache space that are set in the memory by the central processing unit CPU and including at least one BD (Buffer Descriptor) item. Send and send operations;
DMA调度单元103，配置为通过仲裁的方式避免外部芯片与CPU之间的数据上送和下发操作所引起的竞争；The DMA scheduling unit 103 is configured to avoid competition caused by data uploading and sending operations between the external chip and the CPU by means of arbitration;
PCIe单元104，配置为为CPU和DMA控制器之间的信息交互提供PCIe接口。The PCIe unit 104 is configured to provide a PCIe interface for information interaction between the CPU and the DMA controller.
可以理解地，DMA控制器10中为了实现各单元的功能，还会相应地在各单元中设置寄存器及缓存等器件，而这些器件并不是本实施例技术方案的主要内容，因此，这些寄存器和缓存仅在后续的技术方案描述中的相应部分进行描述。It is to be understood that, in order to realize the functions of the respective units in the DMA controller 10, devices such as registers and buffers are respectively disposed in the respective units, and these devices are not the main contents of the technical solutions of the embodiment, and therefore, these registers and The cache is described only in the corresponding part of the description of the subsequent technical solution.
需要说明的是，在本实施例中，“主动”和“被动”是相对于外部芯片而言的，即：由外部芯片发起的数据传输称之为“主动”；由CPU发起的数据传输称之为“被动”；“上送”和“下发”是相对于CPU而言的，即：数据传输方向为外部芯片至CPU的为“上送”，数据传输方向为CPU至外部芯片的为“下发”。所以，DMA控制器10中的被动传输单元101和主动传输单元102均需要完成“上送”和“下发”这两个方向的数据传输。It should be noted that, in this embodiment, "active" and "passive" are relative to an external chip, that is, data transmission initiated by an external chip is referred to as "active"; data transmission initiated by the CPU is called It is "passive"; "uploading" and "sending" are relative to the CPU, that is, the data transmission direction is "upward" from the external chip to the CPU, and the data transmission direction is from the CPU to the external chip. "Issued". Therefore, both the passive transmission unit 101 and the active transmission unit 102 in the DMA controller 10 need to complete data transmission in both the "up" and "send" directions.
示例性地，为了完成由CPU发起的外部芯片与CPU之间的数据上送操 作，被动传输单元101具体配置为：Illustratively, in order to complete the data upload operation between the external chip and the CPU initiated by the CPU The passive transmission unit 101 is specifically configured as follows:
接收CPU配置的上送启动指令后，从CPU预置的外部芯片源地址按照CPU预置的上送数据长度将外部芯片存储器中的待上送数据读取至被动上送缓存；After receiving the uploading start command of the CPU configuration, the external chip source address preset by the CPU reads the data to be sent in the external chip memory to the passive uploading buffer according to the uplink data length preset by the CPU;
以及，将被动上送缓存中的待上送数据写入CPU预置的内存目的地址中；And writing the data to be sent in the passive uplink buffer to the memory destination address preset by the CPU;
以及，当待上送数据完全写入CPU预置的内存目的地址后，通知CPU写入完成。And, when the data to be sent is completely written into the memory destination address preset by the CPU, the CPU is notified to complete the writing.
需要说明的是，上述被动传输单元101的具体用途可以应用于CPU想要获取外部芯片中的某一块数据的场景；It should be noted that the specific use of the foregoing passive transmission unit 101 can be applied to a scenario in which the CPU wants to acquire a certain block of data in an external chip;
具体地，CPU配置的上送启动指令可以通过CPU配置被动传输单元101中的写启动寄存器来实现，例如，当写启动寄存器被CPU置位时，表示被动传输单元101开始进行被动上送；CPU预置的上送数据长度可以通过CPU预先配置被动传输单元101中的上送数据长度寄存器来实现，在本实施例中，该寄存器的单位为128bit；CPU预置的外部芯片源地址可以通过CPU预先配置被动传输单元101中的外部芯片片内源地址寄存器来实现；CPU预置的内存目的地址可以通过CPU配置被动传输单元101中的内存目的地址寄存器来实现；被动传输单元101将被动上送缓存中的待上送数据写入CPU预置的内存目的地址可以由被动传输单元101通过PCIe单元104提供的PCIe接口将被动上送缓存中的待上送数据向内存搬移；被动传输单元101通知CPU写入完成可以通过被动传输单元101将上送完成寄存器置位，并发出中断，从而使得CPU可以通过读取被动传输单元101中的上送完成寄存器或接收中断两种方式，判断被动上送过程完成。Specifically, the CPU configuration of the uploading start command may be implemented by the CPU configuring the write start register in the passive transfer unit 101, for example, when the write start register is set by the CPU, indicating that the passive transfer unit 101 starts passively sending; The preset uplink data length can be implemented by the CPU pre-configuring the uplink data length register in the passive transmission unit 101. In this embodiment, the unit of the register is 128 bits; the external chip source address preset by the CPU can pass through the CPU. The external chip internal source address register in the passive transfer unit 101 is pre-configured to be implemented; the memory preset address of the CPU can be implemented by the CPU configuring the memory destination address register in the passive transfer unit 101; the passive transfer unit 101 will be passively sent. The data to be sent in the cache is written to the memory preset address of the CPU. The passive transmission unit 101 can move the data to be sent in the passive uplink buffer to the memory through the PCIe interface provided by the PCIe unit 104. The passive transmission unit 101 notifies The CPU write completion can set the upload completion register through the passive transfer unit 101, and issue it in the middle. , So that the CPU can send a complete passive transmission by reading the register unit 101 receives an interrupt or two ways, the determination process is complete passive feeding.
示例性地，为了完成由CPU发起的外部芯片与CPU之间的数据下发操作，被动传输单元101，具体配置为： Illustratively, in order to complete the data delivery operation between the external chip and the CPU initiated by the CPU, the passive transmission unit 101 is specifically configured to:
接收CPU配置的下发启动指令后，从CPU预置的内存源地址按照CPU预置的下发数据长度将内存中的待下发数据读取至被动下发缓存；After receiving the sending start command of the CPU configuration, the memory source address preset by the CPU reads the data to be sent in the memory to the passive sending cache according to the length of the data sent by the CPU;
以及，将被动下发缓存中的待下发数据写入CPU预置的外部芯片存储器的目的地址中；And writing the data to be sent in the passive sending buffer to the destination address of the external chip memory preset by the CPU;
以及，当待下发数据完全写入CPU预置的外部芯片存储器的目的地址后，通知CPU下发完成。And, when the data to be sent is completely written to the destination address of the external chip memory preset by the CPU, the CPU is notified to complete the delivery.
具体地，CPU配置的下发启动指令可以通过CPU配置被动传输单元101中的读启动寄存器来实现，例如，当读启动寄存器被CPU置位时，表示被动传输单元101开始进行被动下发；CPU预置的下发数据长度可以通过CPU预先配置被动传输单元101中的下发长度寄存器来实现，在本实施例中，下发长度寄存器的单位32bit；CPU预置的内存源地址可以通过CPU预先配置被动传输单元101中的内存源地址寄存器来实现；被动传输单元101通知CPU下发完成可以通过被动传输单元101置位下发完成寄存器，并发出中断来实现，从而使得CPU可以通过读被动传输单元101中的下发完成寄存器或者接收中断的方式，判断被动下发是否完成。Specifically, the CPU startup command of the CPU configuration may be implemented by the CPU configuring the read enable register in the passive transfer unit 101. For example, when the read enable register is set by the CPU, the passive transfer unit 101 starts to be passively sent; The pre-configured data length can be implemented by the CPU pre-configuring the delivery length register in the passive transmission unit 101. In this embodiment, the unit of the length register is 32 bits; the memory source address preset by the CPU can be pre-processed by the CPU. The memory source address register in the passive transmission unit 101 is configured to be implemented; the passive transmission unit 101 notifies the CPU that the completion of the delivery can be set by the passive transmission unit 101, and an interrupt is generated, so that the CPU can passively transmit by reading. In the unit 101, the completion register is received or the interrupt is received, and it is determined whether the passive delivery is completed.
示例性地，为了完成由外部芯片发起的外部芯片与CPU之间的数据上送操作，主动传输单元102，具体配置为：Exemplarily, in order to complete the data upload operation between the external chip and the CPU initiated by the external chip, the active transmission unit 102 is specifically configured to:
接收CPU在初始化完成主动上送BD表后发送的主动上送BD表的特征信息；其中，主动上送BD表的特征信息包括：主动上送BD表中BD项的个数阈值，主动上送BD表存放的首地址和结束地址；而主动上送BD表中的BD项内容可以包括：该BD项的有效指示，该BD项对应的内存中数据块大小及该BD项对应的内存中数据起始地址；以及，Receiving, by the CPU, the feature information of the BD table that is sent by the BD table after the initialization is completed, and the feature information of the BD table that is actively sent to the BD table includes: The first address and the end address of the BD table are stored; and the content of the BD item in the BD table may be: the valid indication of the BD item, the in-memory data block size corresponding to the BD item, and the in-memory data corresponding to the BD item. Starting address; and,
接收外部芯片发送的待上送数据，并将待上送数据存入DMA控制器10中的主动上送缓存；Receiving data to be sent sent by the external chip, and storing the data to be sent into the active upload cache in the DMA controller 10;
当主动上送缓存满足预设条件时且主动传输单元102自身保存的有效 BD项数小于BD项的个数阈值时，根据主动上送BD表存放的首地址和结束地址读取BD项；When the active upload buffer satisfies the preset condition and the active transmission unit 102 saves itself When the number of BD items is less than the threshold number of the BD item, the BD item is read according to the first address and the end address stored in the BD table.
当BD项的有效指示为0时，将主动上送缓存中的待上送数据传输至BD项对应的内存中数据起始地址，并将BD项的有效指示更改为1，且将主动传输单元102自身保存的有效BD项数加一；When the valid indication of the BD item is 0, the data to be sent in the active upload buffer is transmitted to the in-memory data start address corresponding to the BD item, and the valid indication of the BD item is changed to 1, and the active transmission unit is The number of valid BD items saved by 102 itself is increased by one;
根据主动上送BD表存放的首地址和结束地址读取BD项在BD表中的下一个BD项。The next BD item of the BD item in the BD table is read according to the first address and the end address stored in the active delivery BD table.
具体地，CPU可以初始化内存中的主动上送BD表项可以包括将BD项的有效字段val为0，该有效字段可以是BD项的有效指示的一种实现形式、BD项指向的内存空间的首地址字段表示BD项对应的内存中数据起始地址，而BD项的长度字段和保留字段不需要赋值。同时CPU还需要开辟BD表项指向的内存空间，每个BD指向的内存空间不小于最大传输数据长度。如图2所示，内存空间中的BD项的内容如图2右边所示，图2左边中交叉斜线表示的BD项BD_0在内存中指向的空间为交叉斜线所示的Bd_dat0至Bd_datk-1，其中，k表示数据长度；相对应地，方格阴影表示的BD项BD_1在内存中指向的空间为方格阴影所示的Bd_dat0至Bd_datk-1，其中，k表示数据长度。主动上送缓存可以是一个FIFO中缓存，而主动上送缓存满足预设条件可以是如下两个条件之一：(1)FIFO中的缓存数据达到配置长度；(2)FIFO中的数据超过设定的最大等待时间。主动传输单元102自身保存的有效BD项数可以是主动传输单元102中的有效BD计数器。Specifically, the CPU may initialize the active uplink BD entry in the memory, and may include: setting the valid field val of the BD item to 0, the valid field may be an implementation form of the valid indication of the BD item, and the memory space pointed by the BD item. The first address field indicates the in-memory data start address corresponding to the BD item, and the length field and the reserved field of the BD item do not need to be assigned. At the same time, the CPU also needs to open up the memory space pointed to by the BD entry, and the memory space pointed by each BD is not less than the maximum transmission data length. As shown in FIG. 2, the content of the BD item in the memory space is as shown on the right side of FIG. 2, and the space indicated by the BD item BD_0 indicated by the cross slash in the left side of FIG. 2 is Bd_dat0 to Bd_datk indicated by a cross slash. 1, where k represents the data length; correspondingly, the space pointed by the BD item BD_1 indicated by the square hatching in the memory is Bd_dat0 to Bd_datk-1 indicated by the square shading, where k represents the data length. The active upload cache may be a FIFO buffer, and the active upload cache satisfies the preset condition by one of two conditions: (1) the cached data in the FIFO reaches the configured length; (2) the data in the FIFO exceeds the set. The maximum waiting time. The number of valid BD items held by the active transmission unit 102 itself may be a valid BD counter in the active transmission unit 102.
较佳地，主动传输单元102还配置为：接收CPU在读取完BD项对应的内存中数据起始地址中的待上送数据后发送的读取完毕信息，并将主动传输单元102自身保存的有效BD项数减一。具体地，CPU每次读取一个BD项后，将BD的有效字段val字段写0，并向主动传输单元102的读BD脉冲寄存器写32’h1234_5678，主动传输单元102收到脉冲后，会将有效 BD计数器减1Preferably, the active transmission unit 102 is further configured to: receive the read completion information sent by the CPU after reading the data to be sent in the in-memory data start address corresponding to the BD item, and save the active transmission unit 102 itself. The number of valid BD items is reduced by one. Specifically, after reading one BD item, the CPU writes the valid field val field of the BD to 0, and writes 32'h1234_5678 to the read BD pulse register of the active transmission unit 102. After the active transmission unit 102 receives the pulse, it will Effective BD counter minus 1
示例性地，为了完成由外部芯片发起的外部芯片与CPU之间的数据下发操作，主动传输单元102，具体配置为：Illustratively, in order to complete the data delivery operation between the external chip and the CPU initiated by the external chip, the active transmission unit 102 is specifically configured to:
接收CPU在初始化完成主动下发BD项后发送的主动下发BD项的首地址和结束地址；Receiving a first address and an end address of an active delivery BD item sent by the CPU after the initial completion of the initial delivery of the BD item;
以及，接收CPU发送的主动下发起始指令后，根据主动下发BD项的首地址和结束地址读取主动下发BD项；And, after receiving the active sending start command sent by the CPU, the BD item is actively delivered according to the first address and the end address of the BD item being actively delivered;
以及，根据主动下发BD项指示的内存空间中的待下发数据传输至主动下发缓存，并将主动下发缓存中的数据传输至外部芯片的存储器；And transmitting the data to be delivered in the memory space indicated by the BD item to the active delivery buffer, and transmitting the data in the active delivery buffer to the memory of the external chip;
以及，向CPU发送主动下发完成响应。And sending an active delivery completion response to the CPU.
具体地，CPU初始化内存中的主动下发BD表项。初始的内容包括报文有效字段val为0，BD项对应内存首地址字段为CPU将这个待下发数据存储的内存地址，BD项长度字段和保留字段不需要赋值。CPU需要下发数据时，将数据存放到BD项指向的内存地址，并将BD项的val置1，将数据长度写入BD项的长度字段。CPU发送的主动下发起始指令可以通过CPU向主动传输单元102的写BD脉冲个数寄存器写32’h1234_5678来实现，当主动传输单元102判断写BD脉冲个数寄存器大于0，则读取内存中的BD项，并将写BD脉冲个数寄存器减1。接着主动传输单元102根据读返回的BD项，将内存的数据搬移到外部芯片的存储器。主动传输单元102向CPU发送主动下发完成响应具体可以是主动传输单元102将BD项的val信号置0，并发送中断。从而使得CPU可以通过BD项的val位或中断，来判断当前BD项指向的数据是否被下发完成。Specifically, the CPU initializes the active delivery BD entry in the memory. The initial content includes the message valid field val is 0, the BD item corresponding to the memory first address field is the memory address that the CPU stores the data to be delivered, and the BD item length field and the reserved field do not need to be assigned. When the CPU needs to send data, store the data in the memory address pointed to by the BD item, set the val of the BD item to 1, and write the data length into the length field of the BD item. The active sending start command sent by the CPU may be implemented by the CPU writing 32'h1234_5678 to the write BD pulse number register of the active transfer unit 102. When the active transfer unit 102 determines that the write BD pulse number register is greater than 0, the memory is read. The BD entry, and decrement the write BD pulse count register by one. The active transfer unit 102 then moves the data of the memory to the memory of the external chip according to the BD item returned by the read. The active transmission unit 102 sends an active delivery completion response to the CPU. Specifically, the active transmission unit 102 sets the val signal of the BD item to 0 and sends an interrupt. Therefore, the CPU can determine whether the data pointed to by the current BD item is delivered by the val bit or interrupt of the BD item.
需要说明的是，由于PCIe接口协议中，只存在一个读接口，一个写接口和一个读返回接口，因此，上述被动传输单元101和主动传输单元102在进行数据传输过程中，频繁的跟CPU交互，进行接收和发送，从而难免 出现冲突。于是DMA调度单元103的作用就是将这些存在竞争的操作进行仲裁，仲裁的方式是可以配置的，既可以配置为轮询调度又可以配置为严格优先级调度。It should be noted that, in the PCIe interface protocol, there is only one read interface, one write interface and one read return interface. Therefore, the passive transmission unit 101 and the active transmission unit 102 frequently interact with the CPU during data transmission. , receiving and sending, which is inevitable There is a conflict. Then, the DMA scheduling unit 103 functions to arbitrate these contention operations. The arbitration mode can be configured, and can be configured as a polling scheduling or a strict priority scheduling.
还需要说明的是，由于PCIe的协议层部分包括6组端口，P报文(不需要返回完成completion响应包的报文)发送/接收，NP报文(请求需要返回完成completion响应包的报文)发送/接收，CPL报文(完成completion响应包报文)发送/接收，完全根据PCIe协议开发。因此，DMA控制器10与CPU之间的控制信息接口通过PCIe单元104提供的PCIe接口来实现。It should be noted that, because the protocol layer part of the PCIe includes six groups of ports, the P message (no need to return the message that completes the completion response packet) is sent/received, and the NP message (request needs to return the message that completes the completion response packet) ) Transmission/reception, CPL message (complete completion response packet message) transmission/reception, developed entirely according to the PCIe protocol. Therefore, the control information interface between the DMA controller 10 and the CPU is realized by the PCIe interface provided by the PCIe unit 104.
本实施例提供的DMA控制器10，可以同时支持主动方式和被动方式的数据传输，并且通过仲裁的方式避免了主动方式和被动方式的多路数据之间的竞争现象，通用性强，节省了CPU与外部芯片的读写数据时间。The DMA controller 10 provided in this embodiment can support the data transmission in the active mode and the passive mode at the same time, and avoids the competition between the active mode and the passive mode by using the arbitration mode, which has strong versatility and saves. The read and write data time of the CPU and the external chip.
参见图3，其示出了本发明实施例提供的一种数据传输的方法流程，该方法应用于一直接内存存取DMA控制器，该方法可以包括：Referring to FIG. 3, a method flow of data transmission according to an embodiment of the present invention is shown. The method is applied to a direct memory access DMA controller, and the method may include:
S301：DMA控制器根据中央处理器CPU配置的传输参数完成由CPU发起的外部芯片与CPU之间的数据上送和下发操作；S301: The DMA controller completes the data uploading and sending operation between the external chip and the CPU initiated by the CPU according to the transmission parameter configured by the CPU of the central processing unit;
S302：DMA控制器通过CPU在内存中设置的包括至少一个缓存描述BD项的BD表及数据缓存空间完成由外部芯片发起的外部芯片与CPU之间的数据上送和下发操作；S302: The DMA controller completes the data uploading and sending operation between the external chip initiated by the external chip and the CPU by using the BD table and the data buffer space set by the CPU in the memory including at least one cache description BD item;
S303：DMA控制器通过仲裁的方式避免外部芯片与CPU之间的数据上送和下发操作所引起的竞争；S303: The DMA controller avoids competition caused by data uploading and sending operations between the external chip and the CPU by means of arbitration;
在本实施例中，CPU和DMA控制器之间的信息交互通过PCIe接口进行。In this embodiment, the information interaction between the CPU and the DMA controller is performed through the PCIe interface.
示例性地，DMA控制器根据CPU配置的传输参数完成由CPU发起的外部芯片与CPU之间的数据上送操作，包括：Illustratively, the DMA controller completes the data upload operation between the external chip and the CPU initiated by the CPU according to the transmission parameters configured by the CPU, including:
DMA控制器接收CPU配置的上送启动指令后，从CPU预置的外部芯 片源地址按照CPU预置的上送数据长度将外部芯片存储器中的待上送数据读取至被动上送缓存；After the DMA controller receives the CPU configuration of the send start command, the external core preset from the CPU The source address of the chip reads the data to be sent in the external chip memory to the passive upload buffer according to the length of the data sent by the CPU;
DMA控制器将被动上送缓存中的待上送数据写入CPU预置的内存目的地址中；The DMA controller writes the data to be sent in the passive uplink buffer to the memory destination address preset by the CPU;
DMA控制器当待上送数据完全写入CPU预置的内存目的地址后，通知CPU写入完成。The DMA controller notifies the CPU that the writing is completed after the data to be sent is completely written to the memory preset address of the CPU.
示例性地，DMA控制器根据CPU配置的传输参数完成由CPU发起的外部芯片与CPU之间的数据下发操作，包括：Illustratively, the DMA controller completes the data delivery operation between the external chip and the CPU initiated by the CPU according to the transmission parameters configured by the CPU, including:
DMA控制器接收CPU配置的下发启动指令后，从CPU预置的内存源地址按照CPU预置的下发数据长度将内存中的待下发数据读取至被动下发缓存；After receiving the sending start command of the CPU configuration, the DMA controller reads the data to be sent in the memory to the passive sending buffer according to the data length of the CPU preset by the CPU.
DMA控制器将被动下发缓存中的待下发数据写入CPU预置的外部芯片存储器的目的地址中；The DMA controller writes the data to be sent in the passive delivery buffer into the destination address of the external chip memory preset by the CPU;
DMA控制器当待下发数据完全写入CPU预置的外部芯片存储器的目的地址后，通知CPU下发完成。After the DMA controller completely writes the data to the destination address of the external chip memory preset by the CPU, the DMA controller notifies the CPU that the delivery is completed.
示例性地，DMA控制器通过CPU在内存中设置的包括至少一个缓存描述BD项的BD表及数据缓存空间完成由外部芯片发起的外部芯片与CPU之间的数据上送操作，包括：Illustratively, the DMA controller completes the data upload operation between the external chip and the CPU initiated by the external chip by the BD table and the data cache space of the CPU including the at least one cache description BD item set in the memory, including:
DMA控制器接收CPU在初始化完成主动上送BD表后发送的主动上送BD表的特征信息；其中，主动上送BD表的特征信息包括：主动上送BD表中BD项的个数阈值，主动上送BD表存放的首地址和结束地址；而主动上送BD表中的BD项内容可以包括：该BD项的有效指示，该BD项对应的内存中数据块大小及该BD项对应的内存中数据起始地址；The DMA controller receives the feature information of the active BD table sent by the CPU after the initialization completes the BD table, and the feature information of the BD table that is actively sent to the BD table includes: Actively uploading the first address and the ending address of the BD table; and actively uploading the content of the BD item in the BD table may include: a valid indication of the BD item, an in-memory data block size corresponding to the BD item, and a corresponding BD item The starting address of the data in the memory;
DMA控制器接收外部芯片发送的待上送数据，并将待上送数据存入所述DMA控制器中的主动上送缓存； The DMA controller receives the data to be sent sent by the external chip, and stores the data to be sent into the active upload cache in the DMA controller;
当主动上送缓存满足预设条件时且主动传输单元自身保存的有效BD项数小于BD项的个数阈值时，DMA控制器根据主动上送BD表存放的首地址和结束地址读取BD项；When the active uplink buffer meets the preset condition and the number of valid BD items saved by the active transmission unit itself is less than the threshold number of the BD item, the DMA controller reads the BD item according to the first address and the end address stored in the BD table. ;
当BD项的有效指示为0时，DMA控制器将主动上送缓存中的待上送数据传输至BD项对应的内存中数据起始地址，并将BD项的有效指示更改为1，且将主动传输单元自身保存的有效BD项数加一；When the valid indication of the BD item is 0, the DMA controller transfers the data to be sent in the cache to the in-memory data start address corresponding to the BD item, and changes the valid indication of the BD item to 1, and The number of valid BD items saved by the active transmission unit itself is increased by one;
DMA控制器根据主动上送BD表存放的首地址和结束地址读取BD项在BD表中的下一个BD项。The DMA controller reads the next BD item of the BD item in the BD table according to the first address and the end address stored in the BD table.
较佳地，该方法还包括：Preferably, the method further comprises:
DMA控制器接收CPU在读取完BD项对应的内存中数据起始地址中的待上送数据后发送的读取完毕信息，并将主动传输单元自身保存的有效BD项数减一。The DMA controller receives the read completion information sent by the CPU after reading the data to be sent in the data start address corresponding to the BD item, and reduces the number of valid BD items saved by the active transmission unit by one.
示例性地，DMA控制器通过CPU在内存中设置的包括至少一个缓存描述BD项的BD表及数据缓存空间完成由外部芯片发起的外部芯片与CPU之间的数据下发操作，包括：Illustratively, the DMA controller completes the data delivery operation between the external chip and the CPU initiated by the external chip by using the BD table and the data cache space of the CPU, which is set in the memory, including at least one cache description BD item, including:
DMA控制器接收CPU在初始化完成主动下发BD项后发送的主动下发BD项的首地址和结束地址；The DMA controller receives the first address and the end address of the active delivery BD item sent by the CPU after the initialization completes the active delivery of the BD item;
DMA控制器接收CPU发送的主动下发起始指令后，根据主动下发BD项的首地址和结束地址读取主动下发BD项；After receiving the active sending start command sent by the CPU, the DMA controller actively releases the BD item according to the first address and the end address of the BD item.
DMA控制器根据主动下发BD项指示的内存空间中的待下发数据传输至主动下发缓存，并将主动下发缓存中的数据传输至外部芯片的存储器；The DMA controller transmits the data to be delivered in the memory space indicated by the BD item to the active delivery buffer, and transmits the data in the active delivery buffer to the memory of the external chip;
DMA控制器向CPU发送主动下发完成响应。The DMA controller sends an active delivery completion response to the CPU.
本实施例提供的数据传输的方法，可以同时支持主动方式和被动方式的数据传输，并且通过仲裁的方式避免了主动方式和被动方式的多路数据之间的竞争现象，通用性强，节省了CPU与外部芯片的读写数据时间 The data transmission method provided in this embodiment can support the data transmission in the active mode and the passive mode at the same time, and avoids the competition between the active mode and the passive mode of the multi-path data by means of arbitration, and has high versatility and saves. CPU and external chip read and write data time
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用硬件实施例、软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。Those skilled in the art will appreciate that embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention can take the form of a hardware embodiment, a software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
本发明是参照根据本发明实施例的方法、设备(系统)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。The present invention has been described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (system), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device. Means for implementing the functions specified in one or more of the flow or in a block or blocks of the flow chart.
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。The computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device. The apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device. The instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.
以上，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。 The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention.

Claims (12)

  1. 一种直接内存存取DMA控制器，所述DMA控制器包括：被动传输单元、主动传输单元、DMA调度单元和快捷外部设备互连PCIe单元，其中，A direct memory access DMA controller, the DMA controller comprising: a passive transmission unit, an active transmission unit, a DMA scheduling unit, and a shortcut external device interconnection PCIe unit, wherein
    所述被动传输单元，配置为根据中央处理器CPU配置的传输参数完成由所述CPU发起的所述外部芯片与所述CPU之间的数据上送和下发操作；The passive transmission unit is configured to complete a data uploading and sending operation between the external chip and the CPU initiated by the CPU according to a transmission parameter configured by a CPU of the CPU;
    所述主动传输单元，配置为通过所述CPU在内存中设置的包括至少一个缓存描述BD项的BD表及数据缓存空间完成由外部芯片发起的所述外部芯片与所述CPU之间的数据上送和下发操作；The active transmission unit is configured to complete data between the external chip and the CPU initiated by an external chip by using a BD table and a data cache space that are set in the memory by the CPU and including at least one cache description BD item. Send and deliver operations;
    所述DMA调度单元，配置为通过仲裁的方式避免所述外部芯片与所述CPU之间的数据上送和下发操作所引起的竞争；The DMA scheduling unit is configured to avoid contention caused by data uploading and sending operations between the external chip and the CPU by means of arbitration;
    所述PCIe单元，配置为为所述CPU和所述DMA控制器之间的信息交互提供PCIe接口。The PCIe unit is configured to provide a PCIe interface for information interaction between the CPU and the DMA controller.
  2. 根据权利要求1所述的DMA控制器，其中，所述被动传输单元，配置为：The DMA controller of claim 1, wherein the passive transmission unit is configured to:
    接收所述CPU配置的上送启动指令后，从所述CPU预置的外部芯片源地址按照所述CPU预置的上送数据长度将外部芯片存储器中的待上送数据读取至被动上送缓存；以及，After receiving the uploading start command of the CPU configuration, the external chip source address preset by the CPU reads the data to be sent in the external chip memory to be passively sent according to the uplink data length preset by the CPU. Cache; and,
    将所述被动上送缓存中的待上送数据写入所述CPU预置的内存目的地址中；以及，Writing the data to be sent in the passive uplink buffer to the memory destination address preset by the CPU; and
    当所述待上送数据完全写入所述CPU预置的内存目的地址后，通知所述CPU写入完成。After the data to be sent is completely written to the memory destination address preset by the CPU, the CPU is notified to complete the writing.
  3. 根据权利要求1所述的DMA控制器，其中，所述被动传输单元，配置为： The DMA controller of claim 1, wherein the passive transmission unit is configured to:
    接收所述CPU配置的下发启动指令后，从所述CPU预置的内存源地址按照所述CPU预置的下发数据长度将所述内存中的待下发数据读取至被动下发缓存；以及，After receiving the sending start command of the CPU configuration, the memory source address preset by the CPU reads the to-be-distributed data in the memory to the passive sending buffer according to the issued data length preset by the CPU. ;as well as,
    将所述被动下发缓存中的待下发数据写入所述CPU预置的外部芯片存储器的目的地址中；以及，Writing the data to be delivered in the passive sending buffer to the destination address of the external chip memory preset by the CPU; and
    当所述待下发数据完全写入所述CPU预置的外部芯片存储器的目的地址后，通知所述CPU下发完成。After the data to be delivered is completely written to the destination address of the external chip memory preset by the CPU, the CPU is notified to complete the delivery.
  4. 根据权利要求1所述的DMA控制器，其中，所述主动传输单元，配置为：The DMA controller of claim 1, wherein the active transmission unit is configured to:
    接收所述CPU在初始化完成主动上送BD表后发送的所述主动上送BD表的特征信息；其中，所述主动上送BD表的特征信息包括：所述主动上送BD表中BD项的个数阈值，所述主动上送BD表存放的首地址和结束地址；所述主动上送BD表中BD项的内容包括：所述BD项的有效指示，所述BD项对应的内存中数据块大小及所述BD项对应的内存中数据起始地址；Receiving the feature information of the active delivery BD table that is sent by the CPU after the initialization completes the active delivery of the BD table; wherein the feature information of the active delivery BD table includes: the BD item in the active delivery BD table The number of thresholds, the first address and the end address of the BD table that are actively sent to the BD table; the content of the BD item in the active BD table includes: a valid indication of the BD item, and the BD item corresponds to the memory a data block size and an in-memory data start address corresponding to the BD item;
    以及，接收外部芯片发送的待上送数据，并将所述待上送数据存入所述DMA控制器中的主动上送缓存；And receiving the data to be sent sent by the external chip, and storing the data to be sent into the active upload cache in the DMA controller;
    以及，当所述主动上送缓存满足预设条件时且所述主动传输单元自身保存的有效BD项数小于所述BD项的个数阈值时，根据所述主动上送BD表存放的首地址和结束地址读取所述BD项；And when the active uplink buffer meets the preset condition and the number of valid BD items saved by the active transmission unit itself is less than the threshold number of the BD item, according to the first address stored in the active delivery BD table. And reading the BD item with the end address;
    以及，当所述BD项的有效指示为0时，将所述主动上送缓存中的待上送数据传输至所述BD项对应的内存中数据起始地址，并将所述BD项的有效指示更改为1，且将所述主动传输单元自身保存的有效BD项数加一；And when the valid indication of the BD item is 0, the data to be sent in the active uplink buffer is transmitted to an in-memory data start address corresponding to the BD item, and the BD item is valid. The indication is changed to 1, and the number of valid BD items saved by the active transmission unit itself is increased by one;
    以及，根据所述主动上送BD表存放的首地址和结束地址读取所述BD项在所述BD表中的下一个BD项。And reading the next BD item of the BD item in the BD table according to the first address and the end address stored in the active delivery BD table.
  5. 根据权利要求4所述的DMA控制器，其中，所述主动传输单元还 配置为：接收所述CPU在读取完所述BD项对应的内存中数据起始地址中的待上送数据后发送的读取完毕信息，并将所述主动传输单元自身保存的有效BD项数减一。The DMA controller according to claim 4, wherein said active transmission unit further The method is configured to: receive the read completion information sent by the CPU after reading the data to be sent in the in-memory data start address corresponding to the BD item, and save the valid BD item saved by the active transmission unit itself Decrease by one.
  6. 根据权利要求1所述的DMA控制器，其中，所述主动传输单元，配置为：The DMA controller of claim 1, wherein the active transmission unit is configured to:
    接收所述CPU在初始化完成主动下发BD项后发送的所述主动下发BD项的首地址和结束地址；以及，Receiving, by the CPU, a first address and an end address of the active delivery BD item that are sent after the initial completion of the initial delivery of the BD item by the CPU;
    接收所述CPU发送的主动下发起始指令后，根据所述主动下发BD项的首地址和结束地址读取所述主动下发BD项；以及，After receiving the active delivery start command sent by the CPU, reading the active delivery BD item according to the first address and the end address of the active delivery BD item; and
    根据所述主动下发BD项指示的内存空间中的待下发数据传输至主动下发缓存，并将所述主动下发缓存中的数据传输至所述外部芯片的存储器；以及，Transmitting the data to be delivered in the memory space indicated by the active delivery of the BD item to the active delivery buffer, and transmitting the data in the active delivery buffer to the memory of the external chip;
    向所述CPU发送主动下发完成响应。Sending an active delivery completion response to the CPU.
  7. 一种数据传输的方法，所述方法应用于直接内存存取DMA控制器，所述方法包括：A method of data transmission, the method being applied to a direct memory access DMA controller, the method comprising:
    所述DMA控制器根据中央处理器CPU配置的传输参数完成由所述CPU发起的所述外部芯片与所述CPU之间的数据上送和下发操作；Determining, by the DMA controller, a data uploading and sending operation between the external chip and the CPU initiated by the CPU according to a transmission parameter configured by a CPU of the CPU;
    所述DMA控制器通过所述CPU在内存中设置的包括至少一个缓存描述BD项的BD表及数据缓存空间完成由外部芯片发起的所述外部芯片与所述CPU之间的数据上送和下发操作；The DMA controller performs data uploading and sending between the external chip and the CPU initiated by an external chip by using a BD table and a data cache space of the CPU, which is set in the memory, including at least one cache description BD item. Send operation
    所述DMA控制器通过仲裁的方式避免所述外部芯片与所述CPU之间的数据上送和下发操作所引起的竞争，其中，所述CPU和所述DMA控制器之间的信息交互通过PCIe接口进行。The DMA controller avoids competition caused by data uploading and sending operations between the external chip and the CPU by means of arbitration, wherein information interaction between the CPU and the DMA controller is passed The PCIe interface is performed.
  8. 根据权利要求7所述的方法，其中，所述DMA控制器根据CPU配置的传输参数完成由所述CPU发起的所述外部芯片与所述CPU之间的数据 上送操作，包括：The method according to claim 7, wherein said DMA controller completes data between said external chip and said CPU initiated by said CPU in accordance with a transmission parameter of a CPU configuration Upload operation, including:
    所述DMA控制器接收所述CPU配置的上送启动指令后，从所述CPU预置的外部芯片源地址按照所述CPU预置的上送数据长度将外部芯片存储器中的待上送数据读取至被动上送缓存；After the DMA controller receives the uploading instruction of the CPU configuration, the external chip source address preset by the CPU reads the data to be sent in the external chip memory according to the uplink data length preset by the CPU. Take the passive send cache;
    所述DMA控制器将所述被动上送缓存中的待上送数据写入所述CPU预置的内存目的地址中；The DMA controller writes the data to be sent in the passive uplink buffer to the memory destination address preset by the CPU;
    所述DMA控制器当所述待上送数据完全写入所述CPU预置的内存目的地址后，通知所述CPU写入完成。The DMA controller notifies the CPU that the writing is completed after the data to be sent is completely written to the memory destination address preset by the CPU.
  9. 根据权利要求7所述的方法，其中，所述DMA控制器根据CPU配置的传输参数完成由所述CPU发起的所述外部芯片与所述CPU之间的数据下发操作，包括：The method of claim 7, wherein the DMA controller completes a data delivery operation between the external chip and the CPU initiated by the CPU according to a transmission parameter configured by the CPU, including:
    所述DMA控制器接收所述CPU配置的下发启动指令后，从所述CPU预置的内存源地址按照所述CPU预置的下发数据长度将所述内存中的待下发数据读取至被动下发缓存；After the DMA controller receives the issued start command of the CPU, the memory source address preset by the CPU reads the data to be sent in the memory according to the length of the data sent by the CPU. To passively send the cache;
    所述DMA控制器将所述被动下发缓存中的待下发数据写入所述CPU预置的外部芯片存储器的目的地址中；Writing, by the DMA controller, the data to be sent in the passive sending buffer to the destination address of the external chip memory preset by the CPU;
    所述DMA控制器当所述待下发数据完全写入所述CPU预置的外部芯片存储器的目的地址后，通知所述CPU下发完成。The DMA controller notifies the CPU that the delivery is completed after the data to be sent is completely written to the destination address of the external chip memory preset by the CPU.
  10. 根据权利要求7所述的方法，其中，所述DMA控制器通过所述CPU在内存中设置的包括至少一个缓存描述BD项的BD表及数据缓存空间完成由外部芯片发起的所述外部芯片与所述CPU之间的数据上送操作，包括：The method according to claim 7, wherein said DMA controller completes said external chip initiated by an external chip by said BD table and data buffer space of said CPU being set in said memory including at least one cache description BD item. The data upload operation between the CPUs includes:
    所述DMA控制器接收所述CPU在初始化完成主动上送BD表后发送的所述主动上送BD表的特征信息；其中，所述主动上送BD表的特征信息包括：所述主动上送BD表中BD项的个数阈值，所述主动上送BD表存放 的首地址和结束地址；所述主动上送BD表中BD项的内容包括：所述BD项的有效指示，所述BD项对应的内存中数据块大小，所述BD项对应的内存中数据起始地址；The DMA controller receives the feature information of the active delivery BD table that is sent by the CPU after the initialization completes the active delivery of the BD table, where the feature information of the active delivery BD table includes: the active delivery The threshold of the number of BD items in the BD table, the active delivery BD table storage The first address and the end address; the content of the BD item in the active delivery BD table includes: a valid indication of the BD item, an in-memory data block size corresponding to the BD item, and an in-memory data corresponding to the BD item initial address;
    所述DMA控制器接收外部芯片发送的待上送数据，并将所述待上送数据存入所述DMA控制器中的主动上送缓存；The DMA controller receives the data to be sent sent by the external chip, and stores the data to be sent into the active upload cache in the DMA controller;
    当所述主动上送缓存满足预设条件时且所述主动传输单元自身保存的有效BD项数小于所述BD项的个数阈值时，所述DMA控制器根据所述主动上送BD表存放的首地址和结束地址读取所述BD项；When the active uplink buffer meets the preset condition and the number of valid BD items saved by the active transmission unit itself is less than the threshold number of the BD item, the DMA controller stores the BD table according to the active delivery The first address and the end address read the BD item;
    当所述BD项的有效指示为0时，所述DMA控制器将所述主动上送缓存中的待上送数据传输至所述BD项对应的内存中数据起始地址，并将所述BD项的有效指示更改为1，且将所述主动传输单元自身保存的有效BD项数加一；When the valid indication of the BD item is 0, the DMA controller transmits the data to be sent in the active uplink buffer to the in-memory data start address corresponding to the BD item, and the BD is The effective indication of the item is changed to 1, and the number of valid BD items saved by the active transmission unit itself is increased by one;
    所述DMA控制器根据所述主动上送BD表存放的首地址和结束地址读取所述BD项在所述BD表中的下一个BD项。The DMA controller reads the next BD item of the BD item in the BD table according to the first address and the end address stored in the active delivery BD table.
  11. 根据权利要求10所述的方法，其中，所述方法还包括：The method of claim 10, wherein the method further comprises:
    所述DMA控制器接收所述CPU在读取完所述BD项对应的内存中数据起始地址中的待上送数据后发送的读取完毕信息，并将所述主动传输单元自身保存的有效BD项数减一。Receiving, by the DMA controller, the read completion information sent by the CPU after reading the data to be sent in the in-memory data start address corresponding to the BD item, and saving the active transmission unit itself The number of BD items is reduced by one.
  12. 根据权利要求7所述的方法，其中，所述DMA控制器通过所述CPU在内存中设置的包括至少一个缓存描述BD项的BD表及数据缓存空间完成由外部芯片发起的所述外部芯片与所述CPU之间的数据下发操作，包括：The method according to claim 7, wherein said DMA controller completes said external chip initiated by an external chip by said BD table and data buffer space of said CPU being set in said memory including at least one cache description BD item. The data delivery operation between the CPUs includes:
    所述DMA控制器接收所述CPU在初始化完成主动下发BD项后发送的所述主动下发BD项的首地址和结束地址；Receiving, by the DMA controller, a first address and an end address of the active delivery BD item that are sent by the CPU after the initial completion of the initial delivery of the BD item;
    所述DMA控制器接收所述CPU发送的主动下发起始指令后，根据所 述主动下发BD项的首地址和结束地址读取所述主动下发BD项；After the DMA controller receives the active sending start command sent by the CPU, according to the The active delivery BD item is read by the first address and the end address of the BD item;
    所述DMA控制器根据所述主动下发BD项指示的内存空间中的待下发数据传输至主动下发缓存，并将所述主动下发缓存中的数据传输至所述外部芯片的存储器；The DMA controller transmits the data to be delivered in the memory space indicated by the active delivery BD item to the active delivery buffer, and transmits the data in the active delivery buffer to the memory of the external chip;
    所述DMA控制器向所述CPU发送主动下发完成响应。 The DMA controller sends an active delivery completion response to the CPU.
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