CN106775477B - SSD (solid State disk) master control data transmission management device and method - Google Patents
SSD (solid State disk) master control data transmission management device and method Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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Abstract
The invention discloses a BE Buffer for SSD master control, a SSD master control and a Data transmission management device and a method, wherein the Buffer allocation, the Data synchronization and the Buffer release in the transmission process among DMA are automatically completed by combining a DMA transmission control rule realized by Data Flag and hardware, a CPU (central processing unit) is not required to intervene in the whole transmission process in a large quantity, and a large amount of CPU time resources are saved; the latency of Flash DMA is greatly reduced, thereby reducing the read delay. Particularly, aiming at the condition of large IO, under the DMA transmission control rule realized by combining Data Flag with hardware, BE DMA/Flash DMA can automatically carry out multiple transmissions in a suspension and awakening mode according to the setting condition of the Data Flag without the intervention of a CPU (central processing unit), and the transmission efficiency is not deteriorated but improved in the large IO scene.
Description
Technical Field
The invention belongs to the field of SSD master control data transmission, and particularly relates to a BE Buffer for SSD master control, SSD master control and data transmission management device and method.
Background
In the mainstream SSD main control, there are DMA such as Sata DMA, Flash DMA, and BE DMA, and as shown in fig. 1, a solid arrow in the figure indicates a data flow direction in a write operation, and a dotted arrow indicates a data flow direction in a read operation.
In the SSD writing process, Sata DMA is responsible for transmitting data from HOST to a DRAM outside a chip, Core DMA is responsible for transmitting the data in the DRAM to BE Buffer in the chip, and Flash DMA is responsible for transmitting the data in the BE Buffer to Flash; in the SSD reading process, FLASH DMA is responsible for transmitting FLASH data to BE Buffer, and SATA DMA is responsible for transmitting BE Buffer data to HOST. As can BE seen from fig. 1, if the higher the data transmission efficiency between DMAs is, the less CPU time resources are consumed for managing the data cache between DMAs (DRAM/BE Buffer), the shorter the data transmission delay between HOST and FLASH is, that is, the higher the SSD data read-write bandwidth is.
The data transmission management method between the existing DMAs in the SSD is shown in fig. 2, in which the data transmission management method between the DMAs in the prior art is described by a data transmission process between the BE DMA and the FLASH under the SSD write operation, and the method can also BE applied to the data transmission management between other DMAs.
The operation meanings of the step numbers in fig. 2 are as follows:
as can BE seen from fig. 2, in the existing design, each data transmission request between the BE DMA and the FLASH DMA is completed by 10 steps, wherein 8 steps require CPU to participate, which consumes significant CPU time resources, and inevitably results in a long transmission delay.
In addition, each transmission needs to transmit the data requested to BE transmitted by the BE DMA to the back of the BE Buffer to start the transmission of the Flash DMA, namely the Flash DMA and the CPU have a long time waiting for the completion of the transmission of the data by the BE DMA, and the invalid waiting means low transmission efficiency.
With reference to fig. 2, the conventional DMA transfer management method has the following disadvantages:
(1) the occupied CPU time resource is more, data transmission between the BE DMA and the Flash DMA in the figure 2 needs to BE decomposed into 10 steps to BE completed, 8 steps need the participation of the CPU, obviously, the CPU time resource consumption is serious, the data transmission delay between the BE DMA is inevitably increased, the capacity of the CPU for processing other tasks is weakened, and the performance of the whole SSD system is affected.
(2) The invalid waiting time between the DMAs is too long, and the transmission efficiency is low. As can BE seen from fig. 2, in a single transfer request, the data transfer of the FLASH DMA can BE started only after the BE DMA completes the data transfer (step 5 and step 8 cannot BE performed simultaneously in the same request), that is, the FLASH DMA waits for the BE DMA to complete the data transfer for a long time, and these invalid waits are also an important reason for the long transfer delay.
(3) The large IO transmission efficiency deteriorates, the large IO refers to the condition that the size of one-time data transmission exceeds the size of the BE Buffer, at the moment, the large IO needs to BE disassembled into a plurality of small IOs which can BE cached in the BE Buffer for transmission, namely, for the large IO, the number of operation steps and the number of the disassembled small IOs are increased in proportion, and the data transmission delay is further deteriorated.
The explanations of nouns or abbreviations used in the present invention are as follows:
SSD: solid State Drive, a storage for storing user data using Flash medium
Storing the equipment;
DMA: direct Memory Access; a direct memory access controller;
BE DMA: back end DMA and back end DMA for data transmission inside the SSD;
flash DMA: and the FLASH memory DMA is used for transmitting data to the FLASH or reading the FLASH data.
Disclosure of Invention
The invention aims to solve the technical problems that in the prior art, the BE Buffer for the SSD master control, the SSD master control and the data transmission management device and method are provided, the problems that in the existing DMA data transmission management method, more CPU time resources are occupied, invalid waiting time between the DMAs is too long, and large IO transmission efficiency is deteriorated are solved, the occupation of CPU time resources is reduced, the data transmission efficiency between the DMAs is improved, invalid delay is reduced, and the SSD data throughput capacity is finally improved.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows: an SSD master control BE Buffer comprises a plurality of storage units; the storage unit also comprises a Data Flag space, and each storage unit has exclusive Mbit information in the Data Flag space and corresponds to the storage unit; if the exclusive Mbit information state of the Data Flag space corresponding to a certain storage unit is 0, indicating that the storage unit is not full; if the exclusive Mbit information state of the Data Flag space corresponding to a certain memory cell is set to 1, it indicates that the memory cell is full of Data Flag.
The SSD master control adopts the BE Buffer.
Correspondingly, the invention also provides a data transmission management device between the DMA in the SSD master control, which comprises a CPU; the CPU is used for receiving a Trans Req request from the SSD master control BE DMA, obtaining an initial position of the BE DMA written in the BE Buffer, configuring the initial position to the Flash DMA through the Trans Req request, and starting the SSD master control Flash DMA to transmit data.
In order to solve the above problems, the present invention further provides a method for performing data transfer management between DMAs in SSD master control by using the above transfer management apparatus, comprising the steps of:
1) when the BE DMA needs to transmit data to the BE Buffer, the ending position of the last transmission is automatically used as the starting position of the current data transmission, a Trans Req request is used for notifying a CPU, and the transmission starting position of the BE Buffer is reported to the CPU;
2) after receiving a Trans Req request from a BE DMA, a CPU obtains an initial position of the BE DMA written in a BE Buffer, configures the initial position to a Flash DMA through the Trans Req request, and starts the Flash DMA to transmit data;
3) and starting BE DMA to transmit data, executing data transmission action by the BE DMA, and executing the data transmission action by the Flash DMA when the BE DMA finishes transmitting 1 storage unit.
In step 3), the BE DMA executes data transmission action according to the following rules:
1) if the BE DMA needs to write a certain storage unit, the Data Flag space corresponding to the storage unit is found to BE 0, the BE DMA immediately writes Data into the storage unit, and immediately sets the Data Flag space corresponding to the storage unit to BE 1 after the storage unit is fully written;
2) if the BE DMA needs to write a certain storage unit, the Data Flag space corresponding to the storage unit is found to BE 1, the Data transmission of the BE DMA is suspended, and the BE DMA continues the Data transmission according to the rule 1) until the Data Flag space of the storage unit is cleared by other modules by 0;
3) when the BE Buffer is read and written to the right boundary, the next reading and writing position automatically jumps to the initial position of the left boundary of the BE Buffer to read and write.
In step 3), the Flash DMA executes data transmission action according to the following rules:
rule a): if the Flash DMA needs to fetch Data from a certain storage unit, finding that the Data Flag space value corresponding to the storage unit is 1, fetching the Data in the storage unit, and clearing 0 the Data Flag space corresponding to the storage unit after all the Data in the storage unit are fetched;
rule B): and if the Data Flag space value corresponding to the storage unit is found to be 0 when the Flash DMA needs to fetch Data from the storage unit, suspending Data transmission of the Flash DMA until the Data Flag space of the storage unit is set to be 1 by other hardware modules, and continuing Data transmission of the Flash DMA according to the rule B).
Compared with the prior art, the invention has the beneficial effects that: according to the invention, the allocation of the buffer space, the Data synchronization and the buffer space release in the transmission process among the DMAs are automatically completed through the DMA transmission control rule realized by combining the Data Flag with hardware, and the CPU is released from the heavy processing, so that the precious CPU time resource is greatly saved, and the capacity of the CPU for processing other services of the SSD is effectively improved; by combining a Data Flag mechanism, when the Write DMA finishes writing 1 storage unit Data, the Read DMA can immediately take the Data in the storage unit, and the Read DMA does not need to start Data transmission after waiting for all Data under the request of the Write DMA to finish transmitting once, so that the invalid waiting time of the Read DMA is greatly reduced, and the DMA transmission efficiency is obviously improved; in combination with Data Flag, the Data transmission in a burst mode can be automatically completed between the DMAs, which means that the operation steps of the CPU in the transmission process are the same no matter whether the large IO or the small IO exists, so that under the invention, the transmission efficiency of the large IO is not deteriorated but is better than that of the small IO.
Drawings
FIG. 1 is a diagram of a conventional SSD master DMA;
FIG. 2 is a diagram illustrating a conventional management method for data transmission between DMAs in an SSD;
FIG. 3 is a diagram illustrating a method for managing data transfer between DMAs in an SSD according to the present invention.
Detailed Description
As shown in fig. 3, the implementation process of the present invention is as follows:
1. appointing a storage unit with a specified size and a Data Flag space, wherein the Buffer between the DMAs is composed of a plurality of storage units, and each storage unit has exclusive 1-bit or multi-bit information in the Data Flag and corresponds to the storage unit. If the Data Flag of a certain memory cell is in a state of 0, the memory cell is not fully written; if the Data Flag of a certain memory cell is in state 1, it indicates that the memory cell is full of Data. As the contracted memory cell in FIG. 3 is 512B in size, each memory cell has exclusive 1-bit information corresponding to it in the Data Flag, the state 0 indicates that the Data Flag value of the memory cell is 0, the state 1 indicates that the Data Flag value of the memory cell is 0, and the Buffer between DMAs is BE Buffer.
2. On the basis of 1, when the Write DMA needs to Write a certain memory location in the buffer, if the Data Flag of the Write DMA is in the state 0, the Write DMA can Write the memory location, if the Data Flag of the Write DMA is in the state 1, the Write DMA can not Write the memory location, and the Write operation of the Write DMA is suspended until the Data Flag is converted into the state 0, so that the Write DMA can be activated to continue writing. As in FIG. 3, Write DMA refers to BE DMA, i.e., DMA that needs to Write data into the buffer.
3. On the basis of 1, when the Read DMA needs to Read a certain memory location in the buffer, if the Data Flag is in the state 1, the Read DMA can Read the memory location, and if the Data Flag is in the state 0, the Read DMA cannot Read the memory location, and suspend the Read operation of the Read DMA until the Data Flag is changed into the state 1, so that the Read DMA can be activated to continue reading. As in fig. 3, Read DMA refers to Flash DMA, i.e. DMA that needs to fetch data from buffer.
4. On a 2 basis, when the Write DMA Write exceeds the end of the Buffer, then the Write DMA Write pointer jumps to the beginning of the Buffer to continue writing data.
5. On the basis of 3, when the Read DMA Read exceeds the end point of the Buffer, the Read DMA Read pointer jumps to the starting position of the Buffer to continue reading data. Read DMA refers to Flash DMA.
6. On the basis of 4, the Write DMA can automatically complete the allocation of the Data storage target space without concern about whether the target space exceeds the buffer size or not and whether the target space is occupied by other transmission or not, because the Data Flag automatically controls the allocation.
Comparing the schemes of fig. 3 and fig. 2, the biggest difference of fig. 3 is that one more hardware module Data Flag (implemented by memory) is added.
Data Flag definition: according to the SSD front-end protocol, SSD transmission data is definitely sector aligned, and each sector is 512B in size. Therefore, in the scheme, each sector space in the BE Buffer is provided with exclusive 1-bit information corresponding to the sector space in the Data Flag. A Data Flag of a sector space of 0 indicates that the sector space is not full, and a Data Flag of 1 indicates that the sector space is full.
In combination with Data Flag, the hardware needs to implement the following DMA transfer control rules:
(1) if the BE DMA needs to write a sector space, if the Data Flag corresponding to the sector space is found to BE 0, the BE DMA immediately writes the Data into the space, and immediately sets the Data Flag corresponding to the space to 1 after the BE DMA is completely written with 512B.
(2) And if the BE DMA needs to write a certain sector space, finding that the corresponding Data Flag is 1, suspending the Data transmission of the BE DMA until the Data Flag of the space is cleared by other modules to BE 0, and then continuing the Data transmission of the BE DMA according to the rule (1).
(3) And if the Flash DMA needs to fetch Data from a certain sector space, finding that the corresponding Data Flag value is 1, taking the Data in the space, and clearing 0 the Data Flag corresponding to the space after taking 512B.
(4) And if the Data Flag value corresponding to the Flash DMA is found to be 0 when the Flash DMA needs to fetch Data from a certain sector space, suspending Data transmission of the Flash DMA until the Data Flag of the space is set to be 1 by other hardware modules, and continuing the Data transmission of the Flash DMA according to the rule (3).
(5) The BE DMA/Flash DMA has BE Buffer loop read-write function, namely when the BE Buffer right boundary is read and written, the next read-write position automatically jumps to the BE Buffer left boundary initial position to read and write.
The operation meanings of the step numbers in fig. 3 are as follows:
since the actions of table entry management, subsequent write alignment and the like are also involved in the SSD system, the CPU needs to know the data start position of the write request in the BE Buffer, and thus steps 1 and 2 cannot BE omitted.
As can be seen from fig. 3, in the present invention, the Buffer allocation, Data synchronization (Data synchronization is ensured by Trans Done signals in fig. 2), and Buffer release in the transmission process between DMAs are automatically completed by the DMA transmission control rule realized by Data Flag in combination with hardware, and a large amount of intervention by the CPU in the whole transmission process is not required, and the operations related to the CPU are reduced from 8 steps in fig. 2 to 3 steps, so that a large amount of CPU time resources are saved; in addition, step 5 in fig. 3 does not need to wait until all steps 4 are finished to start data transmission, but step 5 can start data transmission immediately after 1 sector data is transmitted in step 4, so that the waiting time of Flash DMA is greatly reduced, and the read delay is reduced. Particularly, for the situation of large IO, under the DMA transmission control rule realized by combining Data Flag with hardware, BE DMA/Flash DMA can automatically carry out multiple transmissions in a suspension and awakening mode according to the setting situation of the Data Flag without intervention of a CPU (central processing unit), so that for the application of the large IO scene, the transmission can BE finished only by 6 steps of operation in fig. 3, therefore, in the scheme, under the large IO scene, the transmission efficiency cannot BE deteriorated, but is improved.
Claims (6)
1. A data transmission management device between DMA in SSD master control comprises a CPU and a BE Buffer of the SSD master control; the SSD master control BE Buffer comprises a plurality of storage units and a Data Flag space, and each storage unit has exclusive Mbit information in the Data Flag space and corresponds to the storage unit Data Flag; if the exclusive Mbit information state of the Data Flag space corresponding to a certain storage unit is 0, indicating that the storage unit is not full; if the exclusive Mbit information state of the Data Flag space corresponding to a certain storage unit is set to 1, the storage unit is full; the method is characterized in that the CPU is used for receiving a Trans Req request from the SSD master control BE DMA, obtaining the initial position of the BE DMA written in the BE Buffer, configuring the initial position to the Flash DMA through the Trans Req request, and starting the SSD master control Flash DMA to transmit data.
2. The device for managing data transfer between DMAs in SSD master control of claim 1, wherein M ≧ 1.
3. The apparatus according to claim 1, wherein the size of the storage unit is 512B.
4. A method for performing data transfer management between DMAs in SSD master control by using the transfer management device according to any of claims 1 to 3, comprising the steps of:
1) when the BE DMA needs to transmit data to the BE Buffer, the ending position of the last transmission is automatically used as the starting position of the current data transmission, a Trans Req request is used for notifying a CPU, and the transmission starting position of the BE Buffer is reported to the CPU;
2) after receiving a Trans Req request from a BE DMA, a CPU obtains an initial position of the BE DMA written in a BE Buffer, configures the initial position to a Flash DMA through the Trans Req request, and starts the Flash DMA to transmit data;
3) and starting BE DMA to transmit data, executing data transmission action by the BE DMA, and executing the data transmission action by the Flash DMA when the BE DMA finishes transmitting 1 storage unit.
5. The method of claim 4, wherein in step 3), the BE DMA performs the data transfer action according to the following rules:
1) if the BE DMA needs to write a certain storage unit, the Data Flag space corresponding to the storage unit is found to BE 0, the BE DMA immediately writes Data into the storage unit, and immediately sets the Data Flag space corresponding to the storage unit to BE 1 after the storage unit is fully written;
2) if the BE DMA needs to write a certain storage unit, the Data Flag space corresponding to the storage unit is found to BE 1, the Data transmission of the BE DMA is suspended, and the BE DMA continues the Data transmission according to the rule 1) until the Data Flag space of the storage unit is cleared by other modules by 0;
3) when the BE Buffer is read and written to the right boundary, the next reading and writing position automatically jumps to the initial position of the left boundary of the BE Buffer to read and write.
6. The method according to claim 5, wherein in step 3), the Flash DMA executes the data transfer action according to the following rules:
rule a): if the Flash DMA needs to fetch Data from a certain storage unit, finding that the Data Flag space value corresponding to the storage unit is 1, fetching the Data in the storage unit, and clearing 0 the Data Flag space corresponding to the storage unit after all the Data in the storage unit are fetched;
rule B): and if the Data Flag space value corresponding to the storage unit is found to be 0 when the Flash DMA needs to fetch Data from the storage unit, suspending Data transmission of the Flash DMA until the Data Flag space of the storage unit is set to be 1 by other hardware modules, and continuing Data transmission of the Flash DMA according to the rule B).
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| CN109189337B (en) * | 2018-08-21 | 2021-12-17 | 浪潮电子信息产业股份有限公司 | Method, device and equipment for selecting data block and readable storage medium |
| CN109614048B (en) * | 2018-12-10 | 2022-11-11 | 深圳市硅格半导体有限公司 | Data read-write method and device based on flash memory and computer readable storage medium |
| CN111831595A (en) * | 2020-06-30 | 2020-10-27 | 山东云海国创云计算装备产业创新中心有限公司 | DMA transmission method and related device |
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| CN1286029C (en) * | 2002-08-20 | 2006-11-22 | 华为技术有限公司 | Device for controlling interior storage of chip and its storage method |
| US7734842B2 (en) * | 2006-03-28 | 2010-06-08 | International Business Machines Corporation | Computer-implemented method, apparatus, and computer program product for managing DMA write page faults using a pool of substitute pages |
| CN100440184C (en) * | 2007-04-26 | 2008-12-03 | 北京中星微电子有限公司 | DMA controller and transmit method capable of simultaneously carrying out read-write operation |
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