CN210155650U

CN210155650U - Solid state hard disk controller

Info

Publication number: CN210155650U
Application number: CN201921191770.3U
Authority: CN
Inventors: 姚珅; 刘海銮
Original assignee: Hangzhou Electronic Science and Technology University
Current assignee: Hangzhou Electronic Science and Technology University
Priority date: 2019-07-26
Filing date: 2019-07-26
Publication date: 2020-03-17
Anticipated expiration: 2029-07-26

Abstract

The utility model discloses a solid state hard disk controller, the integrated encapsulation of this solid state hard disk controller is single chip, includes CPU, main control interface controller, flash memory controller and cache unit at least, wherein, CPU is connected with main control interface controller, flash memory controller and cache unit for the work of control solid state hard disk controller; the master control interface controller is connected with an external host and is used for carrying out data transmission with the external host; the cache unit adopts an SRAM and is used for caching the data received by the main control interface controller; the FLASH memory controller is connected with the FLASH and is used for storing the data in the cache unit into the FLASH. Compared with the prior art, the utility model provides a brand-new SSD master control buffer memory framework adopts SRAM to replace DRAM to integrate the buffer memory among the main control chip, thereby optimized the system architecture of chip, optimized PCB's distribution and wiring and reduce the size to a certain extent, very big reduction the hardware cost.

Description

Solid state hard disk controller

Technical Field

The utility model relates to a memory technical field especially relates to a solid state hard disk controller.

Background

Solid State Disks (SSDs) have become the mainstream storage devices at present, and are widely used for data storage in various fields. Currently, the mainstream SSD architecture is as shown in fig. 1, a solid state disk Controller (SSD Controller) is an integrated and packaged chip (ASIC), and a host interface Controller, a flash memory Controller and a DRAM Controller are arranged in the SSD, wherein the host interface Controller (host interface Controller) is used as a front end to interface with a host, and the interface can be a PCEI, SATA, SAS interface, or the like; the Flash Controller (Flash Controller) is used as a back end to exchange with the Flash memory (FLASH) and finish data coding and decoding and ECC verification, and the DRAM Controller is also interconnected and communicated with the independently packaged DRAM through an AXI bus and is used for data caching.

In the above structure, the DRAM is externally connected to the outside of the solid state hard disk controller by a PCB connection. The data is transmitted through the host interface, the DRAM controller then applies for the authority of the transmission bus to the CPU, then the data is written into the corresponding address of the DRAM and is informed to the FLASH memory controller, and the FLASH memory controller takes out the data from the DRAM and stores the data into the FLASH so as to finish the storage process of the data. Because the interface bandwidth of the DRAM is generally larger than the data transmission bandwidth, the DRAM can continuously receive and process read and write data of a host interface at full speed.

However, DRAMs are expensive, often more expensive than integrated packaged solid state hard disk controller chips, which undoubtedly increases the hardware cost of SSDs. Meanwhile, as the DRAM and the chip adopt completely different processes and cannot be integrated in the chip, the PCB needs to reserve the placement space of the DRAM on the design of the solid state disk, and the master control needs to design an interface externally connected with the DRAM, so that the size of the SSD cannot be further reduced.

Therefore, it is necessary to provide a technical solution to solve the technical problems of the prior art.

SUMMERY OF THE UTILITY MODEL

In view of the above, it is necessary to provide a solid state disk controller, which adopts the idea of replacing DRAM with SRAM and integrates a cache unit inside the solid state disk controller, so as to completely get rid of the dependence of the system on DRAM, eliminate the need of additional DRAM in the design of the solid state disk, and further reduce the volume and cost of the solid state disk.

In order to solve the technical problem existing in the prior art, the technical scheme of the utility model as follows:

a solid state hard disk controller, the solid state hard disk controller is integrated and packaged as a single chip, at least comprises a CPU, a main control interface controller, a flash memory controller and a cache unit, wherein,

the CPU is connected with the master control interface controller, the flash memory controller and the cache unit and is used for controlling the work of the solid state hard disk controller;

the master control interface controller is connected with an external host and is used for carrying out data transmission with the external host;

the cache unit adopts an SRAM and is used for caching the data received by the master control interface controller;

the FLASH memory controller is connected with the FLASH and is used for storing the data in the cache unit into the FLASH.

As a further improvement, a cache controller is further provided, and the cache controller is connected with the CPU, the main control interface controller, the flash memory controller and the cache unit, and is configured to control the cache unit according to an instruction of the CPU.

As a further improvement, an AXI bus is used between the cache controller and the cache unit.

As a further improvement, the bandwidth of the cache unit is at least twice of the data incoming bandwidth of the host interface side.

As a further improvement, the bandwidth of the cache unit is 4 GB/s.

As a further improvement, the master interface controller adopts PCEI, SATA or SAS interface.

Compared with the prior art, the utility model provides a brand-new SSD master control buffer memory framework adopts SRAM to replace the DRAM module to among the main control chip with the buffer memory, thereby optimized the system architecture of chip, simplified into two big modules of main control and FLASH from original main control, DRAM, three big modules of FLASH, optimized PCB's layout wiring and reduced size to a certain extent, very big reduction hardware cost.

Drawings

Fig. 1 is a block diagram of a solid state disk in the prior art.

Fig. 2 is a schematic block diagram of the solid state hard disk controller of the present invention.

Fig. 3 is a schematic block diagram of a solid state hard disk controller according to another embodiment of the present invention.

The following detailed description of the invention will be made in conjunction with the above-described drawings.

Detailed Description

The technical solution provided by the present invention will be further explained with reference to the accompanying drawings.

In the prior art, the SSD has to use the DRAM during operation, thereby causing the cost of the solid state disk to increase. In view of the technical defect, the present invention provides a novel SSD master cache architecture, which is shown in fig. 2 as a schematic block diagram of the solid state hard disk controller of the present invention, wherein the solid state hard disk controller is integrally packaged as a single chip, and at least comprises a CPU, a master interface controller, a flash memory controller and a cache unit therein,

the master control interface controller adopts PCEI, SATA or SAS and other interfaces, is connected with an external host and is used for carrying out data transmission with the external host;

In the technical scheme, the SRAM is adopted to replace the DRAM, and the SRAM and the main control chip adopt the same process, so that the cache can be integrated into the main control chip, and the DRAM does not need to be additionally arranged in the design of the solid state disk.

Referring to fig. 3, a schematic block diagram of a solid state hard disk controller according to another embodiment of the present invention is shown, and a cache controller is further provided, where the cache controller is connected to the CPU, the main control interface controller, the flash memory controller and the cache unit, and is configured to control the cache unit according to an instruction of the CPU. The cache controller can more conveniently control the cache unit, and the specific control mechanism is as follows:

the bandwidth of the cache unit is assumed to be 4GB/s, the write-in rate of the host interface is assumed to be 1GB/s, data is transmitted from the host interface, the host interface controller is responsible for decoding and verifying the transmitted data and then informing the cache unit controller that the data needs to be transmitted, the cache unit controller applies for the use right of the system bus to the CPU, after the cache unit controller obtains the use right of the system bus, the data which needs to be transmitted is directly stored in the cache unit and informs the FLASH controller, and then the FLASH controller directly takes out the data in the cache unit and writes the data into the FLASH. Because the bandwidth of the cache unit is more than 2 times of the data transmission bandwidth of the host interface end, the design can not reduce the data transmission performance of the hard disk. The design is simplified well, the wiring is laid out, and the design cost is reduced.

In a preferred embodiment, a cache unit structure is adopted to replace a DRAM and the same high-speed AXI bus structure is adopted as the existing DRAM, the cache unit is designed and integrated inside a main control chip during design, and the AXI transmission bus which is the same as the DRAM is simulated in an SOC for mutual communication. The secondary cache unit has the same data bandwidth and data processing speed as the DRAM. Due to the adoption of the AXI bus structure, the external DRAM can be connected with the bus for storage and capacity expansion, so that an interface circuit of an external DRAM part is eliminated, the external DRAM is replaced by a cache unit, and the compatibility of the original architecture can be kept.

The above description of the embodiments is only intended to help understand the method of the present invention and its core ideas. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, the present invention can be further modified and modified, and such modifications and modifications also fall within the protection scope of the appended claims.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A solid state hard disk controller is characterized in that the solid state hard disk controller is integrally packaged into a single chip and at least comprises a CPU, a main control interface controller, a flash memory controller and a cache unit, wherein,

2. The solid state hard disk controller according to claim 1, further comprising a cache controller, the cache controller being connected to the CPU, the main control interface controller, the flash controller and the cache unit, for controlling the cache unit according to an instruction of the CPU.

3. The solid state hard disk controller of claim 2, wherein an AXI bus is employed between the cache controller and the cache unit.

4. The solid state hard disk controller of claim 1 or 2, wherein the bandwidth of the cache unit is at least twice the data incoming bandwidth of the host interface side.

5. The solid state hard disk controller of claim 1 or 2, wherein the bandwidth of the cache unit is 4 GB/s.

6. The solid state hard disk controller of claim 1 or 2, wherein the master interface controller employs a PCEI, SATA or SAS interface.