CN112083878A - Disk controller - Google Patents

Disk controller Download PDF

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Publication number
CN112083878A
CN112083878A CN202010698223.5A CN202010698223A CN112083878A CN 112083878 A CN112083878 A CN 112083878A CN 202010698223 A CN202010698223 A CN 202010698223A CN 112083878 A CN112083878 A CN 112083878A
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China
Prior art keywords
controller
module
main board
udma
flash memory
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Withdrawn
Application number
CN202010698223.5A
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Chinese (zh)
Inventor
张�杰
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Shanghai Bumo Automation Equipment Co ltd
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Shanghai Bumo Automation Equipment Co ltd
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Priority to CN202010698223.5A priority Critical patent/CN112083878A/en
Publication of CN112083878A publication Critical patent/CN112083878A/en
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0674—Disk device
    • G06F3/0676—Magnetic disk device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

The invention discloses a disk controller, which comprises a first main board, a second main board and a third main board, wherein the first main board comprises a command analysis module, a UDMA (universal serial bus access) mode selection module, a double-clock generator and a clock switching module; the second mainboard comprises a CPU, a main control interface controller, a flash memory controller and a cache module; the third main board comprises an SRAM controller, a data buffer area, a register controller, a configuration and state register, a subchannel controller, ECC hardware error correction logic, a checking module, an out-of-band data processing module and an NAND flash memory interface. According to the invention, through the arrangement of the first main board, the second main board and the third main board, the read-write efficiency of the disk controller is effectively increased through the division and cooperation among the first main board, the second main board and the third main board, and the workload of each main board is reduced through the arrangement of the first main board, the second main board and the third main board, so that the working loss of each main board is reduced, and the service life of the disk controller is further prolonged.

Description

Disk controller
Technical Field
The invention belongs to the technical field of automation control, and particularly relates to a disk controller.
Background
The magnetic disk is the main storage device of the computer system periphery, and at present, the read-write control of the magnetic disk data must depend on the computer system standard peripheral interface and the computer operating system. The computer communicates with the magnetic disk through a standard peripheral circuit interface connected with a bus thereof, a designer writes a software driver which can be executed by the computer to configure the magnetic disk, and then the computer organizes the storage and reading of the magnetic disk data by running the driver, however, various magnetic disk controllers on the market still have various problems.
Although the disk array controller disclosed in the publication No. CN103853498A achieves flexibility and convenience in use and high security and reliability, it does not solve the problems of the existing disk controller: the magnetic disk controller has low read-write efficiency and poor anti-interference capability, which affects the service life of the magnetic disk controller.
Disclosure of Invention
It is an object of the present invention to provide a disk controller to solve the above-mentioned problems in the background art.
In order to achieve the purpose, the invention provides the following technical scheme: the utility model provides a disk controller, includes first mainboard, second mainboard and third mainboard, its characterized in that: the first mainboard comprises a command analysis module, a UDMA mode selection module, a double-clock generator and a clock switching module, wherein the command analysis module is used for receiving a detection command, the UDMA mode selection module is used for setting a corresponding clock mode and sending the clock mode to the clock switching module, the double-clock generator is used for simultaneously sending two clock signals with frequencies of 100M and 133M and sending the clock signals to the clock switching module, and the clock switching module is used for selecting one clock signal in 100M/133M according to the clock mode sent by the UDMA mode selection module and setting a multiple value of a reference clock;
the second main board comprises a CPU, a main control interface controller, a FLASH memory controller and a cache module, the CPU is connected with the main control interface controller, the FLASH memory controller and the cache module and is used for controlling the work of the third main board, the main control interface controller is connected with an external host and is used for carrying out data transmission with the external host, the cache module adopts an SRAM and is used for caching data received by the main control interface controller, and the FLASH memory controller is connected with a FLASH and is used for storing the data in the cache module into the FLASH;
the third mainboard comprises an SRAM controller, a data buffer area, a register controller, a configuration and state register, a subchannel controller, ECC hardware error correction logic, an inspection module, an out-of-band data processing module and an NAND flash memory interface, wherein the SRAM controller is connected with and controls the data buffer area, the SRAM controller is connected with the ECC hardware error correction logic, the ECC hardware error correction logic is connected with the NAND flash memory interface, the register controller is connected with and controls the configuration and state register, the configuration and state register is connected with the subchannel controller, the configuration and state register is connected with the NAND flash memory interface, the inspection module is connected with the out-of-band data processing module, and the out-of-band data processing module is connected with the NAND flash memory interface.
Preferably, the reference clock multiple value set in the clock mode transmitted from the UDMA mode selection module includes UDMA 6133M 2, UDMA 5100M 2, UDMA 4133M 4, UDMA 4100M 3, UDMA 3133M 6, UDMA 2133M 8, UDMA 2100M 6, UDMA 1100M 8, UDMA 0133M 16, and UDMA 0100M 12.
Preferably, the second motherboard further includes a cache controller, the cache controller is connected to the CPU, the main control interface controller, the flash controller, and the cache module, and the cache controller is configured to control the cache module according to an instruction of the CPU.
Preferably, an AXI bus is adopted between the cache controller and the cache module, and the master interface controller adopts a PCEI, SATA or SAS interface.
Preferably, the data buffer is 4 data buffers with 4 kbytes, the 4 data buffers with 4 kbytes can receive data from the NAND flash memory interface, and the SRAM controller can operate on the 4 data buffers with 4 kbytes.
Preferably, the NAND flash memory interface is connected to a NAND flash memory chip, and the configuration and status register is configured to support two-plane operation on the NAND flash memory chip, adjust a microinstruction sent to the NAND flash memory chip, and adjust corresponding timing information according to different NAND flash memory chips.
Preferably, the out-of-band data processing module is configured to store mapping information and function information corresponding to each NAND flash physical page of the NAND flash interface, and the check module is configured to check an information error of the out-of-band data processing module.
Preferably, the ECC hardware error correction logic is configured to perform decoding check on the data in the data buffer, and correct a data error, and the ECC hardware error correction logic supports 8/12/16/24-bit configurable BCH hardware error correction in the 1K data.
Compared with the prior art, the invention has the beneficial effects that:
(1) according to the invention, through the arrangement of the first main board, the second main board and the third main board and the division cooperation among the first main board, the second main board and the third main board, the reading and writing efficiency of the disk controller is effectively increased, and through the arrangement of the first main board, the second main board and the third main board, the anti-interference capability of the disk controller is increased, and simultaneously the workload of each main board is reduced, so that the working loss of each main board is reduced, and the service life of the disk controller is further prolonged.
(2) The first mainboard is internally provided with a 133M and 100M double-clock generator, so that the disk controller can be flexibly matched with a UDMA transmission mode, and double clocks are selectively switched according to the rate mode of a mainboard UDMA interface, thereby realizing the low-cost compatibility of the disk controller and the mainboard with different UDMA transmission modes.
(3) The cache module in the second main board adopts SRAM, and the SRAM is used for replacing DRAM, so that the system structure of the second main board is optimized, the original three modules of main control, DRAM and FLASH are simplified into two modules of main control and FLASH, the layout and wiring of the second main board are optimized to a certain extent, the size is reduced, and the cost is greatly reduced.
(4) According to the invention, the NAND flash memory interface is arranged in the third main board, high-speed data transmission can be realized, the NAND flash memory is operated through the data buffer area, the bandwidth for reading the NAND flash memory data is improved, and meanwhile, the reconstruction of the mapping table of the disk controller can be accelerated through the out-of-band data processing module and the verification module.
Drawings
FIG. 1 is a block diagram of a first motherboard according to the present invention;
FIG. 2 is a block diagram of a second motherboard according to the present invention;
fig. 3 is a block diagram of a third main board according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
A disk controller comprises a first mainboard, a second mainboard and a third mainboard, wherein the first mainboard comprises a command analysis module, a UDMA mode selection module, a double-clock generator and a clock switching module, the command analysis module is used for receiving a detection command, the UDMA mode selection module is used for setting a corresponding clock mode and sending the clock mode to the clock switching module, the double-clock generator is used for simultaneously sending two clock signals with frequencies of 100M and 133M and sending the clock signals to the clock switching module, and the clock switching module is used for selecting one clock signal in 100M/133M according to the clock mode sent by the UDMA mode selection module and setting a multiple value of a reference clock;
the second main board comprises a CPU, a main control interface controller, a FLASH memory controller and a cache module, the CPU is connected with the main control interface controller, the FLASH memory controller and the cache module and is used for controlling the work of the third main board, the main control interface controller is connected with an external host and is used for carrying out data transmission with the external host, the cache module adopts an SRAM and is used for caching data received by the main control interface controller, and the FLASH memory controller is connected with a FLASH and is used for storing the data in the cache module into the FLASH;
the third mainboard comprises an SRAM controller, a data buffer area, a register controller, a configuration and state register, a subchannel controller, ECC hardware error correction logic, an inspection module, an out-of-band data processing module and an NAND flash memory interface, wherein the SRAM controller is connected with and controls the data buffer area, the SRAM controller is connected with the ECC hardware error correction logic, the ECC hardware error correction logic is connected with the NAND flash memory interface, the register controller is connected with and controls the configuration and state register, the configuration and state register is connected with the subchannel controller, the configuration and state register is connected with the NAND flash memory interface, the inspection module is connected with the out-of-band data processing module, and the out-of-band data processing module is connected with the NAND flash memory interface.
In this embodiment, the reference clock multiple value set in the clock mode transmitted from the UDMA mode selection module preferably includes UDMA 6133M 2, UDMA 5100M 2, UDMA 4133M 4, UDMA 4100M 3, UDMA 3133M 6, UDMA 2133M 8, UDMA 2100M 6, UDMA 1100M 8, UDMA 0133M 16, and UDMA 0100M 12.
In this embodiment, preferably, the second motherboard further includes a cache controller, the cache controller is connected to the CPU, the main control interface controller, the flash controller, and the cache module, and the cache controller is configured to control the cache module according to an instruction of the CPU.
In this embodiment, preferably, an AXI bus is used between the cache controller and the cache module, and the master interface controller uses an SATA interface.
In this embodiment, preferably, the data buffer is 4 data buffers with 4 kbytes, the 4 data buffers with 4 kbytes can receive data from the NAND flash memory interface, and the SRAM controller can operate the 4 data buffers with 4 kbytes.
In this embodiment, preferably, the NAND flash interface is connected to a NAND flash chip, and the configuration and status register is configured to support a two-plane operation on the NAND flash chip, adjust a microinstruction sent to the NAND flash chip, and adjust corresponding timing information according to different NAND flash chips.
In this embodiment, preferably, the out-of-band data processing module is configured to store mapping information and function information corresponding to each NAND flash physical page of the NAND flash interface, and the checking module is configured to check an information error of the out-of-band data processing module.
In this embodiment, preferably, the ECC hardware error correction logic is configured to perform decoding check on the data in the data buffer, and correct a data error, and the ECC hardware error correction logic supports 8/12/16/24-bit configurable BCH hardware error correction in the 1K data.
Example 2
A disk controller comprises a first mainboard, a second mainboard and a third mainboard, wherein the first mainboard comprises a command analysis module, a UDMA mode selection module, a double-clock generator and a clock switching module, the command analysis module is used for receiving a detection command, the UDMA mode selection module is used for setting a corresponding clock mode and sending the clock mode to the clock switching module, the double-clock generator is used for simultaneously sending two clock signals with frequencies of 100M and 133M and sending the clock signals to the clock switching module, and the clock switching module is used for selecting one clock signal in 100M/133M according to the clock mode sent by the UDMA mode selection module and setting a multiple value of a reference clock;
the second main board comprises a CPU, a main control interface controller, a FLASH memory controller and a cache module, the CPU is connected with the main control interface controller, the FLASH memory controller and the cache module and is used for controlling the work of the third main board, the main control interface controller is connected with an external host and is used for carrying out data transmission with the external host, the cache module adopts an SRAM and is used for caching data received by the main control interface controller, and the FLASH memory controller is connected with a FLASH and is used for storing the data in the cache module into the FLASH;
the third mainboard comprises an SRAM controller, a data buffer area, a register controller, a configuration and state register, a subchannel controller, ECC hardware error correction logic, an inspection module, an out-of-band data processing module and an NAND flash memory interface, wherein the SRAM controller is connected with and controls the data buffer area, the SRAM controller is connected with the ECC hardware error correction logic, the ECC hardware error correction logic is connected with the NAND flash memory interface, the register controller is connected with and controls the configuration and state register, the configuration and state register is connected with the subchannel controller, the configuration and state register is connected with the NAND flash memory interface, the inspection module is connected with the out-of-band data processing module, and the out-of-band data processing module is connected with the NAND flash memory interface.
In this embodiment, the reference clock multiple value set in the clock mode transmitted from the UDMA mode selection module preferably includes UDMA 6133M 2, UDMA 5100M 2, UDMA 4133M 4, UDMA 4100M 3, UDMA 3133M 6, UDMA 2133M 8, UDMA 2100M 6, UDMA 1100M 8, UDMA 0133M 16, and UDMA 0100M 12.
In this embodiment, preferably, an AXI bus is used between the cache controller and the cache module, and the master interface controller uses a PCEI interface.
In this embodiment, preferably, the data buffer is 4 data buffers with 4 kbytes, the 4 data buffers with 4 kbytes can receive data from the NAND flash memory interface, and the SRAM controller can operate the 4 data buffers with 4 kbytes.
In this embodiment, preferably, the ECC hardware error correction logic is configured to perform decoding check on the data in the data buffer, and correct a data error, and the ECC hardware error correction logic supports 8/12/16/24-bit configurable BCH hardware error correction in the 1K data.
Example 3
A disk controller comprises a first mainboard, a second mainboard and a third mainboard, wherein the first mainboard comprises a command analysis module, a UDMA mode selection module, a double-clock generator and a clock switching module, the command analysis module is used for receiving a detection command, the UDMA mode selection module is used for setting a corresponding clock mode and sending the clock mode to the clock switching module, the double-clock generator is used for simultaneously sending two clock signals with frequencies of 100M and 133M and sending the clock signals to the clock switching module, and the clock switching module is used for selecting one clock signal in 100M/133M according to the clock mode sent by the UDMA mode selection module and setting a multiple value of a reference clock;
the second main board comprises a CPU, a main control interface controller, a FLASH memory controller and a cache module, the CPU is connected with the main control interface controller, the FLASH memory controller and the cache module and is used for controlling the work of the third main board, the main control interface controller is connected with an external host and is used for carrying out data transmission with the external host, the cache module adopts an SRAM and is used for caching data received by the main control interface controller, and the FLASH memory controller is connected with a FLASH and is used for storing the data in the cache module into the FLASH;
the third mainboard comprises an SRAM controller, a data buffer area, a register controller, a configuration and state register, a subchannel controller, ECC hardware error correction logic, an inspection module, an out-of-band data processing module and an NAND flash memory interface, wherein the SRAM controller is connected with and controls the data buffer area, the SRAM controller is connected with the ECC hardware error correction logic, the ECC hardware error correction logic is connected with the NAND flash memory interface, the register controller is connected with and controls the configuration and state register, the configuration and state register is connected with the subchannel controller, the configuration and state register is connected with the NAND flash memory interface, the inspection module is connected with the out-of-band data processing module, and the out-of-band data processing module is connected with the NAND flash memory interface.
In this embodiment, preferably, the second motherboard further includes a cache controller, the cache controller is connected to the CPU, the main control interface controller, the flash controller, and the cache module, and the cache controller is configured to control the cache module according to an instruction of the CPU.
In this embodiment, preferably, the data buffer is 4 data buffers with 4 kbytes, the 4 data buffers with 4 kbytes can receive data from the NAND flash memory interface, and the SRAM controller can operate the 4 data buffers with 4 kbytes.
In this embodiment, preferably, the NAND flash interface is connected to a NAND flash chip, and the configuration and status register is configured to support a two-plane operation on the NAND flash chip, adjust a microinstruction sent to the NAND flash chip, and adjust corresponding timing information according to different NAND flash chips.
In this embodiment, preferably, the out-of-band data processing module is configured to store mapping information and function information corresponding to each NAND flash physical page of the NAND flash interface, and the checking module is configured to check an information error of the out-of-band data processing module.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (8)

1. The utility model provides a disk controller, includes first mainboard, second mainboard and third mainboard, its characterized in that: the first mainboard comprises a command analysis module, a UDMA mode selection module, a double-clock generator and a clock switching module, wherein the command analysis module is used for receiving a detection command, the UDMA mode selection module is used for setting a corresponding clock mode and sending the clock mode to the clock switching module, the double-clock generator is used for simultaneously sending two clock signals with frequencies of 100M and 133M and sending the clock signals to the clock switching module, and the clock switching module is used for selecting one clock signal in 100M/133M according to the clock mode sent by the UDMA mode selection module and setting a multiple value of a reference clock;
the second main board comprises a CPU, a main control interface controller, a FLASH memory controller and a cache module, the CPU is connected with the main control interface controller, the FLASH memory controller and the cache module and is used for controlling the work of the third main board, the main control interface controller is connected with an external host and is used for carrying out data transmission with the external host, the cache module adopts an SRAM and is used for caching data received by the main control interface controller, and the FLASH memory controller is connected with a FLASH and is used for storing the data in the cache module into the FLASH;
the third mainboard comprises an SRAM controller, a data buffer area, a register controller, a configuration and state register, a subchannel controller, ECC hardware error correction logic, an inspection module, an out-of-band data processing module and an NAND flash memory interface, wherein the SRAM controller is connected with and controls the data buffer area, the SRAM controller is connected with the ECC hardware error correction logic, the ECC hardware error correction logic is connected with the NAND flash memory interface, the register controller is connected with and controls the configuration and state register, the configuration and state register is connected with the subchannel controller, the configuration and state register is connected with the NAND flash memory interface, the inspection module is connected with the out-of-band data processing module, and the out-of-band data processing module is connected with the NAND flash memory interface.
2. A disk controller according to claim 1, wherein: the reference clock multiple values set in the clock mode transmitted from the UDMA mode selection module include UDMA 6133M 2, UDMA 5100M 2, UDMA 4133M 4, UDMA 4100M 3, UDMA 3133M 6, UDMA 2133M 8, UDMA 2100M 6, UDMA 1100M 8, UDMA 0133M 16, and UDMA 0100M 12.
3. A disk controller according to claim 1, wherein: the second main board further comprises a cache controller, the cache controller is connected with the CPU, the main control interface controller, the flash controller and the cache module, and the cache controller is used for controlling the cache module according to the instruction of the CPU.
4. A disk controller according to claim 1, wherein: an AXI bus is adopted between the cache controller and the cache module, and the master control interface controller adopts PCEI, SATA or SAS interface.
5. A disk controller according to claim 1, wherein: the data buffer area is 4 data buffer areas with 4K bytes, the 4 data buffer areas with 4K bytes can receive data from the NAND flash memory interface, and the SRAM controller can operate the 4 data buffer areas with 4K bytes.
6. A disk controller according to claim 1, wherein: the NAND flash memory interface is connected to the NAND flash memory chip, the configuration and status register is configured to support two-plane operation of the NAND flash memory chip, micro instructions sent to the NAND flash memory chip are adjusted, and corresponding time sequence information is adjusted according to different NAND flash memory chips.
7. A disk controller according to claim 1, wherein: the out-of-band data processing module is used for storing mapping information and function information corresponding to each NAND flash memory physical page of the NAND flash memory interface, and the verification module is used for verifying information errors of the out-of-band data processing module.
8. A disk controller according to claim 1, wherein: the ECC hardware error correction logic is used for decoding and checking the data in the data buffer and correcting data errors, and supports 8/12/16/24bit configurable BCH hardware error correction in 1K data.
CN202010698223.5A 2020-07-20 2020-07-20 Disk controller Withdrawn CN112083878A (en)

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CN202010698223.5A CN112083878A (en) 2020-07-20 2020-07-20 Disk controller

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Application Number Priority Date Filing Date Title
CN202010698223.5A CN112083878A (en) 2020-07-20 2020-07-20 Disk controller

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Application publication date: 20201215