CN110413233A - A kind of solid-state hard disk controller - Google Patents
A kind of solid-state hard disk controller Download PDFInfo
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- CN110413233A CN110413233A CN201910682417.3A CN201910682417A CN110413233A CN 110413233 A CN110413233 A CN 110413233A CN 201910682417 A CN201910682417 A CN 201910682417A CN 110413233 A CN110413233 A CN 110413233A
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- 230000010354 integration Effects 0.000 claims abstract description 5
- 238000004806 packaging method and process Methods 0.000 claims abstract description 5
- 239000007787 solid Substances 0.000 description 9
- 238000013461 design Methods 0.000 description 8
- 230000006872 improvement Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 238000013500 data storage Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
The invention discloses a kind of solid-state hard disk controllers, the solid-state hard disk controller integration packaging is single chip, including at least CPU, host interface controller, flash controller and cache unit, wherein, CPU is connected with host interface controller, flash controller and cache unit, for controlling the work of solid-state hard disk controller；Host interface controller is connected with external host, for carrying out data transmission with external host；Cache unit uses SRAM, for caching the received data of host interface controller；Flash controller is connected with FLASH, for storing the data in cache unit into FLASH.Compared with prior art, the invention proposes a kind of completely new SSD master cache frameworks, DRAM is substituted using SRAM, and caching is integrated among main control chip, to optimize the system structure of chip, placement-and-routing and the minification for optimizing PCB to a certain extent, greatly reduce hardware cost.
Description
Technical field
The present invention relates to memory technology field more particularly to a kind of solid-state hard disk controllers.
Background technique
Solid state hard disk (SSD) has become the storage equipment of current mainstream, is widely used in the data storage of every field.
Currently, the SSD framework of mainstream as shown in Figure 1, solid-state hard disk controller (SSD controller) be integration packaging chip (ASIC),
Host interface controller, flash controller and dram controller is arranged inside, wherein host interface controller (Host
Interface Controller) it comes into contacts with as front end with host, interface can make PCEI, the interfaces such as SATA, SAS；Flash memory
Controller (Flash Controller) is used as rear end to come into contacts with flash memory (FLASH) and completes data encoding and decoding and ECC verifying,
It is interconnected in addition there are also dram controller by the DRAM of AXI bus and individual packages, is used for data buffer storage.
In above-mentioned framework, DRAM is attached outside solid-state hard disk controller by PCB line to be external.Data are logical
It crosses host interface to be passed to, the permission of dram controller and backward CPU application transfer bus then writes data into the correspondence of DRAM
In address, and notify flash controller, data are deposited into FLASH by flash controller from taking-up in DRAM, just complete data
Storing process.Since the interface bandwidth of DRAM is generally incoming compared with data with roomy, so can continue to receive processing master at full speed
The read-write data of machine interface.
However, DRAM is expensive, usually also more expensive than the solid-state hard disk controller chip of integration packaging, this is undoubtedly improved
The hardware cost of SSD.Simultaneously as DRAM and chip use entirely different technique, can not be integrated in chip, therefore,
The placement space that upper PCB needs reserved DRAM is designed in solid state hard disk, master control needs to design the interface of external DRAM, leads to SSD
Size can not further reduce.
Therefore in view of the drawbacks of the prior art, it is really necessary to propose a kind of technical solution to solve skill of the existing technology
Art problem.
Summary of the invention
In view of this, using the thinking of SRAM substitution DRAM, and will delay it is necessory to provide a kind of solid-state hard disk controller
Memory cell has been integrated in the inside of solid-state hard disk controller, so that dependence of the system to DRAM has been completely free of, in solid state hard disk
It is not necessarily to additional DRAM in design, and the volume and reduced cost of solid state hard disk can be further reduced.
In order to solve technical problem of the existing technology, technical scheme is as follows:
A kind of solid-state hard disk controller, the solid-state hard disk controller integration packaging are single chip, include at least CPU, master
Control interface controller, flash controller and cache unit, wherein
The CPU is connected with host interface controller, flash controller and cache unit, for controlling solid state hard disk control
The work of device processed；
The host interface controller is connected with external host, for carrying out data transmission with external host；
The cache unit uses SRAM, for caching the received data of host interface controller；
The flash controller is connected with FLASH, for storing the data in the cache unit into FLASH.
Scheme as a further improvement also sets up cache controller, the cache controller and CPU, host interface control
Device processed, flash controller are connected with cache unit, for controlling the cache unit according to the instruction of CPU.
Scheme as a further improvement uses AXI bus between the cache controller and cache unit.
Scheme as a further improvement, the data that the bandwidth of the cache unit is at least host interface port are passed to bandwidth
Twice.
Scheme as a further improvement, the bandwidth of the cache unit are 4GB/s.
Scheme as a further improvement, the host interface controller use PCEI, SATA or SAS interface.
Compared with prior art, it the invention proposes a kind of completely new SSD master cache framework, is substituted using SRAM
DRAM module, and caching is integrated among main control chip, to optimize the system structure of chip, from original master control,
The big module reduction of DRAM, FLASH tri- optimizes placement-and-routing and the contracting of PCB at master control and the big module of FLASH two to a certain extent
Small size greatly reduces hardware cost.
Detailed description of the invention
Fig. 1 is the block architecture diagram of solid state hard disk in the prior art.
Fig. 2 is the functional block diagram of solid-state hard disk controller of the present invention.
Fig. 3 is the functional block diagram of the solid-state hard disk controller of another embodiment of the present invention.
Following specific embodiment will further illustrate the present invention in conjunction with above-mentioned attached drawing.
Specific embodiment
Technical solution provided by the invention is described further below with reference to attached drawing.
In the prior art, SSD is had in the process of running using DRAM is arrived, so as to cause solid state hard disk increased costs.
For the technological deficiency, the invention proposes a kind of completely new SSD master cache frameworks to show solid-state of the present invention referring to fig. 2
The functional block diagram of hard disk controller, which is single chip, interior to include at least CPU, master control
Interface controller, flash controller and cache unit, wherein
The CPU is connected with host interface controller, flash controller and cache unit, for controlling solid state hard disk control
The work of device processed；
The host interface controller is connected using the interfaces such as PCEI, SATA or SAS with external host, for it is outer
Portion's host carries out data transmission；
The cache unit uses SRAM, for caching the received data of host interface controller；
The flash controller is connected with FLASH, for storing the data in the cache unit into FLASH.
In above-mentioned technical proposal, DRAM is substituted using SRAM, since SRAM and main control chip use identical technique, from
And caching can be integrated among main control chip, without adding DRAM outside in solid state hard disk design.
Referring to Fig. 3, it is shown the functional block diagram of the solid-state hard disk controller of another embodiment of the present invention, is also set up slow
Memory controller, the cache controller are connected with CPU, host interface controller, flash controller and cache unit, are used for root
The cache unit is controlled according to the instruction of CPU.Control cache unit, specific controlling mechanism can be more convenient by cache controller
It is as follows:
Assuming that the bandwidth of cache unit is 4GB/s, the writing rate of host interface is 1GB/s, and data are passed by host interface
Enter, host interface controller is responsible for that incoming data are decoded and are verified, and then cache unit controller is notified there are data
It needs to be passed to, for cache unit controller then to the right to use of CPU application system bus, cache unit controller obtains system bus
After the right to use, directly incoming data will be needed to be directly stored in cache unit and notify flash controller, then flash memory controls
Data taking-up in cache unit is directly written in FLASH by device.Since the band of cache unit is wider than 2 times of host interface
The data at end are passed to bandwidth, so the design will not reduce the data transmission performance of hard disk.Simplified design and cloth well
The work of office's wiring, reduces the cost of design.
In a preferred embodiment, DRAM is substituted using cache unit structure and with existing DRAM using identical
High speed AXI bus structures, in design by cache unit integrated design inside main control chip, and simulate in SOC with
The identical AXI transfer bus of DRAM is mutually communicated.Secondary cache unit it possess data bandwidth identical with DRAM and number
According to processing speed.Due to using AXI bus structures, storage dilatation can be carried out by the external DRAM of the bus, to cancel
The interface circuit of the external part DRAM and the DRAM connected outside are substituted using cache unit, and are able to maintain to original framework
Compatibility.
The above description of the embodiment is only used to help understand the method for the present invention and its core ideas.It should be pointed out that pair
For those skilled in the art, without departing from the principle of the present invention, the present invention can also be carried out
Some improvements and modifications, these improvements and modifications also fall within the scope of protection of the claims of the present invention.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (6)
1. a kind of solid-state hard disk controller, which is characterized in that the solid-state hard disk controller integration packaging is single chip, is at least wrapped
Include CPU, host interface controller, flash controller and cache unit, wherein
The CPU is connected with host interface controller, flash controller and cache unit, for controlling solid-state hard disk controller
Work；
The host interface controller is connected with external host, for carrying out data transmission with external host；
The cache unit uses SRAM, for caching the received data of host interface controller；
The flash controller is connected with FLASH, for storing the data in the cache unit into FLASH.
2. solid-state hard disk controller according to claim 1, which is characterized in that also set up cache controller, the caching
Controller is connected with CPU, host interface controller, flash controller and cache unit, for controlling institute according to the instruction of CPU
State cache unit.
3. solid-state hard disk controller according to claim 2, which is characterized in that the cache controller and cache unit it
Between use AXI bus.
4. solid-state hard disk controller according to claim 1 or 2, which is characterized in that the bandwidth of the cache unit is at least
It is twice of the incoming bandwidth of data of host interface port.
5. solid-state hard disk controller according to claim 1 or 2, which is characterized in that the bandwidth of the cache unit is
4GB/s。
6. solid-state hard disk controller according to claim 1 or 2, which is characterized in that the host interface controller uses
PCEI, SATA or SAS interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910682417.3A CN110413233B (en) | 2019-07-26 | Solid state disk controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910682417.3A CN110413233B (en) | 2019-07-26 | Solid state disk controller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110413233A true CN110413233A (en) | 2019-11-05 |
| CN110413233B CN110413233B (en) | 2024-10-29 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113778344A (en) * | 2021-04-25 | 2021-12-10 | 联芸科技（杭州）有限公司 | Solid state disk and write operation method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103631728A (en) * | 2012-08-27 | 2014-03-12 | 苹果公司 | Fast execution of refresh commands using adaptive compression ratio |
| CN104035897A (en) * | 2014-06-12 | 2014-09-10 | 上海新储集成电路有限公司 | Storage controller |
| CN104346287A (en) * | 2013-08-09 | 2015-02-11 | Lsi公司 | Trim mechanism using multi-level mapping in a solid-state media |
| CN109947694A (en) * | 2019-04-04 | 2019-06-28 | 上海威固信息技术股份有限公司 | A kind of Reconfigurable Computation storage fusion flash memory control system |
| CN210155650U (en) * | 2019-07-26 | 2020-03-17 | 杭州电子科技大学 | Solid state hard disk controller |
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103631728A (en) * | 2012-08-27 | 2014-03-12 | 苹果公司 | Fast execution of refresh commands using adaptive compression ratio |
| CN104346287A (en) * | 2013-08-09 | 2015-02-11 | Lsi公司 | Trim mechanism using multi-level mapping in a solid-state media |
| CN104035897A (en) * | 2014-06-12 | 2014-09-10 | 上海新储集成电路有限公司 | Storage controller |
| CN109947694A (en) * | 2019-04-04 | 2019-06-28 | 上海威固信息技术股份有限公司 | A kind of Reconfigurable Computation storage fusion flash memory control system |
| CN210155650U (en) * | 2019-07-26 | 2020-03-17 | 杭州电子科技大学 | Solid state hard disk controller |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113778344A (en) * | 2021-04-25 | 2021-12-10 | 联芸科技（杭州）有限公司 | Solid state disk and write operation method |
| US12045498B2 (en) | 2021-04-25 | 2024-07-23 | Maxio Technology (Hangzhou) Co., Ltd. | Solid state drive and write operation method |
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