CN201218944Y - Structure for implementing flash memory controller caching by double-port RAM - Google Patents
Structure for implementing flash memory controller caching by double-port RAM Download PDFInfo
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- CN201218944Y CN201218944Y CNU2008200295510U CN200820029551U CN201218944Y CN 201218944 Y CN201218944 Y CN 201218944Y CN U2008200295510 U CNU2008200295510 U CN U2008200295510U CN 200820029551 U CN200820029551 U CN 200820029551U CN 201218944 Y CN201218944 Y CN 201218944Y
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Abstract
The utility model relates to a construction for implementing a high-speed flash controller cache by a dual-port RAM, comprising an IDE interface control logic, an IDE register, an IDE cache region, a processor, a Flash interface control logic, a Flash cache region and a FPGA peripheral circuit, wherein the IDE register and the IDE cache region constructs an IDE interface cache region, the IDE interface cache region and the Flash cache region both comprises two fully independent control ports. The utility model is capable of implementing random address access, and has high efficiency in data access.
Description
Technical field
The utility model relates to the structure that a kind of FPGA of use realizes high speed flash controller buffer memory, is specifically related to the structure that a kind of FPGA of use built-in dual-port RAM is realized high speed flash controller buffer memory.
Background technology
FPGA is the abbreviation of English Field Programmable Gate Array, i.e. field programmable gate array, and it is the product that further develops on the basis of programming devices such as PAL, GAL, EPLD.Because the storage medium of flash memory electric board is the FLASH chip, core component as the flash memory electric board, flash controller is undertaken the management role of whole electric board, frequency of utilization is very high in the course of work that is buffered in entire controller of flash controller, often needs to change the content of certain byte in the blocks of data.Present known use FPGA realizes that the method for flash controller buffer memory is to use FIFO, that is: first in first out buffer memory, it is the data of writing into earlier, when reading, read earlier, therefore can read many data of formerly writing in the time of will reading certain at random data, also need to screen these data, very inconvenient in the practical application.Present stage, in data transmission procedure, show as: can't realize the random address read-write, can only read and write in order that it is very inconvenient to use, the efficient of reading and writing data is very low.
Summary of the invention
The structure that the purpose of this utility model has been to provide a kind of FPGA of use built-in dual-port RAM to realize the flash controller buffer memory, it has solved can't realize the random address read-write in the background technology, use the low-down technical matters of efficient of inconvenience and reading and writing data.
Technical solution of the present utility model is:
A kind of dual port RAM is realized the structure of high speed flash controller buffer memory, comprises ide interface steering logic, IDE register, IDE buffer area, processor, Flash interface control logic, Flash buffer area and FPGA peripheral circuit, and its special character is:
Wherein IDE register and IDE buffer area constitute an ide interface buffer area, and described ide interface buffer area comprises two fully independently control mouths;
Described ide interface steering logic is passed through one of them control mouth and is connected with the ide interface buffer area, and described processor is connected with the ide interface buffer area by another control mouth;
Described FLASH buffer area also comprises two fully independently control mouths;
One of them control mouth that described Flash interface control logic passes through the FLASH buffer area is connected with the FLASH buffer area, and described processor is connected with the FLASH buffer area by another control mouth.
Above-mentioned ide interface buffer area and FLASH buffer area are independently of one another.
At least two groups connect identical FLASH buffer area and Flash control interface logic.
Comprise read data register, write data register, error register in the above-mentioned IDE register, read the sector number register, write the sector number register, read the logic sector number register, write logic sector number register read cylinder number register, write the cylinder number register, read the cylinder number register, write the cylinder number register, reading head register, write head register, status register and command register.
Advantage of the present utility model is: can realize the random address read-write, the efficient height of reading and writing data, and can share the storage data, promptly a storer is equipped with two cover address wire, data line and control lines, allow the simultaneously asynchronous storage unit access of two processors, promptly ide interface can the random access buffer unit, and the processor in the controller also can the random access buffer unit simultaneously, reach in flash controller flexible control, improve data transmission efficiency buffer memory.
Description of drawings
Fig. 1 is a schematic block circuit diagram of the present utility model.
Embodiment
Referring to Fig. 1, a kind of dual port RAM is realized the structure of high speed flash controller buffer memory, comprise ide interface steering logic, IDE register, IDE buffer area, processor, Flash interface control logic, FLASH buffer area and FPGA peripheral circuit, wherein IDE register and IDE buffer area constitute an ide interface buffer area, and described ide interface buffer area comprises two fully independently control mouths; The ide interface steering logic is passed through one of them control mouth and is connected with the ide interface buffer area, and processor is connected with the ide interface buffer area by another control mouth; The FLASH buffer area also comprises two fully independently control mouths; The Flash interface control logic is connected with the FLASH buffer area by one of them control mouth of FLASH buffer area, described processor is connected with the FLASH buffer area by another control mouth, ide interface buffer area and FLASH buffer area are independently of one another, there are two groups to connect identical FLASH buffer area and Flash control interface logic, can expand many groups simultaneously and connect identical FLASH buffer area and Flash control interface logic.
Wherein, comprise in the IDE register read data register, write data register, error register, read the sector number register, write the sector number register, read the logic sector number register, write logic sector number register read cylinder number register, write the cylinder number register, read the cylinder number register, write the cylinder number register, reading head register, write head register, status register and command register.
At first flash controller is passive equipment in the course of the work, the flash controller power-on reset enters idle condition after finishing self check, communication between last microcomputer IDE controller and the flash controller is by last microcomputer IDE controller the IDE register of flash controller to be read and write to realize, when last microcomputer IDE controller will carry out data transmission, main frame at first sends command parameter to the IDE of flash controller register, send order to command register then, the execution of initiation command after flash controller receives orders.
Last microcomputer IDE controller is from flash controller reading of data process:
A) according to the sector position that will read, last microcomputer IDE controller sends command parameter, and the ide interface steering logic receives data and leaves the ide interface buffer area in, enters next step behind the equipment READY signal location 1 of last microcomputer IDE controller wait flash controller.
B) go up microcomputer IDE controller and send out read command to flash controller, the ide interface steering logic writes the ide interface buffer area with command word, and the ide interface steering logic enters next step after the position busy signal of IDE status register is set simultaneously.
C) the ide interface steering logic is sent out look-at-me to processor, and processor is resolved from sense command of ide interface buffer area and parameter initiation command thereof.
D) to be resolved to be read command to processor, and processor is write the FLASH buffer area to the physical address of the sector that will read, and processor is sent out trigger pip and given the FLASH interface control logic simultaneously, and notice FLASH interface control logic has order to arrive.
E) the FLASH interface control logic is received trigger pip, from sense command of FLASH buffer area and parameter thereof, resolve command, FLASH interface control logic sense data and be stored in the FLASH buffer area from the Nand Flash chip of appointment enters next step after running through data designated then.
F) the FLASH interface control logic writes the FLASH buffer area to this result who reads, and sends out look-at-me to processor simultaneously, and the data of telling processor to read have been put into the FLASH buffer area.
G) after processor receives look-at-me, data are read the ide interface buffer area from the FLASH buffer area, after data shifted and finish, processor was sent out trigger pip to the ide interface steering logic, tells ide interface steering logic DSR.
H) after the ide interface steering logic is received trigger pip, the position busy signal in the clear control register, upwards microcomputer IDE controller is sent out look-at-me simultaneously.
I) go up microcomputer IDE controller and receive look-at-me, beginning fetch equipment register is if microcomputer IDE controller reading of data on the DSR runs through this subcommand of end up to all data.
Last microcomputer IDE controller writes data procedures from flash controller, specifically may further comprise the steps
A) according to the sector position that will write, last microcomputer IDE controller sends command parameter, and the ide interface steering logic receives data and leaves the ide interface buffer area in, enters next step behind the equipment READY signal location 1 of last microcomputer IDE controller wait flash controller.
B) go up microcomputer IDE controller and send out write order to flash controller, the ide interface steering logic writes the ide interface buffer area with command word, enters next step after the ide interface steering logic is provided with IDE mode register data request position simultaneously.
C) going up microcomputer IDE controller sends data and is saved in the ide interface buffer area to flash controller by the ide interface steering logic, after last microcomputer IDE control sends data, the ide interface steering logic is provided with the position busy signal in the status register and the request signal that clears data, and the ide interface steering logic is sent out look-at-me to processor simultaneously.
D) after processor receives look-at-me, resolve from sense command of ide interface buffer area and parameter initiation command thereof, it is write order that processor is resolved to, processor is write the FLASH buffer area to the physical address of the sector that will write, data are read the FLASH buffer area from the ide interface buffer area, after data shifted and finish, processor was sent out trigger pip and is given the FLASH interface control logic simultaneously, and notice FLASH interface control logic has order to arrive.
E) the FLASH interface control logic is received trigger pip, from sense command of FLASH buffer area and parameter thereof, resolve command, the FLASH interface control logic is write the data in the FLASH buffer area in the fixed NandFlash chip then, enters next step after having write data designated.
F) the FLASH interface control logic writes the FLASH buffer area to the result phase of this write order, sends out look-at-me to processor simultaneously, and the data of telling processor to write have been write in the Nand Flash chip;
G) after processor receives look-at-me, read the status register that the result of this command execution writes from the FLASH buffer area, processor is sent out trigger pip to the ide interface steering logic simultaneously, tells ide interface steering logic data to write and finishes.
No datat transmission command implementation:
A) go up microcomputer IDE controller and send command parameter, the ide interface steering logic of flash controller receives data and leaves the ide interface buffer area in, enters next step behind the equipment READY signal location 1 of last microcomputer IDE controller wait flash controller.
B) go up microcomputer IDE controller and send order to flash controller, the ide interface steering logic of flash controller writes the ide interface buffer area with command word.Simultaneously the ide interface steering logic enters next step after the position busy signal of IDE status register is set
C) the ide interface steering logic of flash controller is sent out look-at-me to processor, after processor receives look-at-me, resolves from sense command of ide interface buffer area and parameter initiation command thereof.
D) to be resolved to be the order of no datat transmission command to processor, and processor begins fill order, the result of command execution is put in the status register sends out trigger pip to the ide interface steering logic simultaneously.
E) after the ide interface steering logic is received trigger pip, the position busy signal in the clear control register, upwards microcomputer IDE controller is sent out look-at-me simultaneously.
F) go up microcomputer IDE controller and receive look-at-me, beginning fetch equipment register finishes this subcommand.
Claims (4)
1. the structure of a dual port RAM realization high speed flash controller buffer memory comprises ide interface steering logic, IDE register, IDE buffer area, processor, Flash interface control logic, FLASH buffer area and FPGA peripheral circuit, it is characterized in that:
Wherein IDE register and IDE buffer area constitute an ide interface buffer area, and described ide interface buffer area comprises two fully independently control mouths;
Described ide interface steering logic is passed through one of them control mouth and is connected with the ide interface buffer area, and described processor is connected with the ide interface buffer area by another control mouth;
Described FLASH buffer area also comprises two fully independently control mouths;
One of them control mouth that described Flash interface control logic passes through the FLASH buffer area is connected with the FLASH buffer area, and described processor is connected with the FLASH buffer area by another control mouth.
2. realize the structure of high speed flash controller buffer memory according to the described dual port RAM of claim 1, it is characterized in that: described ide interface buffer area and FLASH buffer area are independently of one another.
3. according to the structure of claim 1 or 2 arbitrary described dual port RAMs realization high speed flash controller buffer memorys, it is characterized in that: comprise that at least two groups connect identical FLASH buffer area and Flash control interface logic.
4. realize the structure of high speed flash controller buffer memory according to the described dual port RAM of claim 3, it is characterized in that: comprise read data register, write data register, error register in the described IDE register, read the sector number register, write the sector number register, read the logic sector number register, write logic sector number register read cylinder number register, write the cylinder number register, read the cylinder number register, write the cylinder number register, reading head register, write head register, status register and command register.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008200295510U CN201218944Y (en) | 2008-07-03 | 2008-07-03 | Structure for implementing flash memory controller caching by double-port RAM |
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| Application Number | Priority Date | Filing Date | Title |
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| CNU2008200295510U CN201218944Y (en) | 2008-07-03 | 2008-07-03 | Structure for implementing flash memory controller caching by double-port RAM |
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| CN201218944Y true CN201218944Y (en) | 2009-04-08 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102306124A (en) * | 2011-08-01 | 2012-01-04 | 深圳市文鼎创数据科技有限公司 | Method for implementing hardware driver layer of Nand Flash chip |
| CN103631176A (en) * | 2013-08-30 | 2014-03-12 | 天津大学 | FPGA-based ultrahigh-speed industrial controller |
| CN110727637A (en) * | 2019-12-18 | 2020-01-24 | 广东高云半导体科技股份有限公司 | FPGA chip and electronic equipment |
| CN111679599A (en) * | 2020-05-22 | 2020-09-18 | 中国航空工业集团公司西安航空计算技术研究所 | High-reliability exchange method for CPU and DSP data |
-
2008
- 2008-07-03 CN CNU2008200295510U patent/CN201218944Y/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102306124A (en) * | 2011-08-01 | 2012-01-04 | 深圳市文鼎创数据科技有限公司 | Method for implementing hardware driver layer of Nand Flash chip |
| CN103631176A (en) * | 2013-08-30 | 2014-03-12 | 天津大学 | FPGA-based ultrahigh-speed industrial controller |
| CN103631176B (en) * | 2013-08-30 | 2017-01-25 | 天津大学 | FPGA-based ultrahigh-speed industrial controller |
| CN110727637A (en) * | 2019-12-18 | 2020-01-24 | 广东高云半导体科技股份有限公司 | FPGA chip and electronic equipment |
| CN111679599A (en) * | 2020-05-22 | 2020-09-18 | 中国航空工业集团公司西安航空计算技术研究所 | High-reliability exchange method for CPU and DSP data |
| CN111679599B (en) * | 2020-05-22 | 2022-01-25 | 中国航空工业集团公司西安航空计算技术研究所 | High-reliability exchange method for CPU and DSP data |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: XI AN KEYWAY TECHNOLOGY CO., LTD. Free format text: FORMER NAME: XI AN QIVI TEST + CONTROL TECHNOLOGY CO., LTD. |
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| CP01 | Change in the name or title of a patent holder |
Address after: Chibi 8 No. 710077 Shaanxi province science and technology high tech District of Xi'an City Jinye Road No. 69 business development park C District Patentee after: Xi'an Keyway Technology Co.,Ltd. Address before: Chibi 8 No. 710077 Shaanxi province science and technology high tech District of Xi'an City Jinye Road No. 69 business development park C District Patentee before: Xi'an Qivi Test & Control Technology Co., Ltd. |
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| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090408 Termination date: 20120703 |