CN206557758U - A kind of NAND FLASH storage chip array control unit expansible based on FPGA - Google Patents
A kind of NAND FLASH storage chip array control unit expansible based on FPGA Download PDFInfo
- Publication number
- CN206557758U CN206557758U CN201720235609.6U CN201720235609U CN206557758U CN 206557758 U CN206557758 U CN 206557758U CN 201720235609 U CN201720235609 U CN 201720235609U CN 206557758 U CN206557758 U CN 206557758U
- Authority
- CN
- China
- Prior art keywords
- nand flash
- flash storage
- data
- storage chip
- control unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Abstract
The utility model is related to a kind of NAND FLASH storage chip array control unit expansible based on FPGA.The utility model is made up of host computer control module and NAND FLASH storage chip controller modules, using single NAND FLASH storage chips controller as core, parallel work-flow multi-disc NAND FLASH storage chips, avoid the stationary problem produced by multiple controllers, add double buffering and pipelining simultaneously, the access rate of data is improved, the operation to NAND FLASH storage chip arrays is completed, realizes the storage to high-speed high capacity data.The more complicated stationary problem of the utility model presence of overcoming over.The high data access speed of the utility model, realizes the control to NAND FLASH storage chip arrays.
Description
Technical field
The utility model is related to Large Copacity and high data rate technical field of memory, more particularly to a kind of FPGA that is based on can expand
The NAND FLASH storage chip array control units of exhibition.
Background technology
With developing rapidly with information industry to call data storage more and more higher for electronic information technology, each social row
Industry is increasing to the demand of Mass Digital Storage System, promotes mass data storage technology advances.Data are deposited
The development of storage technology is mainly made up of the development of storage medium and the aspect of development two of data transmission interface.90 years last century
Start to develop Large Copacity solid-state memory and put it into commercial operation for recording equipment manufacturer, limited by integrated level and price, nowadays greatly
Capacity solid-state memory is seldom using sram chip as primary storage medium, and the NAND FLASH based on flash memory technology are deposited
Chip is stored up because its price is low, density is high and efficiency high advantage has already taken up dominant position.Deposited using NAND Flash
Chip is stored up as the solid-state disk of storage medium, than traditional storage device more can the changing of bearing temperature, machinery vibration and punching
Hit, while it is higher to have the advantages that little power consumption, storage density lift fast, reliability, it is easy to accomplish the storage of high speed Large Copacity.
Meanwhile, with the appearance of some high-speed buses of PCIe, RapidIO and RocketIO, the data access band of mass-storage system
Wide also constantly lifting.NAND FLASH storage chips structure is low per bit cost, with higher performance, and can be as disk one
Sample can easily be upgraded by interface.In addition, the memory capacity of NAND FLASH storage chips improves three-to-four-fold per annual meeting, and
Package dimension is being reduced, and monolithic read-write speed is relatively low, can be carried using multi-disc NAND FLASH storage chips formation array structure
High data rate and memory capacity.
Before the present utility model, use popular based on NAND FLASH to improve data storage rate
The high speed data transfer and memory technology of storage chip, mainly employ streamline storage mode of operation and data/address bus simultaneously
The technology of row extension, its speed is even up to several GB/S up to hundreds of MB/S, and capacity is also up to the ranks of T million.
But, the control logic of NAND FLASH storage chips is more complicated, also very strict to timing requirements, directly grasps
Make NAND FLASH storage chip difficulty big, it is therefore desirable to which the controller of design specialized to carry out NAND FLASH storage chips
Basic read-write erasing operation.At present, the control to NAND FLASH storage chips has developed into multichannel from single channel,
Access speed is further improved, and the read-write of most of multichannels is realized by increasing the number of controller, this to set
Although meter method also can parallel work-flow multi-disc NAND FLASH storage chips, more complicated stationary problem can be brought.
Utility model content
The purpose of this utility model, which is that, overcomes drawbacks described above, develops a kind of NAND FLASH expansible based on FPGA
Storage chip array control unit.
The technical solution adopted in the utility model is：
A kind of NAND FLASH storage chip array control unit expansible based on FPGA, it is mainly characterized by：
Described whole system is made up of host computer control module and NAND FLASH storage chip controller modules, parallel control multi-disc
NAND FLASH storage chips, the NAND FLASH storage chips array control unit include Logic control module, two
Data buffer zone module, register group and interface module；The NAND FLASH storage chips controller module is used to connect
Host module and NAND FLASH storage chips；The Logic control module is used to produce and NAND FLASH storage chip kissings
The time sequential routine of conjunction；Described two data buffer zone modules are used for the caching of data and realize ping-pong operation；The register
Group sets order, state, address and configuration parameter for depositing the interior of NAND FLASH storage chips；The host computer control module bag
The order that NAND FLASH storage chips are accessed for producing and data are included to controller, the state fed back by controller is connected and believes
Number and data message；The interface module is used for the soap-free emulsion polymeization interface for being mapped as a similar SRAM.
The host computer control module be used to producing the order for accessing NAND FLASH and data to controller and receive by
The status signal and data message of controller feedback.
The NAND FLASH storage chips controller module is used to connect host module and NAND FLASH storage chips,
The order of Receiving Host transmission and data and concurrently manipulation multi-disc NAND FLASH storage chips, while feedback states signal
To main frame.
The Logic control module is used for the time sequential routine produced and NAND FLASH storage chips match, including reads
Write, wipe, reading ID and reset the sequential of operation.
Described two data buffer zone modules are used for the caching of data and realize ping-pong operation.
The register group sets order, state, address and configuration parameter for depositing the interior of NAND FLASH storage chips.
The interface module is used for the soap-free emulsion polymeization interface for being mapped as a similar SRAM.
The beneficial effects of the utility model are that the utility model is based on NAND FLASH storage chips battle array expansible FPGA
The design of row controller produces the order for accessing NAND FLASH storage chip arrays by host computer control module and data message is given
Controller, order and data that NAND FLASH storage chip array control units Receiving Host is sent, and to NAND FLASH
Storage chip array does corresponding manipulation, while feedback states signal is to main frame.The utility model realizes single controller simultaneously
Row operation multi-disc NAND FLASH storage chips, solve the stationary problem of multiple controller operations, while adding streamline
Technology and ping-pong operation, further increase data access speed, realize the control to NAND FLASH storage chip arrays.
Brief description of the drawings
Fig. 1 --- the utility model system framework schematic diagram.
Fig. 2 --- the utility model major state shifts schematic diagram.
Fig. 3 --- the utility model page programming state transfer schematic diagram.
Fig. 4 --- the utility model page read states transfer schematic diagram.
Fig. 5 --- the utility model block erase status shifts schematic diagram.
Fig. 6 --- the utility model reads ID states transfer schematic diagram.
Fig. 7 --- the utility model reset state shifts schematic diagram.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is carried out
Clearly and completely describe.
Technical thought of the present utility model is：
Using single NAND FLASH storage chips controller as core, parallel work-flow multi-disc NAND FLASH storage chips,
The stationary problem produced by multiple controllers is avoided, while adding double buffering and pipelining, number is effectively improved
According to access rate, complete operation to NAND FLASH storage chip arrays, realize the storage to high-speed high capacity data.
The utility model is specifically described below.
As shown in figure 1, the design overall structure based on NAND FLASH storage chip array control units expansible FPGA
Figure, including host computer control module 1 and NAND FLASH storage chip array control units module 2.NAND FLASH storage chips battle array
Control signal, status signal between row controller module 2 and NAND FLASH storage chip arrays expand to 4, data
Line end mouthful is extended to 32, four NAND FLASH storage chip concurrent workings is realized, due to only having used a NAND
FLASH storage chip array control units, therefore be 1 in main frame and all control signals in controller part, data wire is extended to
32.The utility model, using the CYCLONE V in FPGA as key control unit, is to utilize Verilog HDL language designs
Out.Wherein core NAND FLASH storage chip array control units module 2 is by a Logic control module 21, two
Individual data buffer zone 22 (A and B), register group 23 and standard SRAM interface module 24 are constituted.Logic control module 21 is
The key of NAND FLASH storage chip array control units module 2, it will be specifically described with state transition diagram below,
Two data buffer sizes are all the I/O ports of 8K byte and 32, and number can be effectively improved using dual-cache mechanism
According to transmission rate.Implement step：After main frame sends page program command, NAND FLASH storage chip array control unit moulds
The lowest order reset of address register is represented that main frame is programmed operation to data buffer zone A by block 2, once the number of 8K bytes
After writing, i.e. data buffer zone A is fully written, and NAND FLASH storage chip array control units module 2 is changed at once
By the lowest order set of address register, at this moment main frame is just operated to data buffer zone B.So NAND FLASH are stored
Chip is programmed operation with regard to usage data buffer area A；When data buffer zone B is fully written and NAND FLASH storage chips
Complete after page programming operation, by the conversion again of data buffer zone, host service function, NAND are given again by data buffer zone A
FLASH storage chip usage data buffer area B, so realize ping-pong operation repeatedly, be especially suitable for data pipeline processing and
The seamless buffering of data is realized, is conducive to improving the access rate of data.Register group 23 includes configuration register, Status register
Device, command register and address register.Configuration register is used for setting the configuration of NAND FLASH storage chips to include sequential
The size of parameter, data bit width and page, status register is used for detecting the states of NAND FLASH storage chips, read operation it
R/B# signals are detected after preceding or programming operation, command register is used for sending the operation life of NNAD FLASH storage chips
Order, address register is used for sending address signal to NAND FLASH storage chips.
The utility model application process is briefly described as follows.
Fig. 2 is the major state transfer figure of NAND FLASH storage chip array control unit systems, mainly by six state groups
Into being idle condition 31 respectively, programming state 32, reads ID states 32 and reset state 36 at read states 33, erase status 34.Tool
Body flow：System complete reset state 36 after, major state will into idle condition 31 wait enable signal arrival so as to
Into next state.After enable signal is received, specifically transfer is determined by the value (cmd_code) of command code to state
's.If command code cmd_code=A1, then state transition to programming state 32 and the corresponding sub- state of execution, in the shape
State sends complement mark done signals to major state after completing, at this moment major state can enter idle condition 31 and wait next
The individual arrival for enabling signal.If command code cmd_code=A2, A3, A4 or A5, flow and command code cmd_code=A1
Perform similar.
Fig. 3 is the page programming state transfer figure of NAND FLASH storage chip controllers.Idiographic flow：Between 40 expression states
Redirect, 41 represent switching programming buffering areas, for doing the caching of data, 42 represent main frames send 8K bytes of page of data to
Data buffer zone, 43 represent that send order 80H represents to start on page programming operation, figure to NAND FLASH storage chip controllers
44 be due to that the least unit of NAND FLASH storage chips read-write is page, as long as so the address of three bytes represents needs
The block address and page address of programming；NAND FLASH storage chips controller needs the data in data buffer zone to write afterwards
In the register of NAND FLASH storage chips.45 expression NAND FLASH storage chip controllers send command word 10H, 46 tables
Show after execution of step 45, NAND FLASH storage chips will automated programming, 47 expression status signal R/B# will enter low electricity
Put down and R/B# signals are always maintained at low level in this process.48 represent after the completion of programming operation, status signal R/B#
Into high level.49 represent to detect whether operation successfully completes by the value of status register.
Fig. 4 is the reading page status transfer figure of NAND FLASH storage chip controllers.Idiographic flow：
51 expression NAND FLASH storage chips controllers enter to study in a page process, 52 represent main frames send command word OOH to
NAND FLASH storage chip controllers start to read page operations, and 53 expression main frames are sent to NAND FLASH storage chip controllers
The address of three bytes, 54 represent that main frame sends command word 30H, subsequent NAND to NAND FLASH storage chips controller
FLASH storage chips controller carries out inter-process, and is changed into low level into step 55, i.e. status signal R/B#, herein
During NAND FLASH storage chips controllers page of data is loaded into data buffering from NAND FLASH storage chips
Qu Li, once status signal R/B# is changed into after high level i.e. step 56, show controller by whole page data all read into
In data buffer zone, 57 represent that the data that caching is gone in area can be taken away by main frame, and 58 represent to wait all data to be read by main frame
It is complete, redirecting between 59 expression states.
Fig. 5 is the block erase status transfer figure of NAND FLASH storage chip controllers.Core is stored for NAND FLASH
For piece, block erasing operation must be carried out before write-in data.Idiographic flow：First, 61 NAND FLASH storage cores are represented
Piece controller receives the command word 60H of main frame transmission, and expression starts to carry out block erasing operation to NAND FLASH storage chips.
62 expression main frames send the address of three bytes to determine specific block to be erased, and step 63 is performed afterwards, NAND is represented
Command word DOH is sent inside FLASH storage chip controllers, i.e., real erasing operation starts, and subsequently enters step 64, state
Signal R/B# is changed into low level, shows that block erasing operation is in progress, and 65 expression status signal R/B# are changed into high level, explanation
Erasing operation is completed, redirecting between 66 expression states.
Fig. 6 is the reading ID state transition diagrams of NAND FLASH storage chip controllers.Idiographic flow：71 represent main frames to
NAND FLASH storage chips controller sends command word 90H, that is, proceeds by reading ID operations, and 72 represent main frame to NAND
FLASH storage chips controller writes ID to be read address, then performs step 73, represents that the data for reading 4 bytes are
For the identification information of NAND FLASH storage chips, redirecting between 74 expression states.
Fig. 7 is the reset state transfer figure of NAND FLASH storage chip controllers.Idiographic flow：81 represent to work as NAND
FLASH storage chip controllers, which are received, will proceed by reset operation, subsequent NAND after the command word FOH of main frame transmission
Command word FFH is sent inside FLASH storage chip controllers and gives NAND FLASH storage chips, 82 represent in execution of step 81
Afterwards, status signal R/B# enters low level, shows that resetting operation is carried out, and 83 represent to wait until that status signal R/B# is changed into high electricity
After flat, illustrate that operation is completed.
Claims (7)
1. a kind of NAND FLASH storage chip array control unit expansible based on FPGA, it is characterised in that：Described is whole
System is made up of host computer control module and NAND FLASH storage chip controller modules, and parallel control multi-disc NAND FLASH are deposited
Chip is stored up, the NAND FLASH storage chips array control unit includes Logic control module, two data buffer zone moulds
Block, register group and interface module；The NAND FLASH storage chips controller module be used for connect host module and
NAND FLASH storage chips；During the operation that the Logic control module is used to produce and NAND FLASH storage chips match
Sequence；Described two data buffer zone modules are used for the caching of data and realize ping-pong operation；The register group is used to deposit
Order, state, address and configuration parameter are set in NAND FLASH storage chips；The host computer control module includes being used to produce
Access NAND FLASH storage chips order and data to controller, connect the status signal sum fed back by controller it is believed that
Breath；The interface module is used for the soap-free emulsion polymeization interface for being mapped as a similar SRAM.
2. a kind of NAND FLASH storage chip array control unit expansible based on FPGA according to claim 1, its
It is characterised by：The host computer control module be used to producing the order for accessing NAND FLASH and data to controller and receive by
The status signal and data message of controller feedback.
3. a kind of NAND FLASH storage chip array control unit expansible based on FPGA according to claim 1, its
It is characterised by：The NAND FLASH storage chips controller module is used to connect host module and NAND FLASH storage cores
Piece, the order of Receiving Host transmission and data and concurrently manipulation multi-disc NAND FLASH storage chips, while feedback states
Signal is to main frame.
4. a kind of NAND FLASH storage chip array control unit expansible based on FPGA according to claim 1, its
It is characterised by：The Logic control module is used for the time sequential routine produced and NAND FLASH storage chips match, including reads
Write, wipe, reading ID and reset the sequential of operation.
5. a kind of NAND FLASH storage chip array control unit expansible based on FPGA according to claim 1, its
It is characterised by：Described two data buffer zone modules are used for the caching of data and realize ping-pong operation.
6. a kind of NAND FLASH storage chip array control unit expansible based on FPGA according to claim 1, its
It is characterised by：The register group sets order, state, address and configuration ginseng for depositing the interior of NAND FLASH storage chips
Number.
7. a kind of NAND FLASH storage chip array control unit expansible based on FPGA according to claim 1, its
It is characterised by：The interface module is used for the soap-free emulsion polymeization interface for being mapped as a similar SRAM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720235609.6U CN206557758U (en) | 2017-03-06 | 2017-03-06 | A kind of NAND FLASH storage chip array control unit expansible based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720235609.6U CN206557758U (en) | 2017-03-06 | 2017-03-06 | A kind of NAND FLASH storage chip array control unit expansible based on FPGA |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206557758U true CN206557758U (en) | 2017-10-13 |
Family
ID=60362895
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720235609.6U Expired - Fee Related CN206557758U (en) | 2017-03-06 | 2017-03-06 | A kind of NAND FLASH storage chip array control unit expansible based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206557758U (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108008919A (en) * | 2017-12-22 | 2018-05-08 | 中国电子科技集团公司第五十四研究所 | A kind of high-speed data handles SSD |
| CN109086229A (en) * | 2018-07-17 | 2018-12-25 | 京信通信系统（中国）有限公司 | device access method, device, controller and storage medium |
| CN109635401A (en) * | 2018-12-04 | 2019-04-16 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of dynamic and configurable storage control design method |
| CN109741385A (en) * | 2018-12-24 | 2019-05-10 | 浙江大华技术股份有限公司 | A kind of image processing system, method, apparatus, electronic equipment and storage medium |
| CN109783411A (en) * | 2018-12-20 | 2019-05-21 | 成都旋极历通信息技术有限公司 | A kind of FLASH antenna array control method and controller based on FPGA |
| CN110134337A (en) * | 2019-05-17 | 2019-08-16 | 苏州大学 | Based on Open-Channel SSD structure exact sequence write method |
| CN111931442A (en) * | 2020-09-24 | 2020-11-13 | 广东高云半导体科技股份有限公司 | FPGA embedded FLASH controller and electronic device |
-
2017
- 2017-03-06 CN CN201720235609.6U patent/CN206557758U/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108008919A (en) * | 2017-12-22 | 2018-05-08 | 中国电子科技集团公司第五十四研究所 | A kind of high-speed data handles SSD |
| CN109086229A (en) * | 2018-07-17 | 2018-12-25 | 京信通信系统（中国）有限公司 | device access method, device, controller and storage medium |
| CN109635401A (en) * | 2018-12-04 | 2019-04-16 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of dynamic and configurable storage control design method |
| CN109783411A (en) * | 2018-12-20 | 2019-05-21 | 成都旋极历通信息技术有限公司 | A kind of FLASH antenna array control method and controller based on FPGA |
| CN109783411B (en) * | 2018-12-20 | 2022-05-17 | 成都旋极历通信息技术有限公司 | FLASH array control method based on FPGA and controller |
| CN109741385A (en) * | 2018-12-24 | 2019-05-10 | 浙江大华技术股份有限公司 | A kind of image processing system, method, apparatus, electronic equipment and storage medium |
| CN110134337A (en) * | 2019-05-17 | 2019-08-16 | 苏州大学 | Based on Open-Channel SSD structure exact sequence write method |
| CN111931442A (en) * | 2020-09-24 | 2020-11-13 | 广东高云半导体科技股份有限公司 | FPGA embedded FLASH controller and electronic device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN206557758U (en) | A kind of NAND FLASH storage chip array control unit expansible based on FPGA | |
| CN206557767U (en) | A kind of caching system based on ping-pong operation structure control data buffer storage | |
| CN101498994B (en) | Solid state disk controller | |
| TWI543185B (en) | Memory with output control and system thereof | |
| TWI424435B (en) | Method for giving program commands to flash memory chips, and controller and storage system using the same | |
| CN102165532B (en) | Solid state storage device controller with parallel operation mode | |
| CN101740102B (en) | Multi-channel flash memory chip array structure and write-in and read-out methods thereof | |
| CN104599698A (en) | Multiple independent serial link memory | |
| CN110096469A (en) | Multiple independent serial link memories | |
| CN105138470A (en) | Multi-channel nand flash controller | |
| CN107391392A (en) | A kind of garbage reclamation optimization method based on flash memory device Concurrent Feature | |
| CN104238957B (en) | SPI controller, SPI flash memory and its access method and access control method | |
| WO2010000101A1 (en) | Device and method for extending memory space of embedded system | |
| TWI470437B (en) | Apparatus and method for capturing serial input data | |
| CN106802870A (en) | A kind of efficient embedded system chip Nor Flash controllers and control method | |
| CN101515221A (en) | Method, device and system for reading data | |
| CN207008602U (en) | A kind of storage array control device based on Nand Flash memorizer multichannel | |
| CN111240598B (en) | Large-capacity rapid NandFlash storage implementation method based on software and hardware combination mode | |
| CN206331414U (en) | A kind of solid state hard disc | |
| CN105677576B (en) | A kind of Bank controllers read-write control device and method towards phase transition storage | |
| CN104331145A (en) | Realization method for reducing DDR3 memory write operation power consumption | |
| CN104461967B (en) | It is a kind of to support synchronous and asynchronous transfer mode parallel data grabbing card | |
| CN201218944Y (en) | Structure for implementing flash memory controller caching by double-port RAM | |
| CN1375873A (en) | High speed and high-capacity flash solid memory structure and manufacture process | |
| CN113220616B (en) | FPGA-based interface conversion system and method from SDRAM to MRAM |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20171013 Termination date: 20200306 |