CN108008919A - A kind of high-speed data handles SSD - Google Patents
A kind of high-speed data handles SSD Download PDFInfo
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- CN108008919A CN108008919A CN201711407780.1A CN201711407780A CN108008919A CN 108008919 A CN108008919 A CN 108008919A CN 201711407780 A CN201711407780 A CN 201711407780A CN 108008919 A CN108008919 A CN 108008919A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0688—Non-volatile semiconductor memory arrays
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- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Read Only Memory (AREA)
Abstract
The invention discloses a kind of high-speed data to handle SSD, belongs to SSD technology field.It includes SSD controller and multiple flash chips, wherein, the ratio between the programming time of each flash chip and load time are N, multiple flash chips are organized into M N array form, and SSD controller is connected with a data bus, a controlling bus and a silver with every row flash chip and selects bus respectively.The SSD has the advantages that storage speed is fast, suitable for requiring storage speed high equipment.
Description
Technical field
The present invention relates to SSD technology field, particularly relates to a kind of high-speed data processing SSD.
Background technology
With the arrival in big data epoch, the SSD based on NAND flash（Solid State Disk, solid state hard disc）
Through being used widely in large-scale data center.NAND flash have non-volatile, high reliability, small, light-weight, high
The features such as performance and small power consumption, therefore be widely used in various SSD storage devices.
Monolithic NAND flash are programmed（NAND flash carry out the operation of data storage, referred to as program）Operation can be divided into three
A step：1) loading operation, mainly completes the loading work of program command, address and data；2) automated programming operate, i.e., by
Flash, which is automatically performed, to be loaded onto the data of page data register and is written to the programming operation of internal storage unit；3) detection behaviour
Make, it is necessary to which whether the data for detecting write-in program correctly, if incorrect, it is necessary to reprogram after automated programming；If
Correctly, operation below could be continued.
Any one step of flash all has " Busy " state, in this case, can not carry out other behaviour again to flash
Make.When flash carries out data storage, be in units of page, loaded page of data to after caching of page register, it is necessary into
Enter " Busy " phase of page automated programming, data can not be loaded to piece flash again in this period；And the time of page automated programming
The data load time generally is several times as much as, causes flash to continue storage speed not high, is filled with the time of a piece of flash relatively
It is long.
At present, the capacity of monolithic NAND flash is up to 8G or 16G at present, far can not meet great Rong in storage system
The demand of amount.The technology generally used in solid-state disk product in the industry now is to integrate polylith flash chip, and expansion is deposited
Store up capacity.But during for mass data storage, the storage characteristics of flash chip itself cause data be press piece when storing into
Row storage, therefore, this flash chip storage mode can not meet the needs of high speed.
The content of the invention
In view of this, the present invention proposes a kind of high-speed data processing SSD, it has the advantages that storage speed is fast.
Based on above-mentioned purpose, technical solution provided by the invention is：
A kind of high-speed data handles SSD, including SSD controller and multiple flash chips, the programming time of each flash chip
Be N with the ratio between load time, the multiple flash chip is organized into M N array form, the SSD controller respectively with battle array
Often row flash chip in row is connected with a data bus, a controlling bus and a silver and selects bus.
Optionally, the SSD controller includes programmable digital circuit, the SSD controller by plug-in according to
Following steps store data：
（1）Data to be stored is divided into data cell by the page size according to flash chip, and each data cell corresponds to one
One page unit of flash chip；
（2）All data cells are divided into m groups, in addition to data cell number≤N of last group, remaining every group data cell
Number is N number of；Correspondingly, the address composition m row N column address matrixes of m × N number of flash chip are chosen from flash arrays,
Wherein, during the flash chip corresponding to address do not gone together also is located at not going together in flash arrays, the address institute of same row
Corresponding flash chip also is located in same row in flash arrays；
（3）According to the address of flash chip, corresponding flash chip is selected by chip selection signal, each data cell is distinguished
It is stored in different flash chips；During storage, the flash chip in address matrix corresponding to the address of same row is synchronously
Data storage is carried out, data storage is carried out by chip selection signal successively with the flash chip corresponding to the address of a line, and currently
After one flash chip completes loading operation, chip selection signal is immediately switched to next flash chip.
Optionally, the step（3）After further include following steps：
（4）Whether detection data cell stores success, for not storing successful data cell, new by address distribution
Flash chip is stored again, while marks the flash chip address for the data storage unit that fails, storage next time number
According to when skip the address, and the address that a new flash chip is chosen from flash arrays in not the going together of same row is replaced
The address.
Optionally, the step（1）Following steps are further included before：
（0）Check the size of data to be stored, if size of data is less than N number of page of memory length, all data are stored in one
In a flash chip.
Optionally, the SSD controller includes following circuit unit：
Cutting unit, for page size of the data to be stored according to flash chip to be divided into data cell, each data cell
Corresponding to a page unit of a flash chip；
Control unit, for choosing corresponding chip address from flash arrays successively by chip selection signal, and by each number
A different flash chip is sent to according to unit；The chip address forms the address matrix of m rows N row, wherein, it is different
During flash chip corresponding to capable address also is located at not going together in flash arrays, corresponding to the address of same row
Flash chip also is located in same row in flash arrays；During storage, in address matrix corresponding to the address of same row
Flash chip synchronously carries out data storage, is carried out successively by chip selection signal with the flash chip corresponding to the address of a line
Data store, and after previous flash chip completes loading operation, chip selection signal is immediately switched to next flash chip；
Storage unit, for carrying out data storage to flash chip；
Inspection unit, for checking whether data successfully store, and the data cell to storing not successfully is stored again；
Indexing unit, for marking failure flash chip.
From narration above as can be seen that the beneficial effect of technical solution of the present invention is：
1st, flash chip is organized into array format by the present invention, and often row flash chip is individually equipped with a data bus, one
Bar controlling bus and a silver select bus, it is possible to achieve are stored while flash chip of not going together, compared in the prior art
It is a kind of leap from serial structure to parallel organization that all flash chips, which are shared for one group of bus, and storage speed carries significantly
It is high.
2nd, storage organization of the invention includes multiple row flash chip, and when storage can be selected not successively by chip selection signal
The flash chip of same column, and the loading of next column chip can be immediately begun to after previous column flash chip is completed and loaded, this
Sample, each flash chip use a kind of efficient pipelining, are only existed between adjacent flash assembly lines by loading
The time difference caused by process, the utilization rate of data/address bus greatly improve；This mode is changed before must completing in the prior art
The mode of next storage could be once carried out after the overall process of " loading-programming-inspection ", effectively reduces storage time, pole
The earth improves storage speed.
In short, the SSD controller in the present invention can be divided the address of flash chip in flash arrays by matrix-style
For row address and column address, when carrying out data storage, SSD controller provides same piece choosing to the m pieces chip of same column address
With different pieces of information line to load different data, so as to fulfill the parallel memorizing of m row data；To the N piece chips of identical row address
Different piece choosings and identical data line are provided, data are loaded with different time timesharing so as to fulfill the N roads flash to same a line.
It is so designed that, multi-disc flash chip will realize temporal pile line operation and parallel work-flow spatially, fill
Divide the automated programming time that make use of flash chip, realize the multiplexing of data/address bus, when shortening the equivalent operation of flash arrays
Between, the time that single flash takes bus is reduced to greatest extent so that the storage speed of overall flash arrays gets a promotion,
So as to shorten the total storage time of data flow, SSD storage efficiencies are improved.
Brief description of the drawings
In order to clearly describe this patent, one or more attached drawing is provided below, these attached drawings are intended to this patent
Background technology, technical principle and/or some specific embodiments make aid illustration.It should be noted that these attached drawings can
It can not also provide some to provide and have been described and belong to known in those of ordinary skill in the art often at this patent word segment
The detail of knowledge；Also, because those of ordinary skill in the art can combine the published word content of this patent completely
And/or accompanying drawing content, more attached drawings, therefore these attached drawings below are designed in the case where not paying any creative work
Can cover can not also cover all technical solutions that this patent word segment is described.In addition, these attached drawings is specific interior
Containing needs the word content with reference to this patent to be determined, when word content and some obvious knot in these attached drawings of this patent
, it is necessary to which to carry out comprehensive descision be this on earth with reference to the narration of the common knowledge and this patent other parts of this area when structure is not consistent
There are exist to draw mistake in clerical mistake, or attached drawing for the word segment of patent.Especially, the following drawings is the figure of exemplary in nature
Piece, it is not intended that imply the protection domain of this patent, those of ordinary skill in the art are by reference to the text disclosed in this patent
Word content and/or accompanying drawing content, can design more attached drawings, these are new in the case where not paying any creative work
Technical solution representated by attached drawing is still within the protection domain of this patent.
Fig. 1 is a kind of structure diagram of high speed data processing of embodiment of the present invention SSD；
Fig. 2 is the principle schematic that data are stored in a line flash chip in Fig. 1；
Fig. 3 is the flow chart that data store in the embodiment of the present invention.
Embodiment
For the ease of understanding of the those skilled in the art to the art of this patent scheme, meanwhile, in order to make the technology of this patent
Purpose, technical solution and beneficial effect are clearer, and the protection domain of claims is fully supported, below with tool
The form of body case makes the technical solution of this patent further, more detailed description.
As shown in Figure 1, a kind of high-speed data processing SSD, including SSD controller and multiple flash chips, each flash
The ratio between the programming time of chip and load time are N, and the multiple flash chip is organized into M N array form, the SSD
Controller is connected with a data bus, a controlling bus and a silver with every row flash chip and selects bus respectively.
As shown in figure 3, above-mentioned SSD controller can store data as follows by built-in firmware program：
Step 1, check the size of data to be stored, if size of data is less than N number of page of memory length, all data are stored in
In one flash chip（I.e. conventional SSD storage modes）, storage terminates, and otherwise performs following step；
Step 2, data to be stored is divided into data cell by the page size according to flash chip；
Step 3, all data cells are divided into m groups, in addition to data cell number≤N of last group, remaining every group data
Unit number is N number of, and m × N number of flash chip is chosen from flash arrays, and m row N row squares are formed with their address
Battle array, and each data cell is respectively stored in a different flash chip according to address；
Step 4, stored, the flash chip in address matrix corresponding to same column address synchronously carries out data storage, together
Flash chip corresponding to a line address carries out data storage successively by chip selection signal, and when previous flash chip is completed to add
After load, chip selection signal is immediately switched to next flash chip（Principle is as shown in Figure 2）；
Step 5, whether detection data cell stores success；
Step 6, for not storing successful data cell, distribute new flash chip and stored again, while mark fails
The address of the flash chip of success data storage unit, whens storage data next time, skip the flash chip, and from flash arrays
The middle another flash chip for choosing same row replaces the chip（That is, failure flash chip is not selected when forming address matrix
Address, and select the address of other flash chips of same row）.
In addition, SSD controller can also realize data storage procedure by way of circuit unit, i.e. can include such as
Lower circuit unit：
Judging unit, for checking the size of data to be stored, judges which kind of storage mode used；
Cutting unit, for data to be stored to be divided into data cell；
Control unit, for realizing the control to storing process by chip selection signal, in storage, chip selection signal is successively from flash
Corresponding chip address is chosen in array, these addresses are the address matrix for forming this storage；
Storage unit, for carrying out data storage to flash chip；
Inspection unit, for checking whether data successfully store, and the data cell to storing not successfully is stored again；
Indexing unit, for marking failure flash chip.
Foregoing circuit unit can be designed by hardware description language and realized.
Specifically, in the above-described embodiments, the SSD controller data flow to be stored to this first judges,
Judge whether this data flow to be stored can be stored according to SSD storage methods provided by the invention.
Secondly, be able to will be deposited substantially according to composition flash chip according to the data flow that storage method of the present invention is stored
Storage unit capacity is cut into m × N number of data element of equal size, is respectively intended to deposit m × N number of different flash chips；If number
It is less than the memory space performed shared by a single channel N level production lines operation storage data according to the storage space volume needed for stream
Capacity, then it is non-divided directly to store, avoid data storage excessively scattered.
Then, in SSD controller flash chip all inside the SSD, m × N number of is chosen with sufficient storage capacity
Flash chip, forms flash arrays, and distributes row address and column address for each data element, is allowed to and will be stored in flash
Chip array specific location corresponds to.
Then controller performs loading to the flash chip of first row in flash arrays and operates, completion program command,
After the loading work of location and data, row flash pieces will carry the data inside corresponding registers automatically into programming phases
Enter into flash storage units；Then, according to pipeline processes thought, completed waiting first row flash chip programming operation
While, controller to secondary series flash perform loading operation, after the completion of secondary series flash will be automatically into programming phases；Together
Should secondary series flash loading operation after the completion of, controller to the 3rd row directly perform loading operate.
And so on to the last one row flash complete loading operation after, controller detection first row flash programming operations
Whether terminate, further whether the data message of detection programming operation loading is correct effectively if terminating, if correct effective
Data, controller starts to detect whether secondary series flash programming operations terminate, on the contrary then record the flash chip storage unit
Address, start detect secondary series flash programming operations whether terminate, until whole flash arrays complete detection operation after, it is right
Successful data element is not stored re-executes programming operation；If first row flash programming operations do not terminate also, need to wait for programming
Detection after operation into lower next step operates.
After whole flash arrays complete detection operation, the storage of flash arrays is replaced to not storing successful data element
Location, re-executes programming operation, repeats aforesaid operations, until the storage of all data elements is completed, and invalid block is recorded in it is invalid
In block management table, storage misuse next time is prevented.So far this data storage is completed, and can start data storage next time.
As it can be seen that the present invention can make full use of flash chip using the storage method of pile line operation and parallel work-flow
" free time " time of automated programming, while multi-disc flash is stored together, is improved the utilization rate of SSD, is accelerated SSD's
Storage speed.
It is to be appreciated that to be intended merely to facilitate this area common for the above-mentioned narration for this patent embodiment
The exemplary description that technical staff understands this patent scheme and enumerates, does not imply that the protection domain of this patent is limited solely to
In this few example, those of ordinary skill in the art completely can on the premise of making and fully understanding to the art of this patent scheme,
In the form of not paying any creative work, by taking each example cited by this patent combination technique feature, replacing
Some technical characteristics, add more technical characteristics etc. mode, obtains more embodiments, all these specific implementations
Mode is within the covering scope of patent claims book, and therefore, these new embodiments also should be in this patent
Protection domain within.
In addition, for the purpose for simplifying narration, this patent may also not enumerate some ordinary specific embodiments, this
A little schemes are that those of ordinary skill in the art can expect naturally after it understanding of the art of this patent scheme, it is clear that this
A little schemes should also be included within the protection domain of this patent.
For the purpose for simplifying narration, above-mentioned each embodiment may only up to for the extent of disclosure of ins and outs
The degree that can voluntarily make a decision to those skilled in the art, i.e. there is no disclosed ins and outs for above-mentioned embodiment,
Those of ordinary skill in the art completely can be in the case where not paying any creative work, in filling for the art of this patent scheme
Divide under prompting, completed by means of the disclosed document of textbook, reference book, paper, patent, audio-visual product etc., alternatively, this
A little details are the contents that can voluntarily be maked decision according to actual conditions under being generally understood that of those of ordinary skill in the art.
As it can be seen that even if these underground ins and outs, the open adequacy of the art of this patent scheme will not be impacted.
In short, on the basis of explanation effect of the patent specification to claims protection domain is combined, it is any
Fall into the specific embodiment of patent claims book covering scope, within the protection domain of this patent..
Claims (5)
1. a kind of high-speed data handles SSD, including SSD controller and multiple flash chips, it is characterised in that each flash cores
The ratio between the programming time of piece and load time are N, and the multiple flash chip is organized into M N array form, the SSD controls
It is total that device processed is connected with a data bus, a controlling bus and silver choosing with the often row flash chip in array respectively
Line.
2. high-speed data according to claim 1 handles SSD, it is characterised in that the SSD controller includes programmable number
Word circuit, the SSD controller store data in accordance with the following steps by plug-in：
（1）Data to be stored is divided into data cell by the page size according to flash chip, and each data cell corresponds to one
One page unit of flash chip；
（2）All data cells are divided into m groups, in addition to data cell number≤N of last group, remaining every group data cell
Number is N number of；Correspondingly, the address composition m row N column address matrixes of m × N number of flash chip are chosen from flash arrays,
Wherein, during the flash chip corresponding to address do not gone together also is located at not going together in flash arrays, the address institute of same row
Corresponding flash chip also is located in same row in flash arrays；
（3）According to the address of flash chip, corresponding flash chip is selected by chip selection signal, each data cell is distinguished
It is stored in different flash chips；During storage, the flash chip in address matrix corresponding to the address of same row is synchronously
Data storage is carried out, data storage is carried out by chip selection signal successively with the flash chip corresponding to the address of a line, and currently
After one flash chip completes loading operation, chip selection signal is immediately switched to next flash chip.
3. high-speed data according to claim 2 handles SSD, it is characterised in that the step（3）After further include following step
Suddenly：
（4）Whether detection data cell stores success, for not storing successful data cell, new by address distribution
Flash chip is stored again, while marks the flash chip address for the data storage unit that fails, storage next time number
According to when skip the address, and the address that a new flash chip is chosen from flash arrays in not the going together of same row is replaced
The address.
4. high-speed data according to claim 2 handles SSD, it is characterised in that the step（1）Further include before as follows
Step：
（0）Check the size of data to be stored, if size of data is less than N number of page of memory length, all data are stored in one
In a flash chip.
5. high-speed data according to claim 1 handles SSD, it is characterised in that the SSD controller includes following circuit
Unit：
Cutting unit, for page size of the data to be stored according to flash chip to be divided into data cell, each data cell
Corresponding to a page unit of a flash chip；
Control unit, for choosing corresponding chip address from flash arrays successively by chip selection signal, and by each number
A different flash chip is sent to according to unit；The chip address forms the address matrix of m rows N row, wherein, it is different
During flash chip corresponding to capable address also is located at not going together in flash arrays, corresponding to the address of same row
Flash chip also is located in same row in flash arrays；During storage, in address matrix corresponding to the address of same row
Flash chip synchronously carries out data storage, is carried out successively by chip selection signal with the flash chip corresponding to the address of a line
Data store, and after previous flash chip completes loading operation, chip selection signal is immediately switched to next flash chip；
Storage unit, for carrying out data storage to flash chip；
Inspection unit, for checking whether data successfully store, and the data cell to storing not successfully is stored again；
Indexing unit, for marking failure flash chip.
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| CN201711407780.1A CN108008919A (en) | 2017-12-22 | 2017-12-22 | A kind of high-speed data handles SSD |
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| CN110083557A (en) * | 2019-05-05 | 2019-08-02 | 江苏沁恒股份有限公司 | The method and SOC system of high speed access FLASH |
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Application publication date: 20180508 |