CN113220616B - FPGA-based interface conversion system and method from SDRAM to MRAM - Google Patents

Abstract

The invention relates to an interface conversion system and method from SDRAM to MRAM based on FPGA, which adopts FPGA to complete data transmission and control of various sequential logic synchronization. The invention comprises an SDRAM command decoding module, an MRAM command module and an MRAM data reading and writing module; the SDRAM command decoding module realizes the functions of decoding control/address signals and controlling the working state of the MRAM, decodes various commands sent by the SDRAM controller into corresponding MRAM working states and transmits the MRAM working states to the MRAM command control module; the MRAM command module sends a command for controlling the MRAM according to the working state of the MRAM and transmits a read/write signal to the MRAM data read-write module; the MRAM data read-write module reads and writes data. The invention uses MRAM to replace SDRAM as main memory without changing the internal memory controller of the processor, and can be adapted to the current embedded system processor, finally realizing low power consumption data storage.

Description

FPGA-based interface conversion system and method from SDRAM to MRAM

Technical Field

The invention relates to an interface conversion system and method from SDRAM to MRAM based on FPGA, belonging to the technical field of magnetic memory application.

Background

As the feature size of the device is continuously reduced, when the device is scaled down to a deep submicron or even nanometer process size (e.g. 40 nm), the leakage current (or static power consumption) caused by Quantum Tunneling Effect (Quantum Tunneling Effect) becomes an important factor restricting the development of the conventional memory. The static power consumption caused by leakage current will account for more than 50% of the total power consumption of the chip. This part of the static power consumption not only results in low energy utilization but also brings about serious reliability problems. Thus, the development of conventional memory technologies has encountered serious bottlenecks and challenges.

In order to solve these problems to continue moore's law, new Nonvolatile (Nonvolatile) memories such as Phase Change Random Access Memory (PCRAM), resistive Random Access Memory (RRAM), and Spintronics (Spintronics) -based Magnetic Random Access Memory (MRAM) have been developed. Among them, the MRAM based on the spintronics has recently received much attention from the academic and industrial fields because of its excellent characteristics such as high speed, high density, low power consumption, unlimited number of read operations, and scalability.

Compared with the popular memory at present, the MRAM integrates the non-volatility of a FLASH memory (FLASH), the high speed and low power consumption of a Static Random Access Memory (SRAM), and the infinite write-in of a Dynamic Random Access Memory (DRAM), and has the characteristics of permanent memory, high density, high durability and the like. Much research is currently being devoted to the use of MRAM in computer memory systems, exploring its application area.

Magnetic Random Access Memory (MRAM) has attracted the attention of many researchers as a new type of non-volatile memory technology, and many researchers have proposed using MRAM as an on-chip cache instead of SRAM and as a main memory instead of DRAM. MRAM is also considered to be one of the most promising replacements for DRAM due to its same read and write characteristics as DRAM. Related researches for testing the performance, power consumption, feasibility and the like of MRAM instead of DRAM mainly based on simulation exist, but the practical aspect of MRAM has certain limitation. How to embed MRAM into the system as main memory is also a problem.

Disclosure of Invention

The invention solves the problems: the FPGA is used for realizing the conversion of the interface protocol from a Synchronous Dynamic Random Access Memory (SDRAM) to a Magnetic Random Access Memory (MRAM), a memory controller in a processor does not need to be changed, the MRAM can also be used for replacing the SDRAM as a main memory and can be adapted to the current embedded system processor, and finally, the data storage with ultra-low power consumption is realized. The specific implementation mode is to design an image acquisition system which takes MRAM as a main memory and is compatible with an SDRAM controller, so as to realize the image data storage with ultra-low power consumption.

The technical solution of the invention is as follows: an FPGA-based interface conversion system from SDRAM to MRAM, the system comprising: the device comprises an SDRAM controller, a control conversion module and a Magnetic Random Access Memory (MRAM); the control conversion module is realized by adopting an FPGA and comprises an SDRAM command decoding module, an MRAM control module and an MRAM data reading and writing module; the control conversion module realizes the function of converting the SDRAM control into the MRAM control;

the SDRAM controller sends out SDRAM command signals and address signals to the SDRAM command decoding module; meanwhile, after receiving a read-write request of the MRAM data read-write module, the SDRAM controller reads and writes data of the MRAM data read-write module;

the SDRAM command decoding module is used for decoding a command signal sent by the SDRAM controller into an MRAM working state and transmitting the MRAM working state to the MRAM control module; simultaneously, the address signal sent by the SDRAM controller is decoded to the MRAM control module; the commands corresponding to the MRAM working state comprise a waiting address, a read command, a write command, a burst interrupt and an NOP; according to the SDRAM and MRAM command mapping table, when the SDRAM command decoding module receives a Row Active command, the SDRAM command decoding module records the address of a logic storage array (L-Bank) and the address of a Row in the storage array and waits for the next read/write signal; when a read/write command is received, recording the column address, synthesizing a complete address signal, and correspondingly converting the working state of the MRAM into read/write;

the MRAM control module controls the MRAM according to the address signal and the working state transmitted by the SDRAM command decoding module; sending a corresponding MRAM control command and an address signal to the MRAM according to the working state of the corresponding MRAM; the MRAM control module may send a read or write signal to the MRAM data read/write module.

MRAM data read-write module: controlling data read-write of four groups of MRAM (each group comprises two MRAM, each group stores 16bit data, and the four groups of MRAM store 64bit data together); the SDRAM controller can read and write data to the MRAM data read-write module.

The invention adopts a conversion mechanism of an MRAM (magnetic random access memory) access protocol and a DDR (double data rate) access protocol, and deeply researches key problems in the MRAM access protocol, such as time sequence matching of the access protocol, access command conversion and the like; an MRAM array flow line read-write architecture is provided, and the adaptation of an MRAM access time sequence and a DDR access time sequence is completed; a mapping technology of the MRAM access command and the DDR access command is provided, and seamless conversion of the DDR command and the MRAM access command is achieved.

The SDRAM controller comprises an SDRAM initialization module, two FIFOs (W _ FIFO and R _ FIFO), namely a write cache, a read cache and an FIFO control module, a storage array (bank) switching module and an SDRAM read-write control module; the SDRAM initialization module realizes the initialization function of the SDRAM, and transmits an initialization completion signal (Init _ Done) to the SDRAM controller for subsequent operation after the SDRAM initialization is finished after being electrified; the SDRAM read-write control module realizes SDRAM burst read-write operation, respectively starts to send read/write commands to the SDRAM when receiving read/write requests from two FIFOs, and simultaneously realizes pre-charging and periodic refreshing operation to ensure the integrity and correctness of data stored in the SDRAM; the bank switching module sends a bank switching command to the SDRAM read-write control module to realize ping-pong read-write operation among 2 banks, so that input and output image data streams have no conflict; in addition, the SDRAM controller also has an FIFO control module for controlling a read/write cache module added between the SDRAM and the output of the camera and the input interface of the VGA to cache data, and completing asynchronous data cross-clock processing.

The SDRAM command decoding module is specifically realized as follows:

when a Row effective (Active) command sent by an SDRAM controller is received, simultaneously recording the address of a logic storage array (L-Bank), the Row address (Row) and the Column address (Column), and waiting for the next signal;

upon receiving a Read/Write (Read/Write) command, the column address is recorded and the complete address signal is synthesized: the logic memory array address + row address + column address correspondingly converts the working state of the MRAM into read/write;

MRAM does not need precharge, refresh operation, and when other commands are received, including initialization, refresh, precharge commands, no action is taken, and the state of MRAM is IDLE.

The MRAM control module is specifically implemented as follows:

sending a corresponding control command signal and an Address signal to each MRAM according to a working state, wherein the last two bits of the System _ Address signal are chip selection signals, performing Burst Read (Burst Read) operation, reading the System _ Address signal at the beginning, adding 1 to the System _ Address signal in each clock cycle, simultaneously sending a Read command to four groups of MRAMs every four clock cycles (40 ns), and sending the first 21 bits of the System _ Address signal to the four groups of MRAM Address signals; the method comprises the steps of recording a System _ Address signal when a Burst Write (Burst Write) operation starts, adding 1 to the System _ Address signal every clock cycle, sending a Write command to one group of MRAM determined by two bits after the System _ Address signal every other clock cycle (10 ns), wherein the Address signal sent to the group of MRAM is the first 21 bits of the System _ Address signal, and the other three groups of MRAM are in an idle state.

The MRAM data read-write module controls data read-write of four groups of MRAM according to a read-write command sent by an SDRAM controller, the read-write operation adopts an MRAM array flow read-write architecture, the adaptation of MRAM access time sequence and DDR access time sequence is completed, for burst read operation, four clock cycles of a first read command are sent, namely 40ns, data are taken out from which group of MRAM data bus determined by two bits after System _ Address and are put into a System data bus, and then data are taken out from the next group of MRAM data bus in sequence at intervals of 10ns, because the SDRAM working clock is 100MHZ, one clock cycle is 10ns, the time of two times of MRAM operation is 35ns, and the time of 40ns can ensure that the interval between two continuous operations of any group of MRAM is larger than the minimum delay; for burst write operation, each time a write command is sent to a certain group of MRAM, data in a system data bus is taken out and put into a data bus of the reorganized MRAM, and write operation is carried out.

The SDRAM and MRAM command mapping table is implemented as:

when a precharge and SDRAM refresh command is received, the working state of the corresponding MRAM is an IDLE state, and no operation is adopted; when a line effective instruction is received, a downlink address and a bank address are recorded, and a read/write command is waited; when a READ/WRITE command is received, recording a column address, synthesizing the column address with a bank address and a row address received in the previous clock cycle into a complete address signal, and correspondingly changing the working state of the MRAM into a READ/WRITE state, namely a READ/WRITE state; upon receipt of other commands, including initialization, refresh, and precharge commands, no action is taken and the state of the MRAM does not change.

The invention relates to an image acquisition system based on MRAM storage, which comprises an interface conversion system from SDRAM to MRAM based on FPGA and a camera; the control conversion module processes image data collected by the camera and transmits the image data to the SDRAM controller, and then the image data is stored in the MRAM through the control conversion module.

The invention is a realization method based on the interface conversion system, which is characterized by comprising the following steps:

(1) According to the signal command and the address signal sent by the SDRAM controller, the SDRAM command decoding module converts the command signal sent by the SDRAM controller into a corresponding MRAM working state, and when the SDRAM command decoding module receives an ACTIVE row (ACTIVE) command, the SDRAM command decoding module records an L-Bank address and a row address and waits for the next read/write signal; when a READ/WRITE (READ/WRITE) command is received, recording a column address, synthesizing a complete address signal, and correspondingly converting the working state of the MRAM into READ/WRITE;

(2) The MRAM control module controls the four groups of MRAM according to the address signal and the working state transmitted by the SDRAM command decoding module, namely, transmits a corresponding control command signal and an address signal; for burst read operation, when the working state is detected to be changed into read, a read command is simultaneously sent to four groups of MRAM every four clock cycles, and address signals of the four groups of MRAM are the first 21 bits of system address (sys _ addr) signals; for burst write operation, a write operation command is sent to one group of MRAM every other clock cycle, an address signal is sent to the group of MRAM at the same time, the other three groups are in an idle state, and when the address signal is analyzed, the specific operation group of MRAM is selected according to the last two bits of the address signal, so that the interval between two continuous operations of any group of MRAM is ensured to be four clock cycles which is larger than the minimum delay;

(3) For burst read operation, after a read command is sent from the beginning, data is taken out from four groups of MRAM buses every four clock cycles, and a group of data is put into a system data bus in turn in the following time, that is, a read command is sent to the MRAM at the moment of the arrival of the first clock rising edge, then four groups of data are respectively taken out and registered in a 64-bit register at the end of four clock cycles, the width of the four groups of data buses of the MRAM is 64 bits, and the method comprises the following steps: 16bit data in the first group of MRAM, 16bit data in the second group of MRAM, 16bit data in the third group of MRAM, and 16bit data in the fourth group of MRAM, which are 64bit data from low to high, then the first 16bit data in the register is put on the system output bus when the fifth clock cycle comes, the 31 st to the 16 th bit in the register is put on the system output bus when the sixth clock cycle comes, the 47 th to the 32 th bit is put on the system output bus when the seventh clock cycle comes, the 63 rd to the 48 th bit is put on the system output bus when the eighth clock cycle comes, the SDRAM controller adopts a burst read-write mode, the burst length is 256, that is, each time a read/write command is received, the MRAM is required to be read/written for 256 times, that is, each group of MRAM is required to be read/written for 64 times, and the operation is repeated for 64 times;

for burst write operation, at the same time of sending write command to a certain group of MRAM every time, taking out and placing the data in the system input data bus into the data bus of the group of MRAM, and making write operation, i.e. in the first clock cycle, sending write command to the first group of MRAM, placing the data in the system input bus onto the 15 th to 0 th bits of the register, in the second clock cycle, sending write command to the second group of MRAM, placing the data in the system input bus onto the 31 st to 16 th bits of the register, in the third clock cycle, sending write command to the third group of MRAM, placing the data in the system input bus onto the 47 th to 32 th bits of the register, in the fourth clock cycle, sending write command to the fourth group of MRAM, and placing the data in the system input bus onto the 63 rd to 48 th bits of the register.

Compared with the prior art, the invention has the advantages that:

(1) The invention is based on the access protocol time sequence matching of MRAM and SDRAM in read-write operation, and the control command conversion of SDRAM and MRAM; the method comprises the state of the data line DQ under the control of an MRAM chip selection signal, an output enable signal, a write enable signal and a read-write operation time sequence. The SDRAM is also analyzed to randomly perform data read-write operation of the designated address. The mapping table of the MRAM access command and the DDR access command is provided, and seamless conversion of the DDR command and the MRAM access command can be realized.

(2) The invention provides a storage particle array design; the bit width of the SDRAM memory of the FPGA core board is 16bits, and the bit width of the MRAM is 8bits, so that 2 MRAM chips are required to be used for substitution; the working clock frequency of SDRAM is 100MHz, and because of using the way of burst read-write, the read-write delay is 1 clock cycle, namely 10ns (except for the read-write delay of the first position), and the minimum corresponding time of MRAM read-write is 35ns, so the system design uses 4 groups of MRAM chips to carry out the way of flow type read-write to replace. The memory modules in the image acquisition system adopt 4 groups, and each group is provided with 2 MRAM chips to carry out pipelined reading and writing to replace the original SDRAM.

(3) The invention provides an MRAM array flow line read-write architecture, which is used for completing the adaptation of an MRAM access time sequence and a DDR access time sequence; for a burst read operation, a read command is sent from the beginning, then data is taken from the four sets of MRAM buses every 40ns, and one set of data is put into the system data bus in sequence at a later time. This operation was repeated 64 times. For burst write operation, while sending a write command to a certain group of MRAM, data in the system input data bus is taken out and put into the data bus of the group of MRAM, and write operation is performed.

Drawings

FIG. 1 is a diagram of a command mapping table for SDRAM and MRAM;

FIG. 2 is a schematic diagram of an implementation of an interface conversion system from SDRAM to MRAM according to the present invention, in which the SDRAM command decoding module, the MRAM control module, and the MRAM data reading/writing module are collectively referred to as a control conversion module;

FIG. 3 is a timing diagram of full-page burst mode read/write;

fig. 4 is an image acquisition system control design RTL diagram.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings and examples.

The invention uses FPGA to realize the conversion from DDR protocol (SDRAM read-write protocol) to MRAM read-write protocol, uses MRAM as the memory of embedded system and is compatible with SDRAM controller. One side of the interface is the timing constraints of the SDRAM and the other side is the timing constraints of the MRAM. Finally, a complete image acquisition system is completed.

First, the read/write timing, capacity, bit width, and address mapping of SDRAM and MRAM need to be considered. Three parameters are critical to the performance of the SDRAM: tRCD, CL and tRP. tRCD determines the interval between row addressing (active) to column addressing (read/write commands), CL determines the time it takes for column addressing to the data to be actually read, and tRP determines the speed of the different working row transitions in the same L-Bank. The write operation is independent of CL.

Reading and writing time sequence: although MRAM has similar read and write characteristics to SDRAM, the read and write speed of MRAM is still somewhat slower than SDRAM. In burst read/write mode, the SDRAM processes the first data with a delay tRP + tRCD + CL, while the SDRAM processes the other data with a delay of only CL (typically 10 ns). The read-write delay of the MRAM is 35ns;

bit width: the bit width of the MRAM is 8bits, and the bit width of the SDRAM is 16bits;

capacity: the capacity of MRAM is 2Mbits, the capacity of SDRAM is 16Mbits;

row and column addresses: the row address line of SDRAM is 13 bits, the column address line is 9 bits, L-Bank address 2 bits. The address line of an MRAM is 21 bits.

Referring to fig. 2, an interface conversion system from SDRAM to MRAM based on FPGA of the present invention includes: the device comprises an FPGA, an SDRAM controller, an SDRAM command decoding module, an MRAM control module, an MRAM data reading and writing module and a Magnetic Random Access Memory (MRAM). The command mapping table for SDRAM and MRAM is described with reference to FIG. 1.

In the image acquisition system, the FPGA is used for image processing, and the design of a control core is realized by using a Verilog HDL language. Through functional division, the design is divided into modules such as CMOS I2C initialization, data capture, image receiving analysis and decoding, SDRAM asynchronous image storage, control time sequence conversion, VGA drive and the like. Through an RTL (real time language) design diagram of the image acquisition system, referring to fig. 4, a system clock module provides clock frequencies required by other modules; the camera module realizes the control of the camera, and simultaneously splices the received image data and transmits the spliced image data to the SDRAM module; the SDRAM control module stores data from the camera and processes a data reading request from the VGA module; the control conversion module is the most important part and realizes the function of converting the SDRAM control into the MRAM control; the VGA display module realizes the display function of image data.

The invention relates to an interface conversion method from SDRAM to MRAM based on FPGA, comprising the following steps:

(1) According to the signal command and the address signal sent by the SDRAM controller, the SDRAM command decoding module converts the control signal of the SDRAM controller to the SDRAM into a corresponding MRAM working state, and if the module receives an ACTIVE row (ACTIVE) command, the module records an L-Bank address and a row address and waits for the next read/write signal; upon receiving a READ/WRITE (READ/WRITE) command, recording a Column address and synthesizing a complete address signal (sys _ addr [22 ] = { L-Bank, row [12 ] Column [ 0 ];

(2) The MRAM control module controls the four groups of MRAM according to the system address signal and the working state transmitted by the SDRAM command decoding module, namely, transmits corresponding control command signals and address signals. For a burst read operation, a read command is simultaneously sent to four groups of MRAMs every four clock cycles (40 ns) from when the operating state is detected to when the read operation is changed, and the address signal to the four groups of MRAMs is the first 21 bits of the sys _ addr signal (MRAM _ addr = sys _ addr [22 ]. For burst write operations, a write command is sent to one set of MRAMs every other clock cycle (10 ns), while an address signal is sent to this set of MRAMs, with the other three sets in an idle state. When the address signal is analyzed, which set of MRAM is specifically operated is selected according to the last two bits of the sys _ addr signal. This ensures that the interval between successive operations for any one set of MRAMs is 40ns, greater than the minimum delay.

(3) The MRAM data read/write module is used for controlling the data read/write of the four groups of MRAM.

For a burst read operation, such as the read timing diagram shown in fig. 3, a read command is sent from the beginning, then data is taken from the four sets of MRAM buses every 40ns, and one set of data is put into the data buses in sequence at a later time. That is, if the 0ns sends a read command to the MRAM, then four sets of data are respectively fetched in the 40ns and registered in one 64 th register, that is: mram _ dq [63 ] = { mram3_ data [15 [ 0 ]. This operation was repeated 64 times;

for burst write operation, referring to the write timing chart of fig. 3, data input into the data bus is taken out and put into the data bus of a certain group of MRAMs to perform write operation while sending a write command to the group of MRAMs each time. That is, a write command is transmitted to MRAM0 in the 0ns, data input to the bus is put on MRAM0_ data, a write command is transmitted to MRAM0 in the 10ns, data input to the system bus is put on MRAM1_ data, a write command is transmitted to MRAM0 in the 20ns, data input to the system bus is put on MRAM2_ data, a write command is transmitted to MRAM0 in the 30ns, and data input to the bus is put on MRAM3_ data.

Due to the non-destructive reading and data storage characteristics of MRAM, compared to the complicated pre-charging, periodic refreshing, and other control operations of SDRAM, the control using MRAM is simpler and lower power consumption. After a series of operations such as software simulation, hardware debugging and the like, the function of the low-power-consumption image acquisition system adopting MRAM as cache is successfully realized. Compared with the prior image acquisition system which takes SDRAM as cache, the method realizes that MRAM is adopted to replace DRAM as an embedded system main memory and is compatible with SDRAM controller.

The above examples are provided only for the purpose of describing the present invention, and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims. Various equivalent substitutions and modifications can be made without departing from the spirit and principles of the invention, and are intended to be within the scope of the invention.

Claims (5)

1. An interface conversion system from SDRAM to MRAM based on FPGA, characterized in that: the system comprises: the device comprises an SDRAM controller, a control conversion module and a Magnetic Random Access Memory (MRAM); the control conversion module is realized by adopting an FPGA and comprises an SDRAM command decoding module, an MRAM control module and an MRAM data reading and writing module; the control conversion module realizes the function of converting SDRAM control into MRAM control;

the SDRAM controller sends out SDRAM command signals and address signals to the SDRAM command decoding module; meanwhile, after receiving a read-write request of the MRAM data read-write module, the SDRAM controller reads and writes data to the MRAM data read-write module;

the SDRAM command decoding module is used for decoding a command signal sent by the SDRAM controller into an MRAM working state and transmitting the MRAM working state to the MRAM control module; simultaneously, the address signal sent by the SDRAM controller is decoded to the MRAM control module; the commands corresponding to the MRAM working state comprise a waiting address, a read command, a write command, a burst interrupt and an NOP; according to the SDRAM and MRAM command mapping table, when the SDRAM command decoding module receives a row effective command, the SDRAM command decoding module records a logic storage array address and a row address in a storage array and waits for a next read/write signal; when a read/write command is received, recording the column address, synthesizing a complete address signal, and correspondingly converting the working state of the MRAM into read/write;

the MRAM control module controls the MRAM according to the address signal and the working state transmitted by the SDRAM command decoding module; sending a corresponding MRAM control command and an address signal to the MRAM according to the working state of the corresponding MRAM; the MRAM control module can send a read or write signal to the MRAM data read/write module;

MRAM data read-write module: controlling the data reading and writing of the four groups of MRAM; the SDRAM controller reads and writes data of the MRAM data read-write module;

the SDRAM command decoding module is specifically realized as follows:

when a Row effective (Active) command sent by an SDRAM controller is received, simultaneously recording the address of a logic storage array (L-Bank), the Row address (Row) and the Column address (Column), and waiting for the next signal;

upon receiving a Read/Write (Read/Write) command, the column address is recorded and the complete address signal is synthesized: the logic memory array address + row address + column address correspondingly converts the working state of the MRAM into read/write;

MRAM does not need to precharge, refresh operation, when receiving other commands, including initialization, refresh, precharge commands, then do not take any action, MRAM state is IDLE, namely IDLE state;

the MRAM data read-write module controls data read-write of four groups of MRAM according to a read-write command sent by an SDRAM controller, the read-write operation adopts an MRAM array flow read-write architecture, the adaptation of an MRAM access time sequence and an SDRAM access time sequence is completed, for burst read operation, four clock cycles of a first read command are sent, namely 40ns, data are taken out from which group of MRAM data bus determined by two bits after System _ Address and are put into a System data bus, and then data are taken out from a next group of MRAM data bus in sequence at intervals of 10ns, because the SDRAM working clock is 100MHZ, one clock cycle is 10ns, the time of two times of MRAM operation is 35ns, and the time of 40ns can ensure that the interval between two continuous operations of any group of MRAM is larger than the minimum delay; for burst write operation, sending a write command to a certain group of MRAM every time, taking out data in a system data bus, putting the data into a data bus of the reorganized MRAM, and performing write operation;

the SDRAM and MRAM command mapping table is implemented as:

when a precharge and refresh SDRAM command is received, the working state of the corresponding MRAM is IDLE, namely an IDLE state, and no operation is taken; when a line effective instruction is received, a downlink address and a bank address are recorded, and a read/write command is waited; when a READ/WRITE command is received, recording a column address, synthesizing the column address with a bank address and a row address received in the previous clock cycle into a complete address signal, and correspondingly changing the working state of the MRAM into a READ/WRITE state, namely a READ/WRITE state; upon receipt of other commands, including initialization, refresh, and precharge commands, no action is taken and the state of the MRAM does not change.

2. The FPGA-based SDRAM to MRAM interface conversion system of claim 1, wherein: the SDRAM controller comprises an SDRAM initialization module, two FIFOs, a storage array bank switching module and an SDRAM read-write control module, wherein the two FIFOs are a write cache, a read cache and an FIFO control module; the SDRAM initialization module realizes the function of initializing the SDRAM, and transmits an initialization completion signal to the SDRAM controller for subsequent operation after the SDRAM initialization is completed after being powered on; the SDRAM read-write control module realizes SDRAM burst read-write operation, respectively starts to send read/write commands to the SDRAM when receiving read/write requests from two FIFOs, and simultaneously realizes pre-charging and periodic refreshing operation to ensure the integrity and correctness of data stored in the SDRAM; the storage array bank switching module sends a storage array bank switching command to the SDRAM read-write control module to realize ping-pong read-write operation among 2 storage array banks, so that input and output image data streams have no conflict.

3. The FPGA-based SDRAM to MRAM interface conversion system of claim 1, wherein: the MRAM control module is specifically implemented as follows:

transmitting a corresponding control command signal and an Address signal to each MRAM according to a working state, wherein the last two bits of the System _ Address signal are chip selection signals, performing Burst Read (Burst Read) operation, reading the System _ Address signal at the beginning, adding 1 to the System _ Address signal in each clock cycle, simultaneously transmitting a Read command to four groups of MRAMs every four clock cycles, and transmitting the first 21 bits of the System _ Address signal to the four groups of MRAM Address signals; the System _ Address signal is recorded when a Burst Write (Burst Write) operation starts, then 1 is added to the System _ Address signal every clock cycle, a Write command is sent to one group of MRAM determined by two bits after the System _ Address signal every other clock cycle, the Address signal sent to the group of MRAM is the first 21 bits of the System _ Address signal, and other three groups of MRAM are all in an idle state.

4. An image acquisition system based on MRAM storage, characterized by: the system comprises the interface conversion system from SDRAM to MRAM based on FPGA and the camera head of any one of claims 1-3; the control conversion module processes image data collected by the camera and transmits the image data to the SDRAM controller, and then the image data is stored in the MRAM through the control conversion module.

5. An implementation method for implementing the interface conversion system according to any one of claims 1 to 3, characterized by the following steps:

(1) According to the signal command and the address signal sent by the SDRAM controller, the SDRAM command decoding module converts the command signal sent by the SDRAM controller into a corresponding MRAM working state, and when the SDRAM command decoding module receives an ACTIVE row (ACTIVE) command, the SDRAM command decoding module records a logic storage array (L-Bank) address and a row address and waits for the next read/write signal; when a READ/WRITE (READ/WRITE) command is received, recording a column address, synthesizing a complete address signal, and correspondingly converting the working state of the MRAM into READ/WRITE;

(2) The MRAM control module controls the four groups of MRAM according to the address signal and the working state transmitted by the SDRAM command decoding module, namely, transmits corresponding control command signals and address signals; for burst read operation, when the detected working state is changed into read, a read command is simultaneously sent to four groups of MRAM at intervals of four clock cycles, and address signals of the four groups of MRAM are the first 21 bits of a system address (sys _ addr) signal; for burst write operation, a write operation command is sent to one group of MRAM every other clock cycle, an address signal is sent to the group of MRAM at the same time, the other three groups are in an idle state, and when the address signal is analyzed, the specific operation group of MRAM is selected according to the last two bits of the address signal, so that the interval between two continuous operations of any group of MRAM is ensured to be four clock cycles which is larger than the minimum delay;

(3) For burst read operation, a read command is sent from the beginning, then data is taken out from four groups of MRAM buses every four clock cycles, and a group of data is put into a system data bus in sequence in the following time, that is, a read command is sent to the MRAM at the moment when the first clock rising edge arrives, then four groups of data are respectively taken out and registered in a 64-bit register at the end of four clock cycles, the four groups of data buses of the MRAM have 64-bit width, and the method comprises the following steps: 16bit data in the first group of MRAM, 16bit data in the second group of MRAM, 16bit data in the third group of MRAM, and 16bit data in the fourth group of MRAM, which are 64bit data from low to high, then the first 16bit data in the register is put on the system output bus when the fifth clock cycle comes, the 31 st to the 16 th bit in the register is put on the system output bus when the sixth clock cycle comes, the 47 th to the 32 th bit is put on the system output bus when the seventh clock cycle comes, the 63 rd to the 48 th bit is put on the system output bus when the eighth clock cycle comes, the SDRAM controller adopts a burst read-write mode, the burst length is 256, that is, each time a read/write command is received, the MRAM is required to be read/written for 256 times, that is, each group of MRAM is required to be read/written for 64 times, and the operation is repeated for 64 times;

for burst write operation, at the same time of sending write command to a certain group of MRAM every time, taking out and placing the data in the system input data bus into the data bus of the group of MRAM, and making write operation, i.e. in the first clock cycle, sending write command to the first group of MRAM, placing the data in the system input bus onto the 15 th to 0 th bits of the register, in the second clock cycle, sending write command to the second group of MRAM, placing the data in the system input bus onto the 31 st to 16 th bits of the register, in the third clock cycle, sending write command to the third group of MRAM, placing the data in the system input bus onto the 47 th to 32 th bits of the register, in the fourth clock cycle, sending write command to the fourth group of MRAM, and placing the data in the system input bus onto the 63 rd to 48 th bits of the register.

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