WO2009115058A1

WO2009115058A1 - Mainboard for providing flash storage function and storage method thereof

Info

Publication number: WO2009115058A1
Application number: PCT/CN2009/070945
Authority: WO
Inventors: 林松
Original assignee: 深圳市朗科科技股份有限公司
Priority date: 2008-03-21
Filing date: 2009-03-23
Publication date: 2009-09-24
Also published as: HK1136368A1; CN101539785A; CN101539785B

Abstract

A mainboard for providing flash memory function and storing method thereof. The mainboard comprises an input/output module, and also comprises: a flash memory unit, which is integrated in the mainboard and used for storing data; a flash memory controller, which connects with the flash memory unit and can receive instructions from the input/output control module, and control the flash memory unit; a direct memory access controller, which connects with the flash memory controller, and cooperates with the flash memory controller to control the flash memory unit; a buffer, which connects with the direct memory access controller, and can communicates with the flash memory unit.

Description

Main board providing flash storage function and storage method thereof

[1] Technical field

[2] The present application relates to a computer structural component, and in particular to a computer motherboard.

[3] Background Art

[4] The current computer system data storage core is mainly a traditional hard disk. The traditional hard disk uses a disk as a storage medium to perform various operations on the disk through a magnetic head. The existing hard disk is bulky, and because it has mechanical parts such as a motor and a magnetic head therein, it is poor in shock resistance and easily damaged, resulting in loss of data; and still requires dedicated SCSI (Small Computer System Interface)

Small computer system interface), SATA (Serial Advanced Technology Attachment) or PATA (Parallel)

ATA, Parallel ATA) Hard disk interface connection works. Because traditional hard disk is used, a power cable and a data cable need to be connected to the motherboard. The motherboard is connected to the CPU module and memory through the memory control module and input/output control on the motherboard. The module performs communication control, so the connection is complicated and it is not convenient to disassemble.

Disk, SSD), which uses a flash memory instead of a magnet as a storage medium. The hard disk contains a storage controller, a storage medium, a cache, etc., but the interface and installation method are the same as those of a conventional hard disk. Still complicated, the connection is still inconvenient.

[6] Summary of the invention

[7] The technical problem to be solved by the present application is to provide a motherboard capable of providing a flash memory storage function.

[8] According to an embodiment of the present application, a motherboard that provides a flash memory function includes an input/output control module, and further includes:

[9] Flash memory unit, integrated on the motherboard for storing data;

[10] a flash controller, coupled to the flash memory unit, the flash controller capable of receiving an instruction from the input/output control module, and controlling the flash memory unit according to the received instruction;

[11] a direct memory access controller coupled to the flash controller, the direct memory access controller being capable of receiving an instruction from the input/output control module and cooperating with the flash controller according to the received instruction Controlling the flash storage unit;

[12] a cache, connected to the direct memory access controller, and implementing communication with the flash memory unit in accordance with control of the direct memory access controller and the flash controller.

[13] According to another embodiment of the present application, a motherboard that provides a flash memory function includes an input/output control module, and further includes:

[14] Flash memory unit communication interface, capable of connecting to a flash memory unit;

[15] a flash controller, communicatively coupled to the flash memory unit, the flash controller being capable of receiving an instruction from the input/output control module and controlling and communicating with the flash memory unit communication interface according to the received command a flash memory storage unit connected to the flash memory unit communication interface;

[16] a direct memory access controller coupled to the flash controller, the direct memory access controller being capable of receiving an instruction from the input/output control module and cooperating with the flash controller according to the received command The flash memory unit communication interface controls a flash memory unit connected to the flash memory unit communication interface;

[17] a cache, connected to the direct memory access controller, and configured to communicate with the flash memory unit through the flash memory unit communication interface according to the direct memory access controller and the control of the flash controller Communication between flash memory cells connected to the interface.

[18] The present application further provides a flash memory storage unit for use with the motherboard in another embodiment, wherein the flash memory storage unit includes a flash memory storage module and a communication interface, and the communication interface is coupled to the flash memory storage unit. Cooperate.

[19] The present application also provides a reading method for realizing data communication control based on an integrated flash memory unit, comprising the following steps:

[20] The direct memory access controller and the flash controller receive read control commands;

[21] The flash controller controls the flash storage unit to send data to the cache;

[22] The direct memory access controller controls the cache to send data to memory.

[23] The present application further provides a writing method for realizing data communication control based on an integrated flash memory unit, characterized in that it comprises the following steps:

[24] The memory access controller and flash controller receive write control commands;

[25] The direct memory access controller controls the data to be written from memory to the cache; [26] The flash controller allocates an address to the flash memory unit;

[27] The flash controller writes the data in the cache to the flash memory location.

[28] According to the motherboard provided with the flash memory function of the present application, the flash memory is used as a storage unit of the computer by using the flash memory as a storage medium, which has the advantages of fast read/write speed, good shock resistance and low power consumption. The flash memory is directly integrated into the main board, which simplifies the circuit and reduces the size and weight of the main board. Depending on the characteristics of the flash itself, this flash memory unit is faster than the hard disk, consumes less power and is more secure.

[29] BRIEF DESCRIPTION OF THE DRAWINGS

1 is a structural diagram of a main board providing a flash memory storage function according to a first embodiment of the present application;

2 is a schematic diagram of a working principle of a motherboard providing a flash memory storage function according to a first embodiment of the present application;

3 is a structural diagram of a main board providing a flash memory storage function according to a second embodiment of the present application;

4 is a schematic diagram of a working principle of a motherboard providing a flash memory storage function according to first and second embodiments of the present application;

FIG. 5 is a structural diagram of a main board providing a flash memory storage function according to a third embodiment of the present application; FIG.

6 is a schematic diagram of a working principle of a motherboard providing a flash memory storage function according to a third embodiment of the present application;

FIG. 7 is a structural diagram of a main board providing a flash memory storage function according to a fourth embodiment of the present application; FIG.

8 is a working principle diagram of a motherboard algorithm for providing a flash memory storage function according to third and fourth embodiments of the present application;

FIG. 9 is a schematic structural diagram of a flash memory storage unit according to a fifth embodiment of the present application; FIG.

FIG. 10 is a cascading block diagram of a flash memory chip in a flash memory storage unit according to a fifth embodiment of the present application; FIG.

[40] FIG. 11 is a flowchart of a reading method according to a sixth embodiment of the present application;

FIG. 12 is a flowchart of a reading method according to a seventh embodiment of the present application; FIG.

FIG. 13 is a flowchart of a writing method according to an eighth embodiment of the present application; FIG.

14 is a flow chart of a writing method according to a ninth embodiment of the present application.

[44] Specific implementation

[45] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the application and are not intended to limit the application.

As a first embodiment of the present application, FIG. 1 shows a main board providing a flash memory storage function, which is connected to the CPU module 6 and the memory 7. The main board includes a memory control module 12 and an input/output control module 1. Also includes:

[47] Flash memory unit 10, integrated on the motherboard for storing data;

[48] The flash controller 2 is connected to the flash memory unit 10, receives an instruction of the input/output control module, and controls the flash memory unit 10;

[49] Direct Memory Access Controller (DMA) 3, connected to the flash controller 2, receiving input/output control module 1 instructions, cooperative flash controller 2 controlling flash memory unit 10;

[50] Cache 5, connected to the direct memory access controller 3, to communicate with the flash storage unit 10.

[51] Among them, the input/output control module 1 on the main board communicates with the CPU module 6 through the memory control module 12 to realize control of the input/output bus.

[52] The CPU module 6 is generally composed of a logical operation unit, a control unit, and a storage unit. Included in the logic operation and control unit are registers for the temporary storage of data by the CPU module 6 during processing of the data. The CPU module 6 is generally implemented by mounting the CPU in a CPU socket provided on the main board. Alternatively, the CPU module 6 may also be a CPU integrated on the main board.

[53] The memory control module 12 is an important component of the main function of the motherboard chipset. The memory control module 12 is connected to the CPU module 6 and controls the memory 7. The AGP data (graphic acceleration interface data) is transmitted inside the north bridge circuit. The Northbridge chip of the integrated chipset also integrates the display core for the type and frequency of the CPU module 6, the front-side bus frequency of the system, the type and maximum capacity of the memory, the AGP slot, and the ECC error correction. Mainly responsible

Communication between CPU module 6 and memory; communication between CPU module 6 and peripherals; support for memory type and maximum capacity control.

[54] Flash controller 2, controls communication between flash memory unit 10 and input/output control module 1 and direct memory access controller 3.

[55] Direct Memory Access Controller 3 Controls the direct reading and writing of data between external devices and memory without the intervention of CPU module 6. In addition to the involvement of the CPU module 6 at the beginning and end of the data transfer, the CPU module 6 can handle other tasks during the data transfer. Thus, in most of the day, both the CPU module 6 and the input/output control module 1 operate in parallel. Therefore, the CPU resources are saved, and the efficiency of the entire computer system is greatly improved.

[56] Direct memory access controller 3 includes main memory address register, data quantity counter Direct Z memory logic for direct memory access, direct memory access request trigger, data buffer register, interrupt mechanism.

[57] The direct memory access controller 3 works in the following three ways: 1. Stop the CPU module 6 from accessing the memory 7: When the external device requests to transfer a batch of data, the direct memory access controller 3 sends a signal to the CPU module. 6. The direct memory access control device 3 starts the data transfer after obtaining the bus control. After a batch of data has been transferred, the direct memory access controller 3 notifies the CPU module 6 that the memory 7 can be used and the bus control is returned to the CPU module 6. 2. Cycle stealing: When the external device does not have a direct memory access request, the CPU module 6 accesses the memory as required by the program.

If the I/O device has a direct memory access request, the I/O device steals one or several cycles.

3. Direct memory access controller 3 and CPU module 6 alternate access: One CPU cycle can be divided into 2 cycles, one for direct memory access controller 3 access, and the other for CPU module 6 access. The application, establishment and return process of bus usage rights is not required.

[58] The flash memory unit 10 is integrated on the main board. Due to the improvement of the manufacturing process, the size of the flash memory chip has become smaller and smaller, and since the present embodiment eliminates the relevant functions of the hard disk interface and the hard disk interface on the main board, Integrating the flash chip on the motherboard provides plenty of room. The flash memory unit 10 may include a single chip flash chip or or include at least two flash chips that are cascaded with each other. At present, the capacity of a single-chip flash chip can reach 16GB, but it still cannot meet the requirements of computer storage. This requires cascading to expand the overall capacity of the flash storage unit. In Figure 10, a K9GCG08U1M flash chip is used as an example to illustrate a two-channel 8-chip flash chip cascading method, thus constructing a 64GB flash memory cell. The cascading manner of the flash chips in the flash memory unit includes the method shown in Fig. 10, but is not limited thereto. It can be cascaded with more flash chips, or even with four channels.

FIG. 2 is a schematic diagram showing the operation of a motherboard providing a flash memory storage function according to a first embodiment of the present application.

Referring to FIG. 2, the CPU module 6 performs a write operation to the flash memory unit 10, and the CPU module 6 sends a control command to the direct memory access controller 3 and the flash controller 2 through the memory control module 12 and the input/output control module 1. The control commands are transferred from the direct memory access controller 3 to the cache 5. After receiving the control command, the flash controller 2 determines whether a write operation can be performed on the flash memory unit 10, and allocates an address for the data to be written, and then transmits the data in the cache 5 to the flash memory unit 10; the CPU module 6 pairs the flash memory The memory unit 10 performs a read operation, and sends a read command to the direct memory access controller 3 and the flash controller 2, The memory controller 2 reads data from the flash memory unit 10 and transfers it to the cache 5. The data in the buffer 5 is sent to the CPU module 6 through the memory 7 under the control of the direct memory access controller.

[60] The first embodiment achieves an alternative to the existing hard disk interface and hard disk by the above manner. Alternatively, the flash controller, direct memory access controller, and cache can be integrated into one IC chip.

FIG. 3 illustrates a motherboard structure providing a flash memory storage function according to a second embodiment of the present application. In this embodiment, the flash memory control chip built in the input/output control module communicates with the flash memory storage unit on the main board to realize data writing, reading, erasing, and the like to the flash memory unit.

As shown in FIG. 3, according to the second embodiment, the flash controller 2, the direct memory access controller 3, and/or the cache 5 are built into the input/output control module 1. Also, a flash communication interface (not shown) is provided on the input/output control module 1. The input/output control module with the flash controller 2, the direct memory access controller 3, and the cache 5 enables control and communication of the flash memory unit 10 through the flash communication interface. The principles of specific control and communication are the same as those of the first embodiment and will not be repeated here. This design saves the number of chips that need to be placed on the motherboard and simplifies the wiring.

[63] According to the first and second embodiments of the present application, the motherboard with the flash memory unit directly integrates the flash memory unit on the motherboard by using the motherboard space, and directly connects to the flash controller for data transmission, eliminating the need for The communication interface between the flash memory unit and the flash controller simplifies the connection structure of the motherboard.

[64] In the foregoing first and second embodiments, as shown in FIG. 4, according to the characteristics of the flash memory storage unit itself, after the operating system is installed, an algorithm for controlling data read and write of the flash memory storage unit may be added in the operating system 8. For example, the mapping algorithm 81, the equalization algorithm 82, the ECC algorithm 83, and the like.

[65] Mapping algorithm 81, used to manage physical blocks in flash memory. For example, NAND

The memory cells contained in the flash memory operate in the basic unit of page and block, and there is no guarantee that each physical block can be used normally after leaving the factory. Therefore, you need to ensure that the data is stored in a physical block that is working properly. The mapping algorithm implements an effective mapping between the logical address of the logical block in the flash memory and the physical address of the physical block, ensuring that each logical block of the read and write data can correspond to a defect-free physical block to ensure data reliability and integrity.

[66] The equalization algorithm 82 is used to balance the read and write probabilities of logical addresses of logical blocks in the flash memory to improve the lifetime of the flash memory. [67] Error checking and error correction (Error cheching and

Correcting, ECC) Algorithm 83, used to detect and correct errors in the flash memory to store read data, control bit error ratio. On other flash controllers (like flash drives, MP3 controllers), ECC algorithms are implemented in firmware due to limited computing power. In this application, based on the powerful computing power of the computer CPU, the ECC algorithm can be included in the operating system, so that the algorithm can be upgraded by upgrading the operating system. As a result, the latest technology flash memory can be supported without changing the hardware structure of the motherboard.

FIG. 5 is a structural diagram of a motherboard with a flash memory function provided by a third embodiment of the present application.

The motherboard is connected to the CPU module 6 and the memory 7. The motherboard includes a memory control module 12 and an input/output control module 1, which also includes:

[69] The flash memory unit interface _{4 is} integrated on the motherboard and can be connected to a flash memory unit (not shown); [70] the flash controller 2 is connected to the flash memory unit interface 4, and receives the input/output control module 1 An instruction to control the flash memory unit through the flash memory unit interface 4;

[71] Direct memory access controller 3, connected to the flash controller 2 and receives the instruction of the input/output control module 1, and the flash memory controller 2 controls the flash memory unit through the flash memory unit interface 4;

[72] Cache 5, Connect the direct memory access controller 3, communicate with the flash memory unit via the flash memory unit interface 4.

[73] The input/output control module on the main board communicates with the CPU module 6 via the memory control module 12 to control the input/output bus. The CPU module 6 is generally implemented by mounting the CPU in a CPU socket provided on the main board. Alternatively, the CPU module 6 may also be a CPU integrated on the main board.

[74] The memory control module 12 is connected to the CPU module 6 and controls the memory 7. Memory control module 12 is mainly responsible

Communication between CPU module 6 and memory 7;

Communication between the CPU module and peripherals; support for the type of memory and maximum capacity control.

[75] The flash controller 2 controls the communication between the flash memory unit and the input/output control module 1 and the direct memory access controller 3 via the flash memory unit interface 4.

[76] The flash memory cell interface 4 includes a data bus 41 and a control bus 42: The data bus 41 can be 8-bit, 16-bit, 32-bit or 64-bit, etc., can support 8/16-bit flash memory cells, and can realize single channel, Dual or even four channels; control bus 42 may include RE#, WE#, ALE, CLE, WP#, RB, and several CE# Signals, etc.

[77] Direct Memory Access Controller 3 Controls direct reading and writing of data between external devices and memory, neither through CPU module 6 nor CPU module 6 intervention. The CPU module 6 can perform other operations during the transmission except for some processing at the beginning and end of data transmission. Thus, in most of the time, the CPU module 6 and the input/output control module 1 are operated in parallel. Therefore, the efficiency of the entire computer system is greatly improved.

[78] Direct Memory Access Controller 3 includes main memory address register, data quantity counter

Direct memory access control Z-state logic, direct memory access request trigger, data buffer register, interrupt mechanism.

FIG. 6 shows a schematic diagram of a flash memory unit (not shown) communicating with the CPU module 6 via the flash memory unit interface 4. Referring to FIG. 6, the CPU module 6 writes the flash memory cell through the flash memory cell interface 4, and the CPU module 6 sends a write command to the direct memory access controller 3 and the flash controller 2, thereby drawing the data to be written from the memory. 7 is transferred to the cache 5, after receiving the control command, the flash controller 2 determines whether the flash memory storage unit 10 connected to the flash memory cell interface ₄ can be written, and allocates an address for the data to be written, and then caches 5 The middle data is sent to the flash memory unit 10 through the flash memory unit interface 4; the CPU module 6 reads the flash memory unit 10 through the flash memory unit interface 4, and the CPU module 6 sends a read command to the direct memory access controller 3 and the flash memory. The controller 2, the flash controller 2 reads the data in the flash storage unit through the flash storage unit interface 4, and transfers it to the cache 5, and the data in the cache 5 is then sent to the CPU module 6 through the memory 7.

[80] According to the third embodiment of the present application, an alternative to an existing hard disk interface is realized by the flash controller 2, the direct memory access controller 3, the cache 5, and the flash memory unit interface 4, wherein the flash controller 2 The direct memory access controller 3, and the cache 5 can be integrated in one IC chip.

[81] As shown in FIG. 7, unlike the third embodiment described above, in the fourth embodiment, the flash controller 2, the direct memory access controller 3, and/or the cache 5 are built into the input/output control module 1. And a flash interface (not shown) is provided on the input/output control module 1. The input/output control module 1 with the flash controller 2, the direct memory access controller 3, and the cache 5 is connected to the flash memory control interface 4 through a flash interface, thereby realizing communication with the flash memory, and the principle and data transmission thereof The three implementations are the same and will not be repeated here. This design saves the number of chips that need to be placed on the motherboard and simplifies the wiring. [82] In the foregoing third and fourth embodiments, according to the characteristics of the flash memory storage unit itself, as shown in FIG. 8, after the operating system is installed, some control flash memory storage unit data read and write may be added in the operating system 8. The algorithm, such as: mapping algorithm 81, equalization algorithm 82, error checking and correcting (ECC) algorithm 83, and the like.

[83] The motherboard provided in the third and fourth embodiments described above integrates the flash controller and the direct memory access controller and the cache on the main board, compared with the existing hard disk in which the flash chip is used as the storage medium instead of the magnet. Since the hard disk is a component that needs to be added or replaced as a function of capacity or quality among the various components inside the computer, the flash controller and the direct memory access controller and the cache are placed in the hard disk, and each hard disk is added. Cost, and the integration of the flash controller and direct memory access controller with the cache on the motherboard will reduce the cost of adding and replacing memory, and there is no need for flash controllers and direct memory access control in the flash memory cells used with it. There is also a cache, so the fifth embodiment below provides a flash memory unit for use with the motherboard with flash memory of the present embodiment.

The fifth embodiment of the present application provides a flash memory storage unit for use with the motherboard provided in the third or fourth embodiment, and FIG. 9 is a schematic structural diagram of the flash memory storage unit 9 provided by the present application. The storage unit 9 includes a flash memory 910 and a communication interface 920. The communication interface 920 can cooperate with the flash storage control interface 4 provided in the third or fourth embodiment. Data operations within flash memory 910 are transmitted over communication interface 920.

The flash memory 910 may include a single flash chip or include at least two flash chips that are cascaded with each other.

The cascading mode may employ the cascading mode described above with reference to FIG. 10 according to the first embodiment of the present application.

[86] The communication interface 920 bus includes a data bus 921 and a control bus 922, and the data bus 921 can be 8-bit, 16-bit, 32-bit or 64-bit, etc., can support 8/16-bit flash memory cells, and can realize single channel, Dual or even four channels; Control Bus 922 may include RE#, WE#, ALE, CLE, WP#, RB, and several. 5# signal, etc.

[87] The specification of the data bus of the communication interface of the flash memory unit provided by the fifth embodiment and the signal of the control bus are both the specifications of the bus of the communication interface of the motherboard with the flash memory in the third and fourth embodiments. It is consistent with the signal of the control bus. After the connection is made, communication can be performed. The flash memory unit is also The simple structure reduces the cost of use.

[6] The sixth embodiment provides a reading method for implementing data communication control based on a main board with a flash memory unit. The transmission relationship of each component is as shown in FIG. 2. As shown in FIG. 11, the reading method includes the following steps: [89] S110, the direct memory access controller and the flash controller receive the read control command;

[90] S120, the flash controller controls the flash storage unit to send data to the cache;

[91] S130. The direct memory access controller controls the cache to send data to the memory.

[92] As shown in FIG. 12, the seventh embodiment further includes a read data error detection and error correction (ECC) step 1301 after the direct memory access controller of the sixth embodiment controls the buffer to send data to the memory step. Used to complete error detection and error correction for reading data in the flash memory, and control the bit error ratio. On other flash controllers (like flash drives, MP3 controllers), ECC algorithms are implemented in firmware due to limited computing power. It is also possible to include the ECC algorithm in the operating system based on the powerful computing power of the computer CPU, so that the algorithm can be upgraded by upgrading the operating system. This allows the latest technology flash memory to be supported without re-masking.

[93] The eighth embodiment provides a reading method for implementing data communication control based on a main board with a flash memory unit. The transmission relationship of each component is as shown in FIG. 2. As shown in FIG. 13, the reading step includes the following steps: The step in the steps consists of the following steps:

[94] S210, memory access controller and flash controller receive write control commands,

[95] S220, the direct memory access controller controls the data to be written from the memory to the cache;

[96] S230. The flash controller allocates an address to the flash storage unit;

[97] S240. The flash controller writes the data in the cache to the flash storage unit.

[98] The above method implements data communication control of a motherboard based on a flash memory unit, but in the communication process, due to data errors and the quality of the flash memory unit, the quality of the data communication is affected, so on the basis of the sixth embodiment. A seventh embodiment is proposed.

[99] As shown in FIG. 14, the ninth embodiment further includes: before the allocation of the address to the flash memory unit by the flash controller in the eighth embodiment, the address mapping step 2301 of ensuring that the read/write data corresponds to the physical block without defects. The mapping step 2301 implements an effective mapping between the logical block address and the physical block address in the flash memory by the mapping algorithm, and ensures that each logical block of the read and write data can correspond to a defect-free physical block to ensure data reliability and integrity. The above description is only the embodiment of the present application, and thus does not limit the scope of the patent application, and the equivalent structure or equivalent process transformation made by using the specification and the drawings of the present application, or directly or indirectly applied to other related technologies. The scope of the invention is included in the scope of patent protection of this application.

Claims

Claim

1. A motherboard for providing a flash memory function, the motherboard comprising an input /

An output control module, further comprising:

a flash storage unit integrated on the motherboard for storing data;

a flash controller, coupled to the flash memory unit, the flash controller capable of receiving an instruction from the input/output control module, and controlling the flash memory unit according to the received instruction; a direct memory access controller, and the flash memory a controller connection, the direct memory access controller being capable of inputting from the input

The output control module receives the instruction, and cooperates with the flash controller to control the flash memory storage unit according to the received instruction;

a cache, coupled to the direct memory access controller, and in communication with the flash memory unit in accordance with control of the direct memory access controller and the flash controller.

2. As claimed in claim 1

The motherboard is characterized in that: the flash controller, the direct memory access controller and the cache are built in the input I output control module.

3. According to claim 1 or 2

The motherboard is characterized in that: the flash memory unit comprises a single chip flash chip or at least two flash chips that are cascaded with each other.

4. A motherboard for providing a flash memory function, the motherboard includes a memory control module and an input/output control module, and the method further includes:

a flash memory unit communication interface capable of being connected to a flash memory unit;

a flash controller, communicatively coupled to the flash memory unit, the flash controller being capable of inputting from the

The output control module receives the instruction, and controls, by the flash memory storage unit communication interface, a flash memory storage unit connected to the flash memory unit communication interface according to the received instruction;

a direct memory access controller coupled to the flash controller, the direct memory access controller being capable of inputting from the input

Outputting a control command of the control module, and cooperating with the flash controller according to the received command The flash memory unit communication interface controls a flash memory unit connected to the flash memory unit communication interface;

Cache, connected to the direct memory access controller, and according to the direct memory access controller and the control of the flash controller, through the flash memory unit communication interface and a flash memory connected to the flash memory unit communication interface The storage unit communicates.

5. According to claim 4

6. One capable of complying with claim 4

The flash memory unit used in conjunction with the motherboard is characterized in that: the flash storage unit comprises:

Flash memory module;

A communication interface that cooperates with a flash memory unit communication interface on the motherboard.

7. According to claim 6

The flash memory storage unit is characterized in that: the flash memory storage module comprises a single chip flash chip or at least two flash chips that are cascaded with each other.

8. A claim based on claim 1

The data reading method implemented by the main board is characterized in that: the reading method comprises the following steps: the direct memory access controller and the flash controller receive the read control command;

The flash controller controls the flash storage unit to send the data to be read to the cache;

The direct memory access controller controls the cache to send data to memory.

9. According to claim 8

The reading method is characterized in that: after the direct memory access controller controls the buffer to send data to the memory step, the method further comprises the steps of performing error detection and error correction on the data.

10. A method based on claim 1

The data writing method implemented by the main board is characterized in that the writing method comprises the following steps The memory access controller and the flash controller receive a write control command;

The direct memory access controller controls the data to be written from the memory to the cache;

The flash controller allocates an address to the flash memory unit;

The flash controller writes the data in the cache to the flash storage unit according to the assigned address. 11. According to claim 10

The writing method is characterized in that: the flash controller allocates an address to the flash memory unit, and further includes a mapping step of ensuring a correct mapping between the logical address and the physical address in the flash memory unit.