CN106776404B - SSD (solid State disk) master control Buffer, SSD master control and SSD non-aligned write data transmission control method - Google Patents
SSD (solid State disk) master control Buffer, SSD master control and SSD non-aligned write data transmission control method Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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Abstract
The invention discloses an SSD master control Buffer, an SSD master control and SSD non-aligned write data transmission control method.A CPU only participates in one step in the whole read filling process, and the application, data synchronization and Buffer release of the Buffer are automatically completed by logic in other processes according to a data transmission control rule, so that the consumption of CPU time resources is greatly saved, and the capacity of the CPU for processing other transactions is improved; in addition, in the method of the invention, once the Read DMA finishes writing the data of the part2 and the part3, the RD flag of the part2 and the part3 is set at this time, even if the data of the part1 is not prepared, the Read DMA still immediately executes the operation of reading the part1, the part2 and the part3, so that the waiting time of the Read DMA is greatly reduced, and the transmission efficiency between the DMAs is effectively improved.
Description
In the technical field of
The invention relates to the field of SSD data reading and writing, in particular to an SSD master control Buffer, an SSD master control method and an SSD non-aligned write data transmission control method.
Background
In the mainstream SSD master control, the front end must read and write data in a sector (512-byte) length data alignment manner, and the SSD usually employs a unit (unit size is 4KByte or 8KByte) alignment manner for facilitating management to flush data and check and modify table entries. Non-aligned write refers to write behavior in which the range of read and write data is not aligned according to units, as shown in fig. 1. In the scenario of fig. 1, the non-aligned portion (yellow region) needs to be filled up by a read operation, which is called read fill, and then the data is flushed down to the flash and re-tabulated after filling up.
The existing method for writing the non-aligned SSD in conjunction with fig. 1 and 2 can be decomposed into the following steps:
the method comprises the steps that 1, a CPU allocates a Write cache for the Write DMA from a Buffer, the cache is marked as Buffer A, and the size of the Buffer A is equal to the data size of Part2+ Part1+ Part 3;
2, the CPU starts Write DMA Write data part1 to a specified position in the buffer A;
3, the CPU starts Read DMA to write data part2/part3 to the specified position in the buffer A;
when the data transmission of Part1 or Part2 or Part3 is completed, reporting the completion of the CPU writing by Wirte DMA or Read DMA;
interrupting, entering the next step when the transmission of the part1, the part2 and the part3 is finished, or waiting;
5, CPU starts Read DMA to Read part2+ part1+ par 3;
reporting the interruption of the Read completion of the CPU after the Read DMA finishes reading;
and 7, releasing the buffer A space by the CPU.
As known from the existing method, almost every key step needs the participation of a CPU, the occupation of CPU time resources is serious, and the operation is more complicated. The condition of entering the 5 th step from the step 4 is that the data transmission of part2, part1 and part3 is finished, the waiting time is too long, and the transmission efficiency is low. It is because of the above disadvantages that the bandwidth of the SSD is reduced significantly when performing non-aligned writes as compared to aligned writes.
In summary, the following disadvantages are known in the prior art:
(1) the method has the advantages that more CPU time resources are occupied, steps of the method in the prior art are more, the CPU is basically required to be involved in transmission processing, obviously, the CPU time resources are seriously consumed, the data transmission delay between DMA (direct memory access) is inevitably increased, meanwhile, the capability of the CPU for processing other tasks is weakened, and the performance of the whole SSD system is affected.
(2) The invalid waiting time between the DMAs is too long, and the transmission efficiency is low. As can be seen from the description of the prior art method, the data transfer of the Read DMA can be started only after all of the Part1, Part2, and Part3 complete the data transfer, that is, the Read DMA has a long time waiting for the data transfer to complete, and these invalid waits are also an important reason for the long transfer delay.
The nouns to which the invention relates are explained or abbreviated as follows:
SSD: solid State Drive, a Solid State disk, a storage device that stores user data using a Flash medium.
DMA: direct Memory Access; direct memory access module
Buffer: caching;
and (3) Sector: sector, in SSD SATA protocol often referred to as a contiguous 512 byte length unit of data
Disclosure of Invention
The invention aims to solve the technical problems that aiming at the defects of the prior art, the SSD master control Buffer, the SSD master control and the SSD non-aligned write data transmission control method are provided, the problems that the existing non-aligned write method occupies more CPU time resources and has low transmission efficiency among DMAs are solved, the data transmission efficiency among DMAs is improved, the invalid waiting is reduced, and the SSD data throughput capacity is finally improved.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows: an SSD master control Buffer comprises a plurality of storage units; the storage unit also comprises a WD Flag space and an RD Flag space, wherein each storage unit has exclusive L-bit information in the WD Flag space to describe the writable state of the storage unit, and each storage unit has exclusive L-bit information in the RD Flag space to describe the readable state of the storage unit; if the exclusive L bit information of the WD flag space corresponding to a certain storage unit is in a state of 0, the WD flag space indicates that the Write DMA can Write the storage unit; if the WD flag corresponding to the storage unit is in a state 1, the storage unit is indicated to be completely written by the Write DMA or a reserved space is reserved for the Read DMA; if the exclusive L bit information of the RD Flag space corresponding to a certain memory cell is in a state 0, the Read DMA can Write the memory cell, and if the exclusive L bit information of the RD Flag space corresponding to the memory cell is in a state 1, the Read DMA can Write the memory cell completely or Read DMA can Write the memory cell completely; in a non-aligned scenario, the Write DMA sets a WD flag for reading a fill buffer space, so that the READ DMA completes writing the READ fill buffer space data and simultaneously completes reading the READ fill buffer space and the data of the non-unit aligned portion.
L > -1, the memory cell size is 512 bytes. The basic unit of transfer in the SSD industry standard is 512 bytes, so the design storage unit size is 512 bytes.
Correspondingly, the invention provides an SSD master control, which comprises a CPU, a Write DMA and a Read DMA; the Buffer is also included; the Write DMA reports the data transmission address and the length of the non-unit alignment part1 to the CPU; the CPU calculates the transmission starting address and the transmission length of part2 and part3 according to the transmission address and the transmission length, calculates the transmission starting address and the transmission length of part1+ part2+ part3, and sequentially issues a request for writing part2 data, a request for writing part3 data and a request for reading part1+ part2+ part3 data to the Read DMA; where part1 is a non-unit alignment part; part3, the last unit, needs to read the padding; READ DMApart1+ part2+ part3 data READ completes writing part2, part3 data, and completes reading part1+ part2+ part3 data.
Correspondingly, the invention also provides a method for controlling the transmission of the non-aligned write data of the SSD by utilizing the SSD master control, which comprises the following steps:
1) the Write DMA moves a Write pointer to the next unit, sets exclusive L bit information of a WDflag space corresponding to a non-unit alignment part1 to be 1, simultaneously starts part1 data transmission, and reports a CPU transmission address and length;
2) the CPU calculates the transmission starting address and the length of part2 and part3 according to the transmission address and the length, calculates the transmission starting address and the data length of part1+ part2+ part3, and sequentially issues a request for writing part2 data, a request for writing part3 data and a request for reading part1+ part2+ part3 data to the Read DMA; where part1 is a non-unit alignment part; part3, the last unit, needs to read the padding;
3) READ DMA completes writing part1, part2 data, and READ DMA completes reading part1+ part2+ part3 data.
In step 1), if the Write pointer is moved to the next unit by the Write DMA and exceeds the Buffer boundary, the next read-Write position automatically jumps to the starting position of the left boundary of the Buffer to read and Write when the Write pointer is read and written to the right boundary of the Buffer.
In step 1), the rule for starting part1 data transmission is as follows:
A) if the WD flag space corresponding to a memory unit is found to be 0 when the Write DMA needs to Write the memory unit, immediately writing data into the space, and immediately setting the WD flag space and the RDflag space corresponding to the memory unit to be 1 after the memory unit is written;
B) if the Write DMA needs to Write a certain storage unit, the WD flag space corresponding to the storage unit is found to be 1, the data transmission of the Write DMA is suspended until the WD flag space of the space is cleared by other modules (for example, a Read DMA module or a CPU), and the Write DMA continues the data transmission according to the rule A).
In step 3), the READ DMA completes writing the data of part1 and part2 to meet the following rules:
I) if the Read DMA needs to write a certain storage unit, when the data is written, the RD flag space values corresponding to the storage unit are all 0, the data is immediately written into the storage unit, and after the storage unit is fully written, the RD flag space corresponding to the storage unit is immediately set to be 1;
II) if the Read DMA needs to write a certain storage unit, when the data is written, the RD flag space value corresponding to the storage unit is found to be 1, the data transmission of the Read DMA is suspended until the RD flag space of the storage unit is cleared by other modules by 0, and the Read DMA continues to transmit data according to the rule I).
In step 6), Read DMA completes reading of part1+ part2+ part3 data according to the following rule:
i) if the Read DMA needs to fetch data from a certain storage unit, finding that the RD flag space values corresponding to the storage unit are all 1, taking away the data in the storage unit, and clearing 0 the WD flag space and the RD flag space corresponding to the storage unit after all the data in the storage unit are taken away;
ii) if the Read DMA needs to fetch data from a certain storage unit, if the RD flag space value corresponding to the storage unit is found to be 0, suspending the data transmission of the Read DMA until the RD flag space of the storage unit is set to 1 by other modules, and continuing the data transmission of the Read DMA according to the rule i).
Compared with the prior art, the invention has the beneficial effects that: according to the invention, the buffer space distribution, the data synchronization and the buffer space release in the DMA transmission and read filling operations are automatically completed through the DMA transmission control rule realized by combining the WD flag and the RD flag with hardware, so that the CPU is released from the heavy processing, the precious CPU time resource is greatly saved, and the capacity of the CPU for processing other services of the SSD is effectively improved; by combining a WD flag mechanism and an RD flag mechanism, data reading operation can be immediately executed after the ReadDMA finishes data writing, and the Read DMA does not need to start data transmission after the Write DMA finishes data transmission, so that invalid waiting time of the Read DMA is greatly reduced, and the DMA transmission efficiency is obviously improved; in a non-aligned scene, the Write DMA ingeniously sets a WD flag of a cache space for executing Read filling to prevent the Write DMA from overwriting, and the RD flag is not set to execute Read filling reserved space for the Read DMA, so that the whole Write DMA under the non-aligned writing is written, and Read DMA Read filling and Read DMA data reading operations depend on the WD flag and the RD flag to be automatically matched.
Drawings
FIG. 1 is a schematic diagram of a non-aligned write data structure;
FIG. 2 is a diagram of a conventional data transmission management hardware architecture;
FIG. 3 is a diagram illustrating data transfer management between DMAs in an SSD according to the present invention.
Detailed Description
The solution of the invention is shown in figure 3. The most difference from the prior art is that two hardware modules WD flag and RD flag are added.
WD Flag (Write DMA Flag) definition: according to the SSD front-end protocol, SSD transmission data is definitely sector aligned, and each sector is 512 bytes in size. In this embodiment, it is therefore provided that each sector space in the Buffer has a dedicated 1-bit message associated with it in the WD Flag. WD Flag of a certain sector space is 0, which indicates that Write DMA can Write the sector space; if WD Flash is set to 1, the sector space is written to full by Write DMA or reserved for Read DMA data.
RD Flag (Read DMA Flag) definition: according to the SSD front-end protocol, SSD transmission data is definitely sector aligned, and each sector is 512 bytes in size. In this embodiment, it is therefore provided that each sector space in the Buffer has a dedicated 1-bit message associated with it in the RD Flag. The RD Flag of a certain sector space is 0, which means that the Read DMA can Write the sector space, and if the RD Flag is set to 1, the sector space is fully written by the Write DMA or fully written by the Read DMA.
With WD Flag and RD Flag, the hardware needs to implement the following DMA transfer control rules:
① if the WD flag corresponding to the Write DMA needs to be 0 when the Write DMA needs to Write a sector space, the data is immediately written into the space, and after 512 bytes are written, the WD flag and the RD flag corresponding to the space are immediately set to be 1.
② if the Write DMA needs to Write a sector space and finds that the WD flag corresponding to the Write DMA is 1, the data transmission of the Write DMA is suspended until the WD flag of the space is cleared by other modules to be 0, and the Write DMA continues the data transmission according to the rule ①.
③ if the Read DMA needs to write some sector space fetch data and finds that the corresponding RD flag values are all 0, the data is immediately written into the space, and after 512 bytes are written, the RD flag value corresponding to the space is immediately set to 1.
④ if the Read DMA needs to write some sector space fetch data and finds that the corresponding RD flag values are all 1, the data transmission of the Read DMA is suspended until the RD flag value of the space is cleared by other modules by 0, and the Read DMA continues to transmit data according to the rule ③.
⑤ if the Read DMA needs to fetch data from a sector space, if the corresponding RD flag values are all 1, then take away the data in the space, and after taking away 512 bytes, clear 0 for both the WD flag and the RD flag corresponding to the space.
⑥ if the corresponding RD flag value is found to be 0 when the Read DMA needs to fetch data from a sector space, the data transmission of the Read DMA is suspended until the RD flag value of the space is set to 1 by other hardware modules, and the Read DMA continues to transmit data according to the rule ⑤.
⑦ Write DMA/Read DMA has Buffer loop Read-Write function, that is, when reading and writing to the right boundary of Buffer, the next Read-Write position automatically jumps to the starting position of the left boundary of Buffer to Read and Write.
⑧ Write DMA needs to set the WD flag of the start unit that needs to read the padding part to 1 when writing a certain space, and not to operate the RD flag (e.g. the WD flag corresponding to part2 data in FIG. 2).
After the above definitions and rules are provided, if the same work is to be completed, it is assumed that the values of the WD flag and the RD flag are both 0. The scheme comprises the following implementation steps:
(1) write DMA moves the Write pointer from the current unit to the next unit (if the buffer boundary is exceeded, rule ⑦ applies), sets the WD flag of the space where the starting unit needs to read padding (part2) to 1 (rule ⑧), starts part1 data transfer (rules ① and ② are applied during transfer), and reports the CPU transfer address and length,
(2) the CPU calculates the transmission starting address and the length of part2 and part3 and the transmission starting address and the data length of part1+ part2+ part3 according to the transmission address and the length, and sequentially issues a request for writing part2 data, a request for writing part3 data and a request for reading part1+ part2+ part3 data to the Read DMA. These requests are buffered in the Read DMA hit FIFO and executed in sequence
(3) The READ DMA completes writing of part1 and part2 data according to rules ③ and ④, the READ DMA completes reading of part1+ part2+ part3 data according to rules ⑤ and ⑥, obviously, after the READ DMA completes data transmission of part1+ part2+ part3, WD flag and RD flag are requested to be 0, namely, the buffer is automatically released.
From the above operation flow, in the whole read filling process, the CPU only participates in one step, and the application of the buffer, the data synchronization, and the release of the buffer are automatically completed by the logic in other processes according to the data transmission control rule, so that the consumption of the CPU time resource is greatly saved, and the capability of the CPU to process other transactions is improved; in addition, in the method, once the Read DMA finishes writing the data of the part2 and the part3, the RD flag of the part2 and the part3 is set at the moment, and even if the data of the part1 is not prepared, the Read DMA still immediately executes the operation of reading the part1, the part2 and the part3, so that the waiting time of the Read DMA is greatly shortened, and the transmission efficiency between the DMAs is effectively improved.
Specifically, the principle of the present invention is as follows:
1. the method comprises the steps of appointing a storage unit with a specified size (such as 512 bytes) and WD Flag space and RD Flag, wherein the Buffer is composed of a plurality of storage units, and each storage unit has exclusive 1-bit or multi-bit information corresponding to the storage unit in the WD Flag and the RD Flag. If the RD Flag of a certain memory cell is in a state of 0, the memory cell is not fully written; if the RDflag of a certain memory cell is in the state 1, the memory cell is full. If the WD Flag of the memory cell is in state 0, the memory cell Write DMA can be written, and if the WD Flag of the memory cell is in state 1, the memory cell Write DMA can not be written.
2. On the basis of 1, when the Write DMA needs to Write a certain memory cell in the buffer, if the WD Flag of the Write DMA is in a state of 0, the Write DMA can Write the memory cell, and after the memory cell is fully written, the WD Flag and the RD Flag of the Write DMA are immediately set to be 1; if WDFlag is in state 1, the Write DMA cannot Write the memory cell, and the Write operation of the Write DMA is suspended until WDFlag is changed to state 0, so that the Write DMA can be activated to continue writing.
3. On the basis of 3, when the Read DMA needs to write a certain memory cell in the buffer, if the RD Flag is in a state of 0, the Read DMA can write the memory cell, and after the memory cell is fully written, the RD Flag is set to be 1 immediately; and if the RD flag is 1, the Read DMA can not write the storage unit, and the write operation of the Read DMA is suspended until the RD flag is changed into the state 0, so that the Read DMA can be activated to continue writing.
4. On the basis of 1, when the Read DMA needs to Read a certain memory cell in the buffer, if the RD Flag of the Read DMA is in a state 1, the Read DMA can Read the memory cell, and after the memory cell is Read, the WD Flag and the RD Flag of the Read DMA are immediately set in a state 0; if the RD Flag is in the state 0, the Read DMA cannot Read the memory unit, and the Read operation of the Read DMA is suspended until the RD Flag is changed into the state 1, so that the Read DMA can be activated to continue reading.
5. On the basis of 2 and 3, when the Write DMA/Read DMA Write exceeds the end of the Buffer, the Write DMA/Read DMA Write pointer jumps to the start position of the Buffer to continue writing data.
6. On the basis of 4, when the Read DMA Read exceeds the end point of the Buffer, the Read DMA Read pointer jumps to the starting position of the Buffer to continue reading data.
7. On a 4 basis, Write DMA can automatically complete the allocation of the target space for data storage without concern as to whether the target space exceeds the buffer size, whether the target space is occupied by other transfers, as these are automatically controlled by WD Flag. And setting WD flag of the start unit needing to read the filling part to 1 and not operating RD flag.
Claims (9)
1. An SSD master cache comprises a plurality of storage units; the method is characterized by further comprising a WD Flag space and an RD Flag space, wherein each storage unit has exclusive L-bit information in the WD Flag space to describe the writable state of the storage unit, and each storage unit has exclusive L-bit information in the RD Flag space to describe the readable state of the storage unit; if the exclusive L bit information of the WD flag space corresponding to a certain storage unit is in a state of 0, the WD flag space indicates that the Write DMA can Write the storage unit; if the WD flag corresponding to the storage unit is in a state 1, the storage unit is indicated to be completely written by the Write DMA or a reserved space is reserved for the Read DMA; if the exclusive L bit information of the RD Flag space corresponding to a certain memory cell is in a state 0, it indicates that the Read DMA can Write the memory cell, and if the exclusive L bit information of the RD Flag space corresponding to the memory cell is in a state 1, it indicates that the memory cell is fully written by the Write DMA or fully written by the Read DMA; in a non-aligned scenario, the WriteDMA sets a WD flag for executing READ filling of a cache space, so that the READ DMA completes writing of the READ filling of the cache space data and simultaneously completes reading of the READ filling of the cache space and the data of the non-unit aligned part.
2. The cache of claim 1, wherein L > -1.
3. The cache of claim 1, wherein the storage unit size is 512 bytes.
4. An SSD master control comprises a CPU, a Write DMA and a Read DMA; the method is characterized by further comprising the cache of any one of claims 1 to 3; the Write DMA reports the data transmission address and the length of the non-unit alignment part1 to the CPU; the CPU calculates the transmission starting address and the transmission length of part2 and part3 according to the transmission address and the transmission length, calculates the transmission starting address and the transmission length of part1+ part2+ part3, and sequentially issues a request for writing part2 data, a request for writing part3 data and a request for reading part1+ part2+ part3 data to the Read DMA; where part1 is a non-unit alignment part; part3, the last unit, needs to read the padding; the READ DMA completes writing of part2, part3 data, and simultaneously completes reading of part1+ part2+ part3 data.
5. A method for controlling the transfer of the SSD non-aligned write data by the SSD master of claim 4, comprising the steps of:
1) the Write DMA moves a Write pointer to the next unit, the filling part, namely part2, which needs to be read by the starting unit is read, the exclusive L bit information position 1 of the WD flag space is corresponding to the filling part, part1 data transmission is started at the same time, and the transmission address and the length of the CPU are reported;
2) the CPU calculates the transmission starting address and the length of part2 and part3 according to the transmission address and the length, calculates the transmission starting address and the data length of part1+ part2+ part3, and sequentially issues a request for writing part2 data, a request for writing part3 data and a request for reading part1+ part2+ part3 data to the Read DMA; where part1 is a non-unit alignment part; part3, the last unit, needs to read the padding;
3) READ DMA completes writing part2, part3 data, and READ DMA completes reading part1+ part2+ part3 data.
6. The method according to claim 5, wherein in step 1), if the Write DMA moves the Write pointer from the current unit to the next unit and exceeds the buffer boundary, the next read/Write location automatically jumps to the starting position of the left boundary of the buffer for reading and writing when the read/Write is at the right boundary of the buffer.
7. The method of claim 6, wherein in step 1), the rule for starting part1 data transmission is as follows:
A) if the Write DMA needs to Write a certain storage unit, the exclusive L bit information of the WD flag space corresponding to the storage unit is found to be in a state of 0, data is immediately written into the space, and after the storage unit is written, the exclusive L bit information of the WD flag space and the exclusive L bit information of the RD flag space corresponding to the storage unit are immediately set to be in a state of 1;
B) and if the exclusive L bit information of the WD flag space corresponding to the storage unit is found to be in a state 1 when the Write DMA needs to Write into the storage unit, suspending the data transmission of the Write DMA until the exclusive L bit information of the WD flag space corresponding to the storage unit is cleared by other modules by 0, and continuing the data transmission of the Write DMA according to the rule A).
8. The method of claim 7, wherein in step 3), READ DMA completion writes part1, part2 data according to the following rules:
I) if Read DMA needs to write a certain storage unit, when data is written, the exclusive L bit information of the RD flag space corresponding to the storage unit is found to be in a state of 0, the data is immediately written into the storage unit, and after the storage unit is fully written, the exclusive L bit information state of the RD flag space corresponding to the storage unit is immediately set to be 1;
II) if the Read DMA needs to write a certain storage unit, when the Read DMA writes data, the exclusive L bit information of the RD flag space corresponding to the storage unit is found to be in a state 1, the data transmission of the Read DMA is suspended until the RD flag space of the storage unit is cleared by other modules by 0, and the Read DMA continues to transmit data according to the rule I).
9. The method of claim 8, wherein Read DMA complete part1+ part2+ part3 data Read complies with the following rules:
i) if the Read DMA needs to fetch data from a certain storage unit, finding that exclusive L bit information of the RD flag space corresponding to the storage unit is in a state 1, taking away the data in the storage unit, and clearing 0 both the WD flag space and the RD flag space corresponding to the storage unit after all the data of the storage unit are taken away;
ii) if the Read DMA needs to fetch data from a certain storage unit, the exclusive L bit information of the RD flag space corresponding to the storage unit is found to be in a state 0, the data transmission of the Read DMA is suspended until the RD flag space of the storage unit is set to be 1 by other modules, and then the Read DMA continues the data transmission according to the rule i).
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| CN103377152A (en) * | 2012-04-26 | 2013-10-30 | 深圳市朗科科技股份有限公司 | Write operation control method and write operation device for solid state disk |
| CN102693198A (en) * | 2012-05-12 | 2012-09-26 | 北京忆恒创源科技有限公司 | DMA (direct memory access) transmission method and system |
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