CN106776404A - SSD master control Buffer, SSD master controls and SSD non-alignments write data transfer control method - Google Patents
SSD master control Buffer, SSD master controls and SSD non-alignments write data transfer control method Download PDFInfo
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- CN106776404A CN106776404A CN201611177857.6A CN201611177857A CN106776404A CN 106776404 A CN106776404 A CN 106776404A CN 201611177857 A CN201611177857 A CN 201611177857A CN 106776404 A CN106776404 A CN 106776404A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/28—DMA
- G06F2213/2806—Space or buffer allocation for DMA transfers
Abstract
Data transfer control method is write the invention discloses a kind of SSD master controls Buffer, SSD master control and SSD non-alignments, in whole reading filling process, CPU has been only involved in a step, other processes are all automatically performed the release of the application of buffer, data syn-chronization, buffer by logic according to Data Transmission Controlling rule, the consumption of CPU time resource has been greatly saved, the ability that CPU processes other affairs has been improved；In addition, in the methods of the invention, Read DMA once complete to write part2, part3 data, the now RD flag set where part2, part3, even if part1 data are not ready to, but Read DMA are still immediately performed reading part1+part2+part3 operations, so greatly reduce efficiency of transmission between Read DMA stand-by period, effectively lifting DMA.
Description
Technical field
The present invention relates to SSD reading and writing datas field, particularly a kind of SSD master controls Buffer, SSD master control and SSD non-alignments
Write data transfer control method.
Background technology
In main flow SSD master controls, front end must read and write data in the way of sector (512Byte) length data is alignd,
And SSD is for convenience of managing frequently with brush data under unit (unit sizes be 4KByte or 8KByte) alignment thereof and look into and change table
.Non-alignment is write and refers to that the scope of read-write data writes behavior not in accordance with what unit alignd, as shown in Figure 1.Under Fig. 1 scenes, need
Will be by read operation by non-alignment part（Yellow area）Polishing, polishing operation is referred to as reading filling, plays brush data after polishing again
To flash and change table.
SSD non-alignments are write with reference to Fig. 1, Fig. 2 existing method can be analyzed to following steps：
For Write DMA distribute write buffer from Buffer, the caching is designated as bufferA to 1.CPU, and bufferA sizes are equal to
Part2+part1+part3 size of data；
2.CPU starts specified location in Write DMA write datas part1 to bufferA；
3.CPU starts specified location in Read DMA write datas part2/part3 to bufferA；
When 4.Part1 or part2 or part3 data transfers are completed, Wirte DMA or Read DMA report CPU write to complete；
Interrupt, when part1+part2+part3 all end of transmissions, into next step, otherwise wait for；
5.CPU starts Read DMA and reads part2+part1+par3；
After 6.Read DMA run through, CPU is reported to run through interruption；
7.CPU release bufferA spaces.
Knowable to existing method, almost each committed step is required for CPU to participate in, and takes CPU time resource seriously, and behaviour
Make relatively complicated.Condition from step 4 into the 5th step is part2, part1, part3 data all end of transmissions, stand-by period
Long, efficiency of transmission is low.Exactly because also there is disadvantages mentioned above, cause SSD to be write in execution non-alignment and compare the band that alignment is write
Width declines very severe.
To sum up, it is known that prior art has the following disadvantages：
(1) occupancy CPU time resource is more, and art methods step is a lot, and is required for CPU to get involved in transmission process substantially
In, it is clear that CPU time resource consumption is serious, necessarily causes the increase of data transfer delay between a DMA, also results at CPU
The ability for managing other tasks dies down, and ties down the performance of whole SSD systems.
(2) the invalid stand-by period is long between DMA, and efficiency of transmission is low.Understood with reference to the description of art methods, only
After Part1, part2, part3 complete data transfer, can just start the data transfer of Read DMA, i.e. Read DMA have
Significant period of time is waiting data transfer to complete, and these invalid waits are also a transmission delay important original more long
Cause.
Explanation of nouns of the present invention is abridged as follows：
SSD：Solid State Drive, solid state hard disc, a kind of storage device of utilization Flash media storage user data.
DMA：Direct Memory Access；Direct memory access module
Buffer：Caching；
Sector：Sector, often refers to continuous 512Byte length datas unit in SSD SATA protocols.
The content of the invention
The technical problems to be solved by the invention are, in view of the shortcomings of the prior art, providing a kind of SSD master controls Buffer, SSD
Master control and SSD non-alignments write data transfer control method, solve to take in existing non-alignment write method CPU time resource it is more,
Data transmission efficiency between the low problem of efficiency of transmission between DMA, lifting DMA, reduces invalid wait, final lifting SSD data throughputs
Ability.
In order to solve the above technical problems, the technical solution adopted in the present invention is：A kind of SSD master controls Buffer, including it is many
Individual memory cell；Also include WD Flag spaces and RD Flag spaces, and each memory cell has specially in WD Flag spaces
The Lbit information of category describes the writable state of the memory cell, and each memory cell has exclusive in RD Flag spaces
What Lbit information described the memory cell can read state；If the exclusive Lbit letters in the corresponding WD flag spaces of certain memory cell
It is state 0 to cease, then it represents that the writeable memory cell of Write DMA；If the corresponding WD flag of the memory cell are state 1, table
Show the memory cell is expired by Write DMA writes or is Read DMA write data headspaces；If certain memory cell is corresponding
The exclusive Lbit information in RD Flag spaces is state 0, then it represents that the writeable memory cell of Read DMA, if the memory cell pair
The exclusive Lbit information in the RD Flash spaces answered is state 1, then it represents that the memory cell expired by Write DMA writes or by
Read DMA writes are expired.
L>=1, the memory cell size is 512B.The elementary cell transmitted in SSD professional standards is 512B, so
Design memory cell size is 512B.
Accordingly, the invention provides a kind of SSD master controls, including CPU, Write DMA and Read DMA；Also include above-mentioned
Buffer；Non- unit aligned portions, the i.e. data transfer address of part2 and length are reported CPU by the Write DMA；Institute
CPU is stated according to transmission address and length, the transmission initial address and length of part2, part3 is calculated, part1+part2+ is calculated
The transmission initial address and data length of part3, issue to Read DMA and write part2 request of data, write part3 data successively
Request, reading part1+part2+part3 request of data；Wherein, part1 is non-unit to its part；Part3 is that end unit is needed
Read to fill part；READ DMA complete to write part1, part2 data, while completing to read the reading of part1+part2+part3 data
Take.
Accordingly, data are write to SSD non-alignments using above-mentioned SSD master controls present invention also offers one kind and is transmitted control
Method, comprise the following steps：
1）Write pointer is moved to next unit by Write DMA, and initial unit is needed to read filling part, i.e. part2 correspondences
The exclusive Lbit information in WD flag spaces put 1, while starting part1 data transfers, and report CPU to transmit address and length
Degree；
2）CPU calculates the transmission initial address and length of part2, part3 according to transmission address and length, calculates part1+
The transmission initial address and data length of part2+part3, issue to Read DMA and write part2 request of data, write part3 successively
The request of data, reading part1+part2+part3 request of data；Wherein, part1 is non-unit to its part；Part3 is end
Unit needs to read filling part；
3）READ DMA complete to write part1, part2 data, and Read DMA complete to read part1+part2+part3 digital independents.
Step 1）In, if write pointer is moved to next unit by Write DMA, more than buffer borders, then read and write
During to Buffer right margins, read and write position automatic jumps to the left margin original position of Buffer and is written and read next time.
Step 1）In, the rule for starting part1 data transfers is：
A）If Write DMA need to write certain memory cell, it is found that the corresponding WD flag spaces of the memory cell are 0, then immediately
The space is write data into, after writing the memory cell, immediately will WD flag spaces corresponding with the memory cell and RD flag
Put 1 in space；
B）If Write DMA need to write certain memory cell, it is found that the corresponding WD flag spaces of the memory cell are 1, then suspend
The data transfer of Write DMA, until the WD flag spaces in the space are by other modules（For example, Read dma modules or CPU）
After clear 0, Write DMA press rule A again）Continue data transfer.
Step 3）In, READ DMA complete to write the following rule of part1, part2 data adaptation：
I）If Read DMA need to write certain memory cell, access according to when find the corresponding RD flag spatial values of the memory cell all
It is 0, then writes data into the memory cell immediately, after writing the full memory cell, immediately will RD corresponding with the memory cell
Flag puts 1 in space；
II）If Read DMA need to write certain memory cell, access according to when find the corresponding RD flag spatial values of the memory cell all
It is 1, then suspends the data transfer of Read DMA, until the RD flag spaces of the memory cell are by other modules clear 0, Read
DMA is further continued for by regular I）Continue data transfer.
Step 6）In, Read DMA complete to read the following rule of part1+part2+part3 digital independents adaptation：
i）If Read DMA need from certain memory cell access according to when, find the corresponding RD flag spatial values of the memory cell all
It is 1, then takes the data in the memory cell away, after the data of the memory cell are all taken away, by the memory cell pair
The WD flag spaces and RD flag spaces all clear 0 answered；
ii）If Read DMA need from certain memory cell access according to when, it is found that the corresponding RD flag spatial values of the memory cell are
0, then suspend the data transfer of Read DMA, until after the RD flag spaces of the memory cell put 1 by other modules, Read
DMA presses rule i again）Continue data transfer.
Compared with prior art, the advantageous effect of present invention is that：Filling behaviour will be transmitted and read to the present invention between DMA
What spatial cache distribution, data syn-chronization, the spatial cache release in work were all realized by WD flag and RD flag combined with hardware
DMA transfer controls rule to be automatically performed, and CPU is freed from above-mentioned these heavy treatment, greatly saves valuable
CPU time resource, the effective ability of lifting CPU treatment SSD other business；With reference to WD flag and RD flag mechanism, Read
After DMA completes data write-in, data read operation just can be immediately performed, Read DMA simultaneously without waiting for Write DMA datas
Just log-on data transmission, greatly reduces the Read DMA invalid stand-by period, so that DMA transfer efficiency is obtained after being transmitted
It is obviously improved；Under non-alignment scene, Write DMA will cleverly perform the WD flag set of the spatial cache for reading filling, with
Itself covering is prevented to write, without going set RD flag to read filling headspace for Read DMA are performed, so as to allow whole non-alignment
The Write DMA writes for writing, Read DMA readings filling, Read DMA take data manipulation dependence WD flag and RD flag and match somebody with somebody automatically
Altogether.
Brief description of the drawings
Fig. 1 writes data structure schematic diagram for non-alignment；
Fig. 2 is frequently-used data transfer management hardware configuration；
Fig. 3 is data transfer management schematic diagram between DMA in SSD in the present invention.
Specific embodiment
The present invention program is as shown in Figure 3.Its maximum difference with prior art two hardware module WD flag that have been many
With RD flag.
WD Flag (Write DMA Flag) are defined：It can be seen from SSD font end protocols, SSD transmission data are certainly
Sector aligns, and each sector size is 512B.Therefore each sector space is in WD in specifying Buffer in this programme
There is exclusive 1bit information corresponding in Flag.The WD Flag in certain sector space are that 0 expression Write DMA are writeable to be somebody's turn to do
Sector spaces；If its WD Flash puts the 1 expression sector spaces and being expired by Write DMA writes or being Read DMA write datas
Headspace.
RD Flag (Read DMA Flag) are defined：It can be seen from SSD font end protocols, SSD transmission data are certainly
Sector aligns, and each sector size is 512B.Therefore each sector space is in RD in specifying Buffer in this programme
There is exclusive 1bit information corresponding in Flag.The RD Flag in certain sector space are that 0 expression Read DMA are writeable to be somebody's turn to do
Sector spaces, if its RD Flash puts 1 expression, the sector spaces are expired by Write DMA writes or are expired by Read DMA writes.
With reference to WD Flag, RD Flag, hardware need to realize following DMA transfer control rule：
If 1. Write DMA need to find that its corresponding WD flag is 0 when writing certain sector space, write data into immediately
The space, after writing full 512B, puts 1. by WD flag and RD flag corresponding with the space immediately
If 2. Write DMA need to find that its corresponding WD flag is 1 when writing certain sector space, pause Write DMA's
Data transfer, until after the WD flag in the space are by other modules clear 0,1. Write DMA continue data transfer by rule again.
If 3. Read DMA need to write the access of certain sector space according to when find that its corresponding RD flag value is all 0, stand
The space is write data into, after writing full 512B, RD flag corresponding with the space 1. is put immediately
If 4. Read DMA need to write the access of certain sector space according to when find that its corresponding RD flag value is all 1, suspend
The data transfer of Read DMA, until the RD flag in the space by clear 0, the Read DMA of other modules be further continued for by rule 3. after
Continuous data transfer..
If 5. Read DMA need from certain sector space access according to when find its corresponding RD flag value all be 1, take this away
Data in space, after taking 512B away, by the space corresponding WD flag and RD flag all clear 0.
If 6. Read DMA need from certain sector space access according to when find its corresponding RD flag value be 0, suspend Read
The data transfer of DMA, until after the RD flag in the space put 1 by other hardware modules, 5. Read DMA continue number by rule again
According to transmission.
7. Write DMA/Read DMA possess Buffer winding read-write capabilitys, i.e., when read-write is to Buffer right margins, under
The left margin original position that read and write position automatic jumps to Buffer is written and read.
8. Write DMA when certain section of space is write, it is necessary to will be needed in initial unit read filling part WD flag put 1,
Without operation RD flag（Such as the corresponding WD flag of part2 data in Fig. 2）.
After possessing above-mentioned definition and rule, to complete identical work, it is assumed that starting WD flag, RD flag values is all
0.This programme realizes that step is as follows：
(1) write pointer is moved to next unit by Write DMA（If more than buffer borders, using rule 7.）, will rise
Beginning unit needs the WD flag in the space for reading filling (part2) to put 1（Rule is 8.）, while starting part1 data transfers（Transmission
During using rule 1. with rule 2.）, and report CPU to transmit address and length,
(2) CPU calculates the transmission initial address and length of part2, part3 according to transmission address and length, calculates part1+
The transmission initial address and data length of part2+part3, issue to Read DMA and write part2 request of data, write part3 successively
The request of data, reading part1+part2+part3 request of data.These requests are cached in Read DMA hits FIFO, by suitable
Sequence is performed
(3) 4. 3. READ DMA complete to write part1, part2 data according to rule with rule.Read DMA according to rule 5. and
6. rule completes to read part1+part2+part3 digital independents.Obviously when Read DMA complete part1+part2+part3 data
After transmission, its WD flag, RD flag are asked 0, i.e., this section caching is automatically released.
Knowable to aforesaid operations flow, entirely read filling process, CPU has been only involved in a step, and other processes are all by patrolling
The release of the application of buffer, data syn-chronization, buffer volume is automatically performed according to Data Transmission Controlling rule, is greatly saved
The consumption of CPU time resource, improves the ability that CPU processes other affairs；In addition, in the method, Read DMA are once completed
Part2, part3 data are write, now the RD flag set where part2, part3, even if part1 data do not prepare
It is good, but Read DMA are still immediately performed reading part1+part2+part3 operations, when so greatly reducing Read DMA and waiting
Between, efficiency of transmission between effectively lifting DMA.
Specifically, the principle of the invention is as follows：
1st, the memory cell of specified size is arranged（Such as 512B sizes）With WD Flag spaces, RD flag, Buffer deposits by multiple
Storage unit is constituted, and each memory cell has exclusive 1bit or many bit information corresponding in WD Flag, RD flag.
If the RD Flag of certain memory cell are state 0, represent that the memory cell is not write full；If the RD flag of certain memory cell are state
1, represent that the memory cell data has expired.If the WD Flag of memory cell are state 0, list item memory cell Write DMA can
Write, if the WD Flag of memory cell are state 1, memory cell Write DMA are not writeable.
2nd, on 1 basis, when Write DMA need to write certain memory cell in buffer, if its WD Flag is state
0, then the writeable memory cell of Write DMA, after memory cell is write completely, puts 1 by its WD flag and RD flag immediately；If its WD
Flag is state 1, then the not writeable memory cell of Write DMA, and the write operation of Write DMA is hung up, until WD Flag
State 0 is transformed to, Write DMA can be activated and continued to write.
3rd, on 3 bases, when Read DMA need to write certain memory cell in buffer, if its RD Flag is state 0,
Then the writeable memory cell of Read DMA, after memory cell is write completely, puts 1 by its RD flag immediately；If its RD flag is 1,
The not writeable memory cell of Read DMA, and Read DMA write operations are hung up, until RD flag are transformed to state 0, can swash
Read DMA living continue to write.
4th, on 1 basis, when Read DMA need to read certain memory cell in buffer, if its RD Flag is state
1, then readable memory cell of Read DMA, after having read memory cell, immediately by its WD Flag and RD flag SM set mode
0；If its RD Flag is state 0, the unreadable memory cell of Read DMA, and the read operation of Read DMA is hung up, directly
State 1 is transformed to RD Flag, Read DMA can be activated and continued to read.
5th, on the basis of 2 and 3, when terminal of the Write DMA/Read DMA writes beyond Buffer, then Write
The original position that DMA/Read DMA write pointers jump to Buffer continues to start to write data.
6th, on 4 basis, when Read DMA read beyond the terminal of Buffer, then Read DMA read pointers are jumped to
The original position of Buffer continues to start to read data.
, 4 basis on, Write DMA can be automatically performed the distribution in data stored target space, and need not be concerned about mesh
Whether mark space exceeds buffer sizes, and whether object space is taken by other transmission, because these all will be by WD Flag certainly
Dynamic control.And need the WD flag for reading filling part to put 1 initial unit, and it is not required to operation RD flag.
Claims (9)
1. a kind of SSD master controls Buffer, including multiple memory cell；Characterized in that, also including WD Flag spaces and RD
Flag spaces, and each memory cell has exclusive Lbit information to describe the writeable of the memory cell in WD Flag spaces
Enter state, each memory cell has what exclusive Lbit information described the memory cell to can read shape in RD Flag spaces
State；If the exclusive Lbit information in the corresponding WD flag spaces of certain memory cell is state 0, then it represents that writeable these of Write DMA is deposited
Storage unit；If the corresponding WD flag of the memory cell be state 1, then it represents that the memory cell expired by Write DMA writes or
It is Read DMA write data headspaces；If the exclusive Lbit information in the corresponding RD Flag spaces of certain memory cell is state 0,
Read writeable memory cell of DMA is then represented, if the exclusive Lbit information in the corresponding RD Flash spaces of the memory cell is shape
State 1, then it represents that the memory cell is expired by Write DMA writes or expired by Read DMA writes.
2. Buffer according to claim 1, it is characterised in that L>=1.
3. Buffer according to claim 1, it is characterised in that the memory cell size is 512B.
4. a kind of SSD master controls, including CPU, Write DMA and Read DMA；Characterized in that, also include claims 1 to 3 it
Buffer described in one；The Write DMA report non-unit aligned portions, the i.e. data transfer address of part2 and length
To CPU；The CPU calculates the transmission initial address and length of part2, part3 according to transmission address and length, calculates part1
The transmission initial address and data length of+part2+part3, issue to Read DMA and write part2 request of data, write successively
The request of part3 data, reading part1+part2+part3 request of data；Wherein, part1 is non-unit to its part；part3
That is end unit needs to read filling part；READ DMA complete to write part1, part2 data, while completing to read part1+part2+
Part3 digital independents.
5. the method that data are transmitted control is write in the SSD master controls described in a kind of utilization claim 4 to SSD non-alignments, and it is special
Levy and be, comprise the following steps：
1) write pointer is moved to next unit by Write DMA, and initial unit is needed to read filling part, i.e. part2 correspondences
The exclusive Lbit information in WD flag spaces put 1, while starting part1 data transfers, and report CPU to transmit address and length；
2) CPU calculates the transmission initial address and length of part2, part3 according to transmission address and length, calculates part1+
The transmission initial address and data length of part2+part3, issue to Read DMA and write part2 request of data, write part3 successively
The request of data, reading part1+part2+part3 request of data；Wherein, part1 is non-unit to its part；Part3 is end
Unit needs to read filling part；
3) READ DMA complete to write part1, part2 data, and Read DMA complete to read part1+part2+part3 digital independents.
6. method according to claim 5, it is characterised in that step 1) in, if Write DMA move to down write pointer
During one unit, more than buffer borders, then when read-write is to Buffer right margins, read and write position is automatic jumped to next time
The left margin original position of Buffer is written and read.
7. method according to claim 6, it is characterised in that step 1) in, the rule for starting part1 data transfers is：
A) if Write DMA need to write certain memory cell, the exclusive Lbit in the corresponding WD flag spaces of the memory cell is found
Information is state 0, then write data into the space immediately, after writing the memory cell, immediately will WD corresponding with the memory cell
The exclusive Lbit information states in flag spaces and RD flag spaces put 1；
B) if Write DMA need to write certain memory cell, the exclusive Lbit in the corresponding WD flag spaces of the memory cell is found
Information is state 1, then suspend the data transfer of Write DMA, until the corresponding WD flag spaces of the memory cell are exclusive
After Lbit information is by other modules clear 0, Write DMA press rule A again) continue data transfer.
8. method according to claim 7, it is characterised in that step 3) in, READ DMA complete to write part1, part2 number
It is following regular according to adapting to：
I) if Read DMA need to write certain memory cell, access according to when find that the corresponding RD flag spaces of the memory cell are exclusive
Lbit information be state 0, then write data into the memory cell immediately, after writing the full memory cell, immediately will this be deposited with this
The exclusive Lbit information states in the corresponding RD flag spaces of storage unit put 1；
II) if Read DMA need to write certain memory cell, access according to when find that the corresponding RD flag spaces of the memory cell are exclusive
Lbit information be state 1, then suspend the data transfer of Read DMA, until the RD flag spaces of the memory cell are by other
Clear 0, the Read DMA of module are further continued for by regular I) continue data transfer.
9. method according to claim 8, it is characterised in that step 6) in, Read DMA complete to read part1+part2+
Part3 digital independents adapt to following rule：
If i) Read DMA need from certain memory cell access according to when, it is found that the corresponding RD flag spaces of the memory cell are exclusive
Lbit information be state 1, then take the data in the memory cell away, when the memory cell data by all taken away after, will
The corresponding WD flag spaces of the memory cell and RD flag spaces all clear 0；
Ii) if Read DMA need from certain memory cell access according to when, it is found that the corresponding RD flag spaces of the memory cell are exclusive
Lbit information be state 0, then suspend the data transfer of Read DMA, until the RD flag spaces of the memory cell are by other
After module puts 1, Read DMA i) continue data transfer by rule again.
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