TW202046112A - Memory controller, memory controlling method, and computer system - Google Patents

Abstract

A memory controller includes an interface circuit and a processor. The interface circuit is configured to perform data communicate with a host device. When the processor finishes N commands transmitted from the host device, the memory controller informs the host device to release memory addresses corresponding to the N commands, wherein N is a positive integer. The processer compares a data transmitting speed of the interface circuit with a predetermined value. If the data transmitting speed is lower than the predetermined value, the processor adjusts the value of N according to the comparison result. The memory controller adjusts the value of N to match the masters having different configurations such that the transmission speed of the interface circuit is optimized.

Description

Memory controller, memory control method, and computer system

This disclosure relates to a memory controller, in particular to a memory controller that can improve data transmission efficiency, its control method, and a computer system.

Commercially available electronic devices can access data using various interface circuits (for example: ATA, PCI-e, USB) and storage devices (for example, solid state drives). Some interface circuits (such as Serial Advanced Technology Attachment (SATA)) interface can support Native Command Queuing (NCQ) technology to improve interface transmission efficiency. NCQ technology allows multiple commands to be stored in the queue Columns are executed in succession or at the same time, which is different from the old sorting technology, which requires waiting for the execution of the previous command before receiving the next command.

Electronic equipment manufacturers on the market have introduced many models of products, such as personal computers, servers, notebooks, etc. These products play the role of the master in data reading and writing operations. However, there are many consoles with different configurations (for example, different operating systems or different hardware architectures) on the market. If the device can only respond to a host with a different configuration in the same operating mode, not only may not be able to increase the overall transmission speed, but it may also reduce the work efficiency of both parties.

The present disclosure provides a memory controller, which includes an interface circuit and a processor. The interface circuit is used for data communication with the host. When the processor finishes executing N commands from the host, the memory controller informs the host to release the memory address corresponding to the N commands, and N is a positive integer. The processor compares the data transmission rate of the interface circuit with a preset value to generate a comparison result, and adjusts the value of N according to the comparison result.

The present disclosure also provides a control method, which is applied to a memory controller including an interface circuit and a processor. The foregoing control method includes the following processes: the interface circuit is used to receive N commands from the host; when the processor finishes executing the N commands, the processor is used to notify the host to release the memory address corresponding to the foregoing N commands, and N It is a positive integer; the processor compares the data transmission rate of the interface circuit with a preset value to generate a comparison result, and adjusts the value of N according to the comparison result.

The present disclosure also provides a computer system, which includes a host, a memory controller, and a memory module. The memory controller includes an interface circuit and a processor. The interface circuit is used for data communication with the host. When the processor finishes executing N commands from the host, the memory controller informs the host to release the memory address corresponding to the aforementioned N commands, and N is a positive integer. The memory module is coupled to the memory controller. The processor compares the data transmission rate of the interface circuit with a preset value to generate a comparison result, and adjusts the value of N according to the comparison result.

The aforementioned memory controller, its control method, and computer system can improve data transmission efficiency.

100‧‧‧Computer system

110‧‧‧Host

112‧‧‧First processor

114‧‧‧The first direct memory access (DMA) circuit

116‧‧‧First memory

118a‧‧‧The first interface circuit

118b‧‧‧The first interface circuit

120‧‧‧Memory Controller

122‧‧‧Second processor

124‧‧‧Second direct memory access (DMA) circuit

126‧‧‧Second memory

128‧‧‧Second interface circuit

Fc‧‧‧Control circuit

130‧‧‧Storage device

140‧‧‧Memory Module

2102~2110‧‧‧Process

2202~2210‧‧‧Process

230, 240, 250‧‧‧process

CMD1, CMD2, CMD[1]~CMD[2N], CMD[N+M]‧‧‧Command

TSa~TSd‧‧‧Transmission stage

TS[1]~TS[4N], TS[2N+2M]‧‧‧Transmission phase

310‧‧‧ Gear Head

320‧‧‧Field

5102~5108‧‧‧Process

5202~5208‧‧‧Process

530~570‧‧‧Process

FIG. 1 is a simplified functional block diagram of a computer system according to an embodiment of the disclosure.

FIG. 2 is a flowchart of a memory control method according to an embodiment of the disclosure.

FIG. 3 is a simplified schematic diagram of the bit FIS of the transmission setting device according to an embodiment of the present disclosure.

Figures 4A and 4B are simplified operational schematic diagrams of the FIS transmission mode of adjusting the setting device bit when the computer system executes the memory control method of Figure 2.

FIG. 5 is a flowchart of a memory control method according to another embodiment of the present disclosure.

FIGS. 6A and 6B are simplified operational schematic diagrams of adjusting the order of completion of multiple read commands when the computer system executes the memory control method of FIG. 5.

The embodiments of the present disclosure will be described below in conjunction with related drawings. In the drawings, the same reference numerals indicate the same or similar elements or method flows.

FIG. 1 is a simplified functional block diagram of the computer system 100 according to an embodiment of the present disclosure. The computer system 100 includes a host 110, a memory controller 120, a storage device 130, and a memory module 140. The host 110 and the storage device 130 may be partial circuits in a certain device. For example, the host 110 and the storage device 130 may be a motherboard and a hard disk in a personal computer, respectively. The memory controller 120 and the memory module 140 may be partial circuits in another device. For example, the memory controller 120 and the memory module 140 may be a solid state drive controller and a NAND flash memory in a solid state drive, respectively. In order to make the drawing concise and easy to explain, other components and connection relationships in the computer system 100 are not shown in the first figure.

The host 110 includes a first processor 112, a first direct memory access (DMA) circuit 114, a first memory 116, a first interface circuit 118a, and a first interface circuit 118b. The first interface circuit 118a is used for data communication with the memory controller 120. The first processor 112 is used to control two-way data transmission between the storage device 130 and the first memory 116. The first DMA circuit 114 is used to perform bidirectional data transmission between the first memory 116 and the memory controller 120.

The memory controller 120 includes a second processor 122, a second direct memory access (DMA) circuit 124, a second memory 126, a second interface circuit 128, and a control circuit Fc. The second interface circuit 128 is used for data communication with the first interface circuit 118a. The second processor 122 is used for controlling the second DMA circuit 124 and the control circuit Fc according to the command of the main control terminal 110. The second DMA circuit 124 is used to perform bidirectional data transmission between the second memory 126 and the host 110. The control circuit Fc is used to perform bidirectional data transmission between the second memory 126 and the memory module 140.

In practice, the first interface circuit 118a and the second interface circuit 128 may be SATA interfaces, but the present disclosure is not limited thereto. In an embodiment, the first interface circuit 118b may be a SATA interface or a PCI Express interface.

The transmission information between the host 110 and the memory controller 120 is packaged as a frame information structure (FIS). For example, the command transmitted by the host 110 to the memory controller 120 is the host to device (Host to Device) FIS, and the message confirmed by the memory controller 120 sent back to the host 110 is the device to host (Device to Device). to Host) FIS. When the memory controller 120 has executed N (one or more) commands, the memory controller 120 will send the Set Device Bits FIS to the host 110 to notify the host 110 to release the allocation Give the memory of the N commands Body address.

In the case where the capacity of the first memory 116 of the host 110 is small or the processing speed of the first processor 112 is slow, if the number of times the memory controller 120 sends the setting device bit FIS is too low (for example, in After executing too many commands before sending a setting device bit FIS), the host 110 will continue to (multiple times) send the hold primitive (Hold Primitive) due to insufficient memory space (because the first memory 116 has not been released). ) To the memory controller 120. On the other hand, when the host 110 has more memory space or the processing speed of the processor is faster, the fewer times the memory controller 120 sends the setting device bit FIS, the more the host 110 can be improved. Transmission efficiency with the memory controller 120.

FIG. 2 is a flowchart of a memory control method according to an embodiment of the disclosure. FIG. 3 is a simplified schematic diagram of the setting device bit FIS according to an embodiment of the present disclosure. The control method in FIG. 2 enables the memory controller 120 to adaptively adjust the transmission pattern of the device bit FIS according to the behavior of the host 110. Please refer to Figures 1~3, the memory controller 120 can execute the command CMD1 from the host 110. The content of the command CMD1 is to read data from the memory module 140, and the execution of the command CMD1 includes the transmission stage TSa~ TSb.

In the transmission phase TSa, the host 110 will use the host-to-device FIS to send the command CMD1 to the memory controller 120 (process 2102). Then, the memory controller 120 uses the device-to-host FIS to reply to the host 110 that the command CMD1 has been received (process 2104).

The control circuit Fc of the memory controller 120 moves the corresponding data from the memory module 140 to the second memory 126 to prepare for transmission (process 2106).

In the transmission phase TSb, the memory controller 120 sends the direct memory access setup (DMA Setup) FIS to the host 110 to notify the host 110 to start receiving Data (process 2108). Then, the memory controller 120 fills the data to be transmitted into the data FIS, and transmits the data FIS to the host 110 (process 2110).

The memory controller 120 can also execute the command CMD2 from the host 110. The content of the command CMD2 is to write data into the memory module 140, and the execution process of the command CMD2 includes transmission stages TSc~TSd.

In the transmission stage TSc, the host 110 will use the host-to-device FIS to send the command CMD2 to the memory controller 120 (process 2202). The second processor 122 uses the device-to-host FIS to reply to the host 110 that the command CMD2 has been received (process 2204).

In the transmission stage TSd, the memory controller 120 transmits the direct memory access setting FIS to the master 110 to notify the master 110 to prepare to start data transmission (process S2206). Then, the host 110 fills the data to be transmitted into the data FIS, and transmits the data FIS to the memory controller 120 (process S2208).

Then, the memory controller 120 writes the received data into the memory module 140 (process 2210).

In the process S230, the memory controller 120 transmits the setting device bit FIS to the host 110, so that the host 110 releases the memory addresses in the first memory 116 corresponding to the commands CMD1 and CMD2. Please refer to Figure 3, the transmission setting device bit FIS includes a file header 310 and a field 320, where the size of the field 320 is 32 bits. The file header 310 may include an error entry (Error Entry), an FIS type entry (FIS Type Entry), an interrupt entry (Interrupt Entry), and so on. Each bit in the field 320 corresponds to a command issued by the host 110. If the value of the bit is set to 1, it means that the host 110 needs to release the corresponding memory address, and if the value of the bit is set to 0, it means that the host 110 does not need to release the corresponding memory address.

In this embodiment, the memory controller 120 will send the device location The two bits (for example, the first bit and the second bit) in the element FIS corresponding to the commands CMD1 and CMD2 are set to 1, and the other bits (for example, the third bit to the thirty-second bit) Yuan) is set to 0.

In an embodiment, the type and content of FIS are determined by the first processor 116 and the second processor 122 in Figure 1, and the transmission of FIS is performed by the first DMA circuit 114 and the second DMA circuit 124. carried out. When the first DMA circuit 114 and the second DMA circuit 124 transfer data FIS to each other, the first processor 112 and the second processor 122 do not need to intervene. In this way, the computing efficiency of the first processor 112 and the second processor 122 can be improved.

For example, when the host 110 receives the direct memory access setting FIS in the process 2108, the first processor 112 may load the physical region description table (Physical Region Description Table) containing the address of the first memory 116 Enter the first DMA circuit 114 to specify the size of the data to be received and the address to be stored. Then, the first DMA circuit 114 receives the data FIS from the second DMA circuit 124 in the process 2110.

For another example, when the host 110 receives the direct memory access setting FIS in the process 2206, the first processor 112 loads the address of the data to be written in the first memory 116 into the first DMA circuit 114. Then, the first DMA circuit 114 uses the data FIS to transfer the data to be written to the second DMA circuit 124 in the process 2208.

In one embodiment, when the computer system 100 supports the native command ordering technology, the second processor 122 still stores multiple commands from the autonomous control terminal 110 in a queue and adjusts the execution order. In other words, the execution sequence of the transmission phase in FIG. 2 is only an example, and can be adjusted according to actual conditions. For example, in the case where the master 110 transmits multiple commands at a time, the transmission phases TSb and TSc can exchange the order with each other.

It can be seen from the above that before executing the process 230, the memory controller 120 has completed two commands CMD1 and CMD2 from the main control terminal 110, and each command is at least Contains two transmission stages. However, the number of completed commands in Figure 2 is only an exemplary embodiment. Each time the memory control method of Figure 2 is executed, the memory controller 120 can actually complete a total of N commands from the host 110 (that is, complete at least 2N transmission stages), and then proceed to the process 230, and N is a positive integer less than or equal to 32. In this case, in the process 230, the memory controller 120 sets the corresponding N bits in the field 320 to 1, and sets other bits to 0 to notify the host 110 to release the first memory The memory addresses in the body 116 respectively correspond to the N commands. In the subsequent paragraphs that continue to describe the memory control method of FIG. 2, it will be assumed that the memory controller 120 has completed N commands from the host 110 before executing the process 230.

In the process 240, the memory controller 120 calculates the transfer rate of the second interface circuit 128. Specifically, the second DMA circuit 124 notifies the second processor 122 at the start and end of each data transfer, for example, at the start and end of the process 2110 and the process 2208. Therefore, the memory controller 120 can calculate the total time that the second DMA circuit 124 is in a busy state when the N commands are executed. The memory controller 120 further calculates the transmission rate of the second interface circuit 128 based on the sum of the time and the sum of the FIS size of the data transmitted when the N commands are executed.

Then, in the process 250, the memory controller 120 compares the transmission rate of the second interface circuit 128 with a preset value. If the comparison result is that the transmission rate of the second interface circuit 128 is lower than the preset value, the memory controller 120 will adjust the number of commands completed before the setting device bit FIS (that is, before the process 230). The specific adjustment method will be further explained with Figure 4A and Figure 4B. Of course, if the comparison result is that the transmission rate of the second interface circuit 128 is higher than the preset value, the memory controller 120 can also increase the number of commands completed before transmitting the setting device bit FIS until the transmission speed is optimized. .

As shown in FIG. 4A, the memory controller 120 is preset to complete every N commands Command (for example, command CMD[1]~CMD[N] or CMD[N+1]~CMD[2N]) and then send it once to set the device bit FIS. That is, the memory controller 120 will transmit the setting device position once after completing at least 2N transmission stages (for example, transmission stage TS[1]~TS[2N] or TS[2N+1]~TS[4N]) Yuan FIS.

If the transmission rate of the second interface circuit 128 is judged to be lower than the preset value in the process 250 of FIG. 2, as shown in FIG. 4B, the memory controller 120 will switch to complete M commands (for example, command After CMD[N+1]~CMD[N+M]), send the setting device bit FIS once, where M is a positive integer not equal to N and M is less than or equal to 32. That is, the memory controller 120 will switch to transmit the set device bit FIS once after completing at least 2M transmission stages (for example, the transmission stages TS[2N+1]~TS[2N+2M]). At this time, when the process 230 in Figure 2 is executed again, the memory controller 120 will adjust the number of bits set to 1 in the device bit FIS from N to M to notify the device 110 to release the corresponding The memory address of the M commands (for example, the command CMD[N+1]~CMD[N+M]).

The computer system 100 can execute the memory control method of FIG. 2 many times, so that the memory controller 120 can adaptively optimize the data transmission efficiency according to the configuration of the host 110. The foregoing configuration refers to the processor architecture of the first processor 112 of the host 110, the north-south bridge chip, the memory size of the first memory 116, the advanced host controller interface architecture, A combination of operating system, driver software, or whether NCQ technology is activated or not. In an embodiment where the random access memory of the host 110 is small or the operation speed is slow, the computer system 100 can reduce the value of N (for example, adjust N from 16 to 7) to increase the host 110 The number of times the memory address is released, thereby reducing the number of times that the host 110 requests to suspend data transmission due to insufficient memory space due to the time to release the memory. In another embodiment where the random access memory of the host 110 is larger or the calculation speed is faster, the computer system 100 can increase the value of N (for example, change N from 16 Adjust to 30) to reduce the transmission time consumed by the memory controller 120 to transmit and set the device bit FIS, improve the data transmission efficiency between the host 110 and the memory controller 120, and improve the memory controller 120 computing performance.

In addition, after the memory controller 120 optimizes the value of N, and when the value of N is greater than or equal to 2, the memory controller 120 determines that the host supports native command sequencing technology. However, among the many masters that support native ordering technology, some masters have higher processing efficiency for the data returned in disorder, while others have higher processing efficiency for the data returned in sequence. Processing efficiency.

FIG. 5 is a flowchart of a memory control method according to another embodiment of the present disclosure. The memory control method of FIG. 5 enables the memory controller 120 to adaptively adjust the order of returning data according to the behavior of the host 110. In the embodiment of FIG. 5, the memory controller 120 executes the commands CMD1 and CMD2, and the contents of the commands CMD1 and CMD2 are read from the memory module 140. The execution process of command CMD1 includes transmission phases TSa and TSc, while the execution process of command CMD2 includes transmission phases TSb and TSd.

In the transmission stage TSa, the host 110 uses the host-to-device FIS to send the command CMD1 to the memory controller 120 (process 5102). The memory controller 120 uses the device-to-host FIS to reply to the host 110 that the command CMD1 has been received (process 5104). Then, in the transmission stage TSb, the host 110 will use the host-to-device FIS to send the command CMD2 to the memory controller 120 (process 5202). The memory controller 120 uses the device-to-host FIS to reply to the host 110 that the command CMD2 has been received (process 5204).

In this embodiment, due to factors such as data size or storage address, the memory controller 120 accesses the data corresponding to the command CMD2 from the memory module 140 faster, and accesses the data corresponding to the command CMD2 more slowly. CMD1 information. That is, the control circuit Fc will be The data corresponding to the command CMD2 is quickly moved from the memory module 140 to the second memory 126 to wait for transmission (process 530).

As mentioned above, the memory controller 120 can determine the order of execution of the multiple commands from the host 110, but not necessarily the order in which the commands are received. Therefore, the memory controller 120 then executes the transmission stage TSc to transmit the data corresponding to the command CMD2 to the host 110. In the transmission stage TSc, the process 5206 and the process 5208 are respectively similar to the process 2108 and the process 2110 in FIG. 2, the difference is that the data FIS corresponding to the command CMD2 is transmitted in the process 5208. For the sake of brevity, the rest of the process 5206 and process 5208 will not be repeated here.

Then, the control circuit Fc moves the data corresponding to the command CMD1 from the memory module 140 to the second memory 126 to wait for transmission (process 540). The memory controller 120 then executes the transmission stage TSd to transmit the data corresponding to the command CMD1 to the host 110. In the transmission stage TSd, the process 5106 and the process 5108 are similar to the process 2108 and the process 2110 in FIG. 2 respectively. The difference is that the data FIS corresponding to the command CMD1 is transmitted in the process 5108. For the sake of brevity, the rest of the process 5106 and process 5108 will not be repeated here.

In addition, the process 550 in FIG. 5 is similar to the process 230 in FIG.

It can be seen from the above that the memory controller 120 may not transmit corresponding data according to the order in which the commands CMD1 and CMD2 are received. The memory controller 120 can improve work efficiency by preferentially transmitting the first accessed data.

The two commands CMD1 and CMD2 in Fig. 5 are merely exemplary embodiments for convenience of description. In practice, each time the memory control method shown in Figure 5 is executed, the computer system 100 can complete a total of N commands before proceeding to the process 550, and N is less than or etc. A positive integer within 32. In the subsequent paragraphs that continue to describe the memory control method in FIG. 5, it will be assumed that the memory controller 120 has completed N commands from the main control terminal 110 before executing the process 550.

In the process 560, the memory controller 120 calculates the transmission rate of the second interface circuit 128 in a method similar to the process 240 in FIG. In the process 570, the memory controller 120 compares the transmission rate of the second interface circuit 128 with a preset value. If the transmission rate of the second interface circuit 128 is less than the preset value, and the aforementioned N commands include i read commands, the memory controller 120 will adjust the i data corresponding to the i read commands. Delivery order.

Specifically, the memory controller 120 adjusts the transfer sequence of the i data from the access sequence corresponding to the i data (that is, the sequence of being moved into the second memory 126) to correspond to The receiving sequence of the i read commands, where i is a positive integer less than or equal to N. For example, the memory controller 120 swaps the execution order of TSc and TSd in the transmission stages of FIG. 5 with each other. The detailed adjustment method will be further explained with Figure 6A and Figure 6B.

To illustrate, Fig. 6A and Fig. 6B only show the read commands CMD[1]~CMD[N] and the corresponding transmission stages TS[1]~TS[2N], and the write commands are omitted. As shown in FIG. 6A, the memory controller 120 presets to give priority to the data that is accessed first. That is, the order in which the memory controller 120 transmits the data FIS corresponds to the order in which the corresponding data is moved into the second memory 126 (for example, 3, 1, 2, ..., N).

If the transmission rate of the second interface circuit 128 is determined to be less than the preset value in the process 560, the memory controller 120 will switch the order of transmitting the data FIS to the order of receiving the corresponding read command (ie, 1,2,3,...,N).

In one embodiment, the FIS and data FIS are set due to direct memory access It is transmitted in the same transmission stage, so when the memory controller 120 switches the transmission sequence of the data FIS, it will also switch the transmission sequence of the direct memory access setting FIS accordingly. That is, the memory controller 120 switches the transmission sequence of the direct memory access setting FIS from the access sequence corresponding to the corresponding data to the receiving sequence corresponding to the corresponding read command.

In some embodiments, the non-volatile memory controller 120 is preset to transmit the corresponding data FIS and/or direct memory access setting FIS according to the receiving order of the read command. When the transmission rate of the second interface circuit 128 is less than the preset value, the non-volatile memory controller 120 switches the transmission sequence of the data FIS and/or the direct memory access setting FIS to correspond to the corresponding data access sequence .

In other embodiments, when the transmission rate of the second interface circuit 128 is higher than the preset value, the non-volatile memory controller 120 may not switch the data FIS and/or direct memory access to set the transmission sequence of the FIS.

Please note that the memory control methods in Figure 2 and Figure 5 can be combined with each other. The process 250 in FIG. 2 may include the operations in the process 570 in FIG. 5, and the process 570 in FIG. 5 may also include the operations in the process 250 in FIG. That is, in some embodiments, the memory control method can also adjust the transmission mode of the setting device bit FIS and the transmission sequence of the data FIS by the memory controller 120.

Certain words are used in the specification and the scope of the patent application to refer to specific elements. However, those with ordinary knowledge in the technical field should understand that the same element may be called by different terms. The specification and the scope of the patent application do not use the difference in names as a way of distinguishing elements, but the difference in function of the elements as the basis for distinguishing. The "including" mentioned in the specification and the scope of the patent application is an open term, so it should be interpreted as "including but not limited to". In addition, "coupling" here includes any direct and indirect connection means. Therefore, if the text describes that the first element is coupled to the second element, then It means that the first element can be directly connected to the second element through electrical connection, wireless transmission, optical transmission, or other signal connection methods, or indirectly electrically or signally connected to the second element through other elements or connection means.

The description method of "and/or" used herein includes any combination of one or more of the listed items. In addition, unless otherwise specified in the specification, any term in the singular case also includes the meaning of the plural case.

The above are only the preferred embodiments of the present disclosure, and all equal changes and modifications made in accordance with the requirements of the present disclosure should fall within the scope of the disclosure.

100‧‧‧Computer system

110‧‧‧Host

112‧‧‧First processor

114‧‧‧The first direct memory access (DMA) circuit

116‧‧‧First memory

118a‧‧‧The first interface circuit

118b‧‧‧The first interface circuit

120‧‧‧Memory Controller

122‧‧‧Second processor

124‧‧‧Second direct memory access (DMA) circuit

126‧‧‧Second memory

128‧‧‧Second interface circuit

Fc‧‧‧Control circuit

130‧‧‧Storage device

140‧‧‧Memory Module

Claims (10)

A memory controller includes: an interface circuit for communicating with a master control terminal; and a processor, wherein when the processor finishes executing N commands from the master control terminal, the memory controller Notify the host to release the memory address corresponding to the N commands, and N is a positive integer; wherein the processor compares a data transmission rate of the interface circuit with a preset value to generate a comparison result, wherein The processor adjusts the value of N according to the comparison result. The memory controller according to claim 1, wherein the memory controller sends a setting device frame information structure (FIS) to the host to notify the host to release the corresponding In the memory address of the N commands, the setting device bit FIS includes a first field, the first field includes a plurality of bits, and the plurality of bits respectively represent the N from the host One of the pen commands. The memory controller according to claim 2, wherein the memory controller switches between a first rule and a second rule according to the comparison result to determine how to transmit a plurality of commands corresponding to the N commands Read a plurality of data FIS of the command, wherein the first rule includes: the transmission sequence of the plurality of data FIS is corresponding to the memory controller accessing a plurality of data corresponding to the plurality of read commands from a memory module The order of the data; The second rule includes: the transmission sequence of the multiple data FIS corresponds to the sequence in which the memory controller receives the multiple read commands from the host. The memory controller according to claim 3, wherein the memory controller transmits a plurality of direct memory access settings FIS corresponding to the plurality of read commands to the host, and the first rule further Including: the transmission sequence of the multiple direct memory access setting FIS corresponds to one of the following sequences: the sequence of the memory controller accessing the multiple data, and the memory controller receives the data from the host The sequence of multiple read commands; wherein the second rule further includes: the transmission sequence of the multiple direct memory access setting FIS corresponds to the other of the following sequence: the sequence of the memory controller accessing the multiple data , And the sequence in which the memory controller receives the multiple read commands from the host. The memory controller according to claim 1, wherein the processor calculates a length of time used by the plurality of data FIS corresponding to the N commands, wherein the processor calculates the length of time and the plurality of data FIS To calculate the data transfer rate. The memory controller of claim 1, wherein the processor adjusts the value of N according to the comparison result, and when the value of N is greater than 1, the processor determines that the configuration of the host supports a Native Command Queuing (NCQ) technology. A control method applied to a memory controller, the memory The body controller includes an interface circuit and a processor, and the method includes: using the interface circuit to receive N commands from a host; when the processor finishes executing the N commands, using the processor to notify the host The terminal releases the memory address corresponding to the N commands, and N is a positive integer; uses the processor to compare a data transmission rate of the interface circuit with a preset value to generate a comparison result; and uses the processor Adjust the value of N according to the comparison result. The method according to claim 7, wherein the process of notifying the host to release the memory address corresponding to the N commands includes: using the processor to transmit a setting device bit FIS to the host, wherein the The setting device bit FIS includes a first field, the first field includes a plurality of bits, and the plurality of bits are respectively used to represent one of the N commands from the host. The method according to claim 8, further comprising: switching between a first rule and a second rule according to the comparison result to determine how to transmit a plurality of read commands corresponding to a plurality of the N commands Data FIS, wherein the first rule includes: the transmission sequence of the multiple data FIS corresponds to the sequence in which the memory controller accesses multiple data corresponding to the multiple read commands from a memory module; wherein The second rule includes: the transmission sequence of the multiple data FIS corresponds to the sequence in which the memory controller receives the multiple read commands from the host. A computer system including: A main control terminal; a memory controller including: an interface circuit for communicating with the main control terminal; a processor, wherein when the processor finishes executing N commands from the main control terminal, the memory The body controller notifies the host to release the memory address corresponding to the N commands, and N is a positive integer; and a memory module coupled to the memory controller; wherein, the processor uses the interface A data transmission rate of the circuit is compared with a preset value to generate a comparison result, and the processor adjusts the value of N according to the comparison result.

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