CN116756075A

CN116756075A - Data transmission method, device, storage medium and equipment

Info

Publication number: CN116756075A
Application number: CN202310755898.2A
Authority: CN
Inventors: 杨金金; 杜肖功; 徐骏; 张德礼; 汤斐挺; 孙泉
Original assignee: Beijing Hexinruitong Electric Power Technology Co ltd
Current assignee: Beijing Hexinruitong Electric Power Technology Co ltd
Priority date: 2023-06-25
Filing date: 2023-06-25
Publication date: 2023-09-15

Abstract

The application discloses a data transmission method, a data transmission device, a storage medium and data transmission equipment. Wherein the method comprises the following steps: receiving data to be transmitted in response to a data transmission signal, and determining a serial port corresponding to the data to be transmitted; determining a transmission buffer area corresponding to the serial port, and sending the data to be transmitted to the transmission buffer area; and reading the data to be transmitted in the transmission buffer area to finish data transmission. The application solves the technical problems that the number of serial ports of the central processing unit is limited and the requirement of multiple serial ports of the equipment cannot be met in the prior art.

Description

Data transmission method, device, storage medium and equipment

Technical Field

The present application relates to the field of computer software technologies, and in particular, to a data transmission method, apparatus, storage medium, and device.

Background

In a device requiring multiple serial ports for data transmission, the number of serial ports of a Central Processing Unit (CPU) is limited, which is insufficient to meet the transmission requirement of multiple serial ports of the data transmission device.

Particularly, in an asymmetric multi-processing (AMP) architecture system, multiple cores all need more serial resources to transmit external serial data, but the number of serial ports of the existing central processing unit cannot meet the transmission requirement of multiple serial ports.

No effective solution has been proposed to the problem.

Disclosure of Invention

The embodiment of the application provides a data transmission method, a device, a storage medium and equipment, which at least solve the technical problem that the number of serial ports of a central processing unit is limited and the requirement of multiple serial ports of the equipment cannot be met in the prior art.

According to an aspect of an embodiment of the present application, there is provided a data transmission method including: receiving data to be transmitted in response to a data transmission signal, and determining a serial port corresponding to the data to be transmitted; determining a transmission buffer area corresponding to the serial port, and sending data to be transmitted to the transmission buffer area; and reading the data to be transmitted in the transmission buffer area, and finishing data transmission.

Optionally, receiving data to be transmitted in response to a data transmission signal, and determining a serial port corresponding to the data to be transmitted, including: determining a signal type of the data transmission signal, wherein the signal type comprises: the data to be transmitted includes: data to be transmitted and data to be received; receiving data to be transmitted of an application core under the condition that the signal type is a data transmission type, and determining a serial port corresponding to the application core, wherein the application core is arranged in a central processing unit; and under the condition that the signal type is the data receiving type, determining the data state of the serial port, and receiving data to be received in the serial port based on the data state, wherein the data state is used for determining the serial port corresponding to the data to be received.

Optionally, when the data to be transmitted is data to be transmitted, determining a transmission buffer area corresponding to the serial port, and transmitting the data to be transmitted to the transmission buffer area, including: acquiring serial port resource configuration information, and determining a serial port corresponding to an application core based on the serial port resource configuration information; determining a transmission buffer area in a transmission buffer area corresponding to a serial port based on serial port resource configuration information; and sending the data to be sent to a sending buffer area.

Optionally, reading the data to be transmitted in the transmission buffer area to complete data transmission, including: determining a plurality of byte data of data to be transmitted; one byte data in the plurality of byte data is sent to the FPGA chip by adopting the CMD52 control instruction to finish one-time data sending operation, wherein the FPGA chip is used for sending the plurality of byte data to the serial port; repeating the data transmission operation a plurality of times until the transmission of the plurality of bytes of data is completed.

Optionally, reading data to be transmitted in the transmission buffer area to complete data transmission, and further including: determining a plurality of byte data of data to be transmitted; and simultaneously transmitting the plurality of byte data to the FPGA chip by adopting a CMD53 control instruction, wherein the FPGA chip is used for transmitting the plurality of byte data to the serial port.

Optionally, when the data to be transmitted is data to be received, determining a transmission buffer area corresponding to the serial port, and sending the data to be transmitted to the transmission buffer area, including: determining an application core corresponding to the serial port; and sending the data to be received to a receiving buffer area in the transmission buffer area corresponding to the application core.

Optionally, reading the data to be transmitted in the transmission buffer area to complete data transmission, including: and sending the data to be received in the receiving buffer area to the application core through the FPGA chip, wherein the FPGA chip is used for sending a plurality of byte data in the data to be received to the application core.

According to another aspect of the embodiment of the present application, there is also provided a data transmission apparatus, including: the receiving module is used for responding to the data transmission signal, receiving data to be transmitted and determining a serial port corresponding to the data to be transmitted; the transmitting module is used for determining a transmission buffer area corresponding to the serial port and transmitting data to be transmitted to the transmission buffer area; and the transmission module is used for reading the data to be transmitted in the transmission buffer area and finishing data transmission.

According to another aspect of the embodiments of the present application, there is also provided a nonvolatile storage medium storing a plurality of instructions adapted to be loaded by a processor and to perform the data transmission method of any one of the above.

According to another aspect of the embodiments of the present application, there is also provided an electronic device including a memory in which a computer program is stored, and a processor configured to run the computer program to perform the data transmission method of any one of the above.

In the embodiment of the application, the data to be transmitted is received by responding to the data transmission signal, and the serial port corresponding to the data to be transmitted is determined; determining a transmission buffer area corresponding to the serial port, and sending data to be transmitted to the transmission buffer area; the data to be transmitted in the transmission buffer area is read to complete data transmission, and the aim of expanding multiple serial ports by using a peripheral interface bus through an FPGA chip is fulfilled, so that the technical effect of expanding the data transmission serial ports of the multi-core central processor is realized, and the technical problem that the serial ports of the central processor are limited in number and cannot meet the requirements of multiple serial ports of equipment in the prior art is solved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:

fig. 1 is a flow chart of a data transmission method according to an embodiment of the present application;

FIG. 2 is a schematic diagram of an alternative multi-core CPU data transmission flow according to an embodiment of the present application;

FIG. 3 is a schematic diagram of an alternative serial port resource configuration information according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a data transmission device according to an embodiment of the present application.

Detailed Description

In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and the claims and drawings of the present application are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

For convenience of description, the following will describe some terms or terminology involved in the embodiments of the present application:

AMP (Asymmetric Multi-Processing Asymmetric multiprocessing): the multiple cores are relatively independent to run different tasks, and each core is isolated from the other cores, so that different operating systems can be run;

SDIO (Secure Digital Input and Output secure digital input output): secure digital input output, a type of peripheral interface defined on the SD standard.

Example 1

According to an embodiment of the present application, there is provided a method embodiment of data transmission, it being noted that the steps shown in the flowcharts of the figures may be performed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that herein.

Fig. 1 is a flowchart of a data transmission method according to an embodiment of the present application, as shown in fig. 1, the method includes the steps of:

step S102, receiving data to be transmitted in response to a data transmission signal, and determining a serial port corresponding to the data to be transmitted;

step S104, determining a transmission buffer area corresponding to the serial port, and sending data to be transmitted to the transmission buffer area;

step S106, reading the data to be transmitted in the transmission buffer area, and finishing data transmission.

In the embodiment of the present application, the execution body of the data transmission method provided in steps S102 to S106 is an FPGA chip in the multi-core central processing unit, and the FPGA chip is adopted to respond to the data transmission signal, receive the data to be transmitted, and determine the serial port corresponding to the data to be transmitted; determining a transmission buffer area corresponding to the serial port, and sending data to be transmitted to the transmission buffer area; and reading the data to be transmitted in the transmission buffer area, and finishing data transmission.

As an alternative embodiment, as shown in the data transmission flow diagram of the multi-core central processing unit in fig. 2, in the case that the signal type is the data transmission type, the data to be transmitted sent by a certain application core is forwarded to the management core by means of a shared memory; the management core receives the data to be sent, and compares serial port data to be sent (i.e. the data to be sent) of each application core with configuration information of serial port resource allocation to the application core through the FPGA chip, for example: comparing the specific application core with a pre-configured configuration information table after determining the specific application core, and determining a serial port corresponding to the application core, and a sending buffer area and a receiving buffer area corresponding to the serial port; based on the comparison result, adding the data to be transmitted into a transmission buffer zone of a corresponding serial port on the management core; the management core sends the data of the corresponding serial port of the sending buffer area to the FPGA chip; and finally, the FPGA chip sends out the data to be sent.

Optionally, under the condition that the signal type is the data receiving type, determining the data state of the serial port, receiving data to be received in the serial port based on the data state, determining a receiving buffer area corresponding to the serial port and a corresponding application core based on a pre-configured configuration information table, sending the data to be received to the receiving buffer area, and finally sending the data to be received to the application core by the FPGA chip.

It should be noted that the data status may be used to indicate whether there is data to be received in the serial port.

It should be further noted that, the serial port resource may be flexibly allocated to different application cores through software configuration, and an operating system or a bare core application program on the central processing unit uses the allocated serial port to perform serial port communication with an external device. The configuration of the serial port resource can be configured in a configuration file, can be configured in a software analysis configuration file, and can be preset in software.

According to the embodiment of the application, the peripheral interface bus is used for expanding the multi-channel serial ports through the FPGA chip, so that the expansion of the data transmission serial ports of the multi-core central processing unit is realized.

In an optional embodiment, when the data to be transmitted is data to be sent, determining a transmission buffer area corresponding to the serial port, and sending the data to be transmitted to the transmission buffer area, including: acquiring serial port resource configuration information, and determining a serial port corresponding to an application core based on the serial port resource configuration information; determining a transmission buffer area in a transmission buffer area corresponding to a serial port based on serial port resource configuration information; and sending the data to be sent to a sending buffer area.

As an alternative embodiment, as shown in the serial port resource configuration information schematic diagram shown in fig. 3, in a specific application, a configuration information table may be used to pre-configure or record a serial port resource configuration relationship, so as to record serial ports corresponding to each application core. After receiving the data to be sent, firstly determining an application core corresponding to the data to be sent, for example: determining which application core is used for transmitting data to be transmitted by a management core, and taking the application core which is used for transmitting the data to be transmitted as a target application core; and determining a serial port corresponding to the target application core through the serial port resource configuration information, for example: application core 1 corresponds to serial port 0 and serial port 1. After receiving the data to be sent, storing the data to be sent into a shared memory; after the serial port corresponding to the application core is determined, the data to be transmitted in the shared memory is transmitted to the transmission buffer.

Optionally, the Central Processing Unit (CPU) communicates with the FPGA chip through a peripheral interface bus (SDIO), and data interaction between the CPU and the FPGA chip is completed through a CMD52 control command or a CMD53 control command. The CMD52 is sent to the FPGA by the CPU, and the read/write data is transferred by CMD52 or Response (Response). CMD52 can only read or write one byte at a time, while CMD53 allows for reading and writing multiple bytes or multiple BLOCKs (BLOCKs) at a time.

Optionally, data transmission control is performed by CMD52 or CMD53, and parameters such as baud rate, parity, stop bit, etc. are configured. The data transmission control, configuration parameters and other data interactions customize a proprietary interaction protocol.

In an alternative embodiment, reading data to be transmitted in the transmission buffer area, and completing data transmission, including: determining a plurality of byte data of data to be transmitted; one byte data in the plurality of byte data is sent to the FPGA chip by adopting the CMD52 control instruction to finish one-time data sending operation, wherein the FPGA chip is used for sending the plurality of byte data to the serial port; repeating the data transmission operation a plurality of times until the transmission of the plurality of bytes of data is completed. The protocol for CMD52 to send data is shown in table 1:

TABLE 1

The serial configuration register definition is shown in table 2:

TABLE 2

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Undefined type

CHK.1

CHK.0

BR.3

BR.2

BR.1

BR.0

Wherein the parity CHK definition is as shown in table 3:

TABLE 3 Table 3

The baud rate BR definition is shown in table 4:

TABLE 4 Table 4

As an alternative embodiment, the serial port sends data through CMD52, and the data is transmitted to the FPGA through CMD52 in a circulating manner until the CPU sends all the data to be sent to the FPGA through CMD52, the FPGA stores the data of one byte received from CMD52 in the buffer memory, and the FPGA sequentially sends the buffered data out from the serial port. The operation of writing the CMD52 into the FPGA can be used to configure parameters of the serial port, such as baud rate, parity check, stop bit, etc., besides data transmission, and the address can be flexibly defined as required.

In an alternative embodiment, the method reads the data to be transmitted in the transmission buffer area to complete data transmission, and further includes: determining a plurality of byte data of data to be transmitted; and simultaneously transmitting the plurality of byte data to the FPGA chip by adopting a CMD53 control instruction, wherein the FPGA chip is used for transmitting the plurality of byte data to the serial port.

As an alternative embodiment, the serial port sends data through the CMD53, the CPU sends the serial port data to be sent to the FPGA chip through the CMD53 at one time, the FPGA stores the data received from the CMD53 in the buffer memory, and the FPGA sequentially sends the buffered data from the serial port.

The protocol for CMD53 to send data is shown in table 5:

TABLE 5

In an optional embodiment, when the data to be transmitted is data to be received, determining a transmission buffer area corresponding to the serial port, and sending the data to be transmitted to the transmission buffer area, including: determining an application core corresponding to the serial port; and sending the data to be received to a receiving buffer area in the transmission buffer area corresponding to the application core, and sending the data to be received in the receiving buffer area to the application core through the FPGA chip, wherein the FPGA chip is used for sending a plurality of byte data in the data to be received to the application core.

In the embodiment of the application, the serial port receives data and then transmits the data to the FPGA chip; the FPGA chip receives serial data into a receiving buffer of the serial port and sends an interrupt signal representing a received message to a CPU (central processing unit); after receiving the interrupt signal, the CPU management core goes to the FPGA chip to read the data state of which serial port and reads the data length of the corresponding serial port receiving buffer zone with the data to be received; the management core reads the data in the corresponding serial port receiving cache, forwards the serial port data to the corresponding application core in a shared memory mode according to the configuration information distributed to the CPU core by serial port resources, and repeats the steps until all the serial port data are read.

Optionally, when the serial port receives data, the FPGA receives the data from the serial port and stores the data in the cache, and when the CPU reads the data through the CMD52 command, one data is taken out of the cache and returned to the CPU. The read operation is mainly used for reading the data received by the serial port and the length of the received data, and the address can be flexibly defined according to the requirement.

The protocol for CMD52 to read serial data is shown in table 6:

TABLE 6

Optionally, the CMD53 can read and write a plurality of bytes each time, when the serial port receives data, the FPGA receives data from the serial port and stores the data in the cache, and when the CPU reads data through the CMD53 command, all the data is taken out of the cache at one time and returned to the CPU.

The protocol for CMD53 to read serial data is shown in table 7:

TABLE 7

As an optional embodiment, the FPGA and the CPU interact through the SDIO bus, so that the CPU expands a plurality of serial ports to access after passing through the FPGA, and the FPGA converts the SDIO data and the serial data and then carries out serial port transceiving operation. The serial port data is sent to the FPGA directly through the CPU through the SDI O bus, the FPGA converts the serial port data into serial port signals and sends the serial port signals out, and after the serial port data are received into the FPGA for buffering, the serial port data trigger interrupt notification CPU reads the serial port data from the FPGA.

Optionally, the same interrupt signal (data receiving type signal) is used by multiple serial ports, which serial port receives data can be further determined in the interrupt signal, and then the data in the serial port cache is read through the SDIO bus, so that interrupt resources of the CPU are saved.

Through the steps, the CPU can be informed by using an interrupt mode when receiving the serial data, compared with a timing refreshing mode, the serial data can be received more quickly, and the instantaneity is improved; compared with a timing refreshing mode, the method can save CPU resources, particularly does not need to frequently trigger reading operation under the condition of smaller data quantity, saves the CPU resources and improves the CPU performance.

Example 2

According to an embodiment of the present application, there is further provided an embodiment of an apparatus for implementing a data transmission method, and fig. 4 is a schematic structural diagram of a data transmission apparatus according to an embodiment of the present application, as shown in fig. 4, where the apparatus includes: a receiving module 40, a transmitting module 42 and a transmitting module 44, wherein:

a receiving module 40, configured to receive data to be transmitted in response to a data transmission signal, and determine a serial port corresponding to the data to be transmitted;

the sending module 42 is configured to determine a transmission buffer area corresponding to the serial port, and send data to be transmitted to the transmission buffer area;

the transmission module 44 is configured to read the data to be transmitted in the transmission buffer area, and complete data transmission.

Here, the receiving module 40, the transmitting module 42, and the transmitting module 44 correspond to steps S102 to S106 in embodiment 1, and the three modules are the same as the examples and application scenarios implemented by the corresponding steps, but are not limited to those disclosed in embodiment 1.

It should be noted that, the preferred implementation manner of this embodiment may be referred to the related description in embodiment 1, and will not be repeated here.

According to an embodiment of the present application, there is also provided an embodiment of a computer-readable storage medium. Alternatively, in the present embodiment, a computer-readable storage medium may be used to store program code executed by the data transmission method provided in embodiment 1.

Alternatively, in this embodiment, the computer readable storage medium may be located in any one of the group of computer terminals in the computer network or in any one of the group of mobile terminals.

Optionally, in the present embodiment, the computer readable storage medium is configured to store program code for performing the steps of: receiving data to be transmitted in response to a data transmission signal, and determining a serial port corresponding to the data to be transmitted; determining a transmission buffer area corresponding to the serial port, and sending data to be transmitted to the transmission buffer area; and reading the data to be transmitted in the transmission buffer area, and finishing data transmission.

Optionally, the computer readable storage medium is arranged to store program code for performing the steps of: determining a signal type of the data transmission signal, wherein the signal type comprises: the data to be transmitted includes: data to be transmitted and data to be received; receiving data to be transmitted of an application core under the condition that the signal type is a data transmission type, and determining a serial port corresponding to the application core, wherein the application core is arranged in a central processing unit; and under the condition that the signal type is the data receiving type, determining the data state of the serial port, and receiving data to be received in the serial port based on the data state, wherein the data state is used for determining the serial port corresponding to the data to be received.

Optionally, the computer readable storage medium is arranged to store program code for performing the steps of: acquiring serial port resource configuration information, and determining a serial port corresponding to an application core based on the serial port resource configuration information; determining a transmission buffer area in a transmission buffer area corresponding to a serial port based on serial port resource configuration information; and sending the data to be sent to a sending buffer area.

Optionally, the computer readable storage medium is arranged to store program code for performing the steps of: determining a plurality of byte data of data to be transmitted; one byte data in the plurality of byte data is sent to the FPGA chip by adopting the CMD52 control instruction to finish one-time data sending operation, wherein the FPGA chip is used for sending the plurality of byte data to the serial port; repeating the data transmission operation a plurality of times until the transmission of the plurality of bytes of data is completed.

Optionally, the computer readable storage medium is arranged to store program code for performing the steps of: determining a plurality of byte data of data to be transmitted; and simultaneously transmitting the plurality of byte data to the FPGA chip by adopting a CMD53 control instruction, wherein the FPGA chip is used for transmitting the plurality of byte data to the serial port.

Optionally, the computer readable storage medium is arranged to store program code for performing the steps of: determining an application core corresponding to the serial port; and sending the data to be received to a receiving buffer area in the transmission buffer area corresponding to the application core.

Optionally, the computer readable storage medium is arranged to store program code for performing the steps of: and sending the data to be received in the receiving buffer area to the application core through the FPGA chip, wherein the FPGA chip is used for sending a plurality of byte data in the data to be received to the application core.

According to an embodiment of the present application, there is also provided an embodiment of a processor. Alternatively, in the present embodiment, a computer-readable storage medium may be used to store program code executed by the data transmission method provided in embodiment 1.

The embodiment of the application provides an electronic device, which comprises a processor, a memory and a program stored on the memory and capable of running on the processor, wherein the processor realizes the following steps when executing the program: receiving data to be transmitted in response to a data transmission signal, and determining a serial port corresponding to the data to be transmitted; determining a transmission buffer area corresponding to the serial port, and sending data to be transmitted to the transmission buffer area; and reading the data to be transmitted in the transmission buffer area, and finishing data transmission.

The application also provides a computer program product adapted to perform, when executed on a data processing device, a program initialized with the method steps of: receiving data to be transmitted in response to a data transmission signal, and determining a serial port corresponding to the data to be transmitted; determining a transmission buffer area corresponding to the serial port, and sending data to be transmitted to the transmission buffer area; and reading the data to be transmitted in the transmission buffer area, and finishing data transmission.

The foregoing embodiment numbers of the present application are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.

In the foregoing embodiments of the present application, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.

In the several embodiments provided in the present application, it should be understood that the disclosed technology may be implemented in other manners. The above-described embodiments of the apparatus are merely exemplary, and the division of the units, for example, may be a logic function division, and may be implemented in another manner, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interfaces, units or modules, or may be in electrical or other forms.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium, including instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a Read-only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing is merely a preferred embodiment of the present application and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present application, which are intended to be comprehended within the scope of the present application.

Claims

1. A data transmission method, comprising:

receiving data to be transmitted in response to a data transmission signal, and determining a serial port corresponding to the data to be transmitted;

determining a transmission buffer area corresponding to the serial port, and sending the data to be transmitted to the transmission buffer area;

and reading the data to be transmitted in the transmission buffer area, and finishing data transmission.

2. The method of claim 1, wherein receiving data to be transmitted in response to a data transmission signal and determining a serial port corresponding to the data to be transmitted comprises:

determining a signal type of the data transmission signal, wherein the signal type comprises: a data transmission type and a data reception type, wherein the data to be transmitted comprises: data to be transmitted and data to be received;

receiving data to be transmitted of an application core and determining a serial port corresponding to the application core under the condition that the signal type is the data transmission type, wherein the application core is arranged in a central processing unit;

and under the condition that the signal type is the data receiving type, determining the data state of the serial port, and receiving the data to be received in the serial port based on the data state, wherein the data state is used for determining the serial port corresponding to the data to be received.

3. The method of claim 2, wherein, in the case that the data to be transmitted is the data to be sent, the determining the transmission buffer corresponding to the serial port and sending the data to be transmitted to the transmission buffer includes:

acquiring serial port resource configuration information, and determining the serial port corresponding to the application core based on the serial port resource configuration information;

determining a transmission buffer area in the transmission buffer area corresponding to the serial port based on the serial port resource configuration information;

and sending the data to be sent to the sending buffer area.

4. A method according to claim 3, wherein said reading the data to be transmitted in the transmission buffer to complete data transmission comprises:

determining a plurality of byte data of the data to be transmitted;

one byte data in the plurality of byte data is sent to an FPGA chip by adopting a CMD52 control instruction to complete one-time data sending operation, wherein the FPGA chip is used for sending the plurality of byte data to the serial port;

repeating the data transmission operation a plurality of times until the transmission of the plurality of bytes of data is completed.

5. The method of claim 3, wherein the reading the data to be transmitted in the transmission buffer completes data transmission, further comprising:

determining a plurality of byte data of the data to be transmitted;

and simultaneously transmitting the plurality of byte data to an FPGA chip by adopting a CMD53 control instruction, wherein the FPGA chip is used for transmitting the plurality of byte data to the serial port.

6. The method of claim 2, wherein, in the case that the data to be transmitted is the data to be received, the determining the transmission buffer corresponding to the serial port and sending the data to be transmitted to the transmission buffer includes:

determining the application core corresponding to the serial port;

and sending the data to be received to a receiving buffer area in the transmission buffer area corresponding to the application core.

7. The method of claim 6, wherein the reading the data to be transmitted in the transmission buffer to complete data transmission comprises:

and sending the data to be received in the receiving buffer area to the application core through an FPGA chip, wherein the FPGA chip is used for sending a plurality of byte data in the data to be received to the application core.

8. A data transmission apparatus, comprising:

the receiving module is used for responding to a data transmission signal, receiving data to be transmitted and determining a serial port corresponding to the data to be transmitted;

the sending module is used for determining a transmission buffer area corresponding to the serial port and sending the data to be transmitted to the transmission buffer area;

and the transmission module is used for reading the data to be transmitted in the transmission buffer area and finishing data transmission.

9. A non-volatile storage medium storing a plurality of instructions adapted to be loaded by a processor and to perform the data transmission method of any one of claims 1 to 7.

10. An electronic device comprising a memory and a processor, characterized in that the memory has stored therein a computer program, the processor being arranged to run the computer program to perform the data transmission method of any of claims 1 to 7.