CN116483259A

CN116483259A - Data processing method and related device

Info

Publication number: CN116483259A
Application number: CN202310107831.8A
Authority: CN
Inventors: 苏一萌; 王运富
Original assignee: XFusion Digital Technologies Co Ltd
Current assignee: XFusion Digital Technologies Co Ltd
Priority date: 2023-02-13
Filing date: 2023-02-13
Publication date: 2023-07-25

Abstract

The application discloses a data processing method and a related device, which are used for a data transmission scene. The method comprises the following steps: the controller reads a data transfer request descriptor generated by the processor, the data transfer request descriptor being generated based on a data transfer request for requesting transfer of the target data. The controller reads target data from a first memory based on the data transmission request descriptor, the first memory stores the target data, and the first memory is a memory corresponding to the controller. The controller then writes the target data to the second memory based on the data transfer request descriptor. In the method, the data transmission is initiated by the controller connected with the memory, so that the data transmission path can be shortened, and the data transmission efficiency can be improved.

Description

Data processing method and related device

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a data processing method and a related device.

Background

In modern computer systems, a central processing unit (Central Processing Unit, CPU), memory, input/Output (IO) constitute the basic computing architecture. At present, a high-speed peripheral component interconnect (peripheral component interconnect express, PCIe) bus is generally used for carrying out IO expansion, and various IO devices are connected. When the IO device performs data interaction with the CPU, a direct memory access (Direct Memory Access, DMA) controller of the IO device mainly sends a data loading (load) or storage (store) instruction to a memory managed by the CPU, so as to realize data handling between a storage space of the IO device and the memory managed by the CPU. However, the PCIe bus belongs to a non-cache-coherent bus, there is no negotiation about cache coherence, and the storage space of the IO device belongs to a device private memory, which is not directly exposed to the CPU for use, and is not globally and uniformly addressed, so that no universal use can be achieved.

In view of this, a computing quick connect (Compute Express Link, CXL) protocol may be employed, where the CPU is externally connected to a third Type (Type 3) memory expansion device via the CXL bus, the CXL protocol providing cache coherency guarantees between the CPU and the memory expansion device. The Type 3CXL memory expansion device provides general data storage resources for the CPU, is managed and used by the CPU, and supports data reading, writing and other operations. However, in this case, the CPU initiates the data operation request entirely, for example, the CPU needs to read data from the source address of the Type 3CXL memory expansion device and store the data in the register, and then write the data into the destination address of the Type 3CXL memory expansion device. Therefore, the whole data transmission process has a longer path, occupies the execution thread of the CPU for a long time, and has low transmission efficiency.

Disclosure of Invention

The application provides a data processing method and a related device, which can initiate data transmission by a controller corresponding to a memory, so that a data transmission path can be shortened, and data transmission efficiency is improved.

A first aspect of the present application provides a data processing method, the method comprising: the first controller reads a data transmission request descriptor generated by the processor, the data transmission request descriptor being generated based on a data transmission request for requesting transmission of target data; the first controller reads target data from a first memory based on the data transmission request descriptor, the first memory stores the target data, and the first memory is a memory corresponding to the controller; the first controller writes the target data to the second memory based on the data transfer request descriptor.

The controller may be integrated into the processor or may be external to the processor. And under the condition that the controller is integrated in the processor, the memory corresponding to the controller is a slave memory of the processor.

The processor enumerates the controller and the memory included in the system, and acquires information of the controller and information of the memory. The information of the controller comprises a system address of the controller and which memories the controller corresponds to, and the information of the memories comprises a system base address of the memories, address lengths of the memories and the like.

The processor generates a data transmission request descriptor based on the information of the controller, the information of the memory, and the information of the source system address, the destination system address, the data length, and the like of the target data, and the data transmission request descriptor is stored in a data transmission request queue. A data transfer request queue is generated by the processor using the memory space in the slave memory that is address-consecutive. The controller has stored therein a head address pointer of the data transmission queue. The controller accesses the data transmission queue at fixed time according to the head address pointer of the data transmission queue, checks whether the data transmission request descriptor relates to the controller, and if yes, reads the data transmission request descriptor. Or when the processor calculates that the target data relates to the first controller, the processor can also send a message to inform the first controller, the message comprises an address pointer of a corresponding data transmission request descriptor, and the controller accesses a data transmission queue and reads the data transmission request descriptor according to the address pointer. The method of reading the data transmission request descriptor by the controller is not particularly limited herein.

After the controller reads the data transmission request descriptor, the controller reads the target data from the first memory based on the data transmission request descriptor and writes the target data into the second memory. The first memory and the second memory may be the same memory or different memories, and when the first memory and the second memory are the same memory, data transmission between the first memory and the second memory is data handling between different local addresses of the memories.

In the first aspect of the present application, after the first controller reads the data transmission request descriptor, the first controller reads the target data from the first memory and writes the target data into the second memory, only unidirectional transmission is required, so that data interaction is reduced, a data transmission path is shortened, and therefore transmission efficiency can be improved. In addition, under the condition that the first controller initiates data transmission, the processor is not required to issue instructions such as loading, reading and the like, the processor is not required to pass through a computing core of the processor, the instruction set of the processor is not relied on, and the execution thread of the processor is released.

In a possible implementation manner of the first aspect, the data transmission request descriptor indicates one or more of the following information: the method comprises the steps of a source system address of target data, a destination system address of the target data, a data length of the target data, a completion queue address pointer, a completion queue depth and a completion status bit.

In this possible implementation manner, the content included in the data transmission request descriptor is limited, so that the feasibility of the scheme is improved.

In a possible implementation manner of the first aspect, the steps are as follows: the first controller reads the target data from the first memory based on the data transfer request descriptor, the method further comprising: the first controller describes Fu Panduan whether the first memory stores the target data based on the data transfer request.

The first memory is a memory for storing target data, which is calculated by the processor according to the information of the target data. However, the processor may calculate an error, so the controller makes a further determination as to whether the target data is stored in the first memory. If yes, initiating data transmission, reading target data from the first memory, otherwise, indicating that the processor calculates errors, wherein the first memory does not participate in the transmission of the target data, and the processor recalculates the memory in which the target data is located. Thereby improving the accuracy of the scheme.

In a possible implementation manner of the first aspect, the target data is stored in the first memory using an address interleaving technique.

Address interleaving refers to storing a segment of data in different memories, one memory being a memory channel. By using address interleaving, multiple pieces of data of the target data can be transmitted in parallel, so that the access bandwidth and the data transmission efficiency are improved.

In a possible implementation manner of the first aspect, the steps are as follows: the first controller writing the target data to the second memory based on the data transfer request descriptor, comprising: the first controller sends the target data to the second controller based on the data transmission request descriptor; and the second controller writes the target data into a second memory, wherein the second memory is a memory corresponding to the second controller.

The controller may be plural, where the first memory corresponds to the first controller and the second memory corresponds to the second controller, and the transmission process of the target data is that the first controller reads the target data from the first memory, then sends the target data to the second controller, and then the second controller writes the target data into the second memory.

In this possible implementation manner, it is described that the controller may include a plurality of controllers, and the controller corresponding to the first memory and the controller corresponding to the second memory may be different controllers, which expands the application scenario of the scheme.

A second aspect of the present application provides a data processing method, the method comprising: the processor determines a data transmission request, wherein the data transmission request is used for requesting transmission of target data; the processor generates a data transfer request descriptor based on the data transfer request, the data transfer request descriptor for provision to a storage device, the storage device including a controller and a first memory, the controller for reading target data from the first memory and writing the target data to the second memory based on the data transfer request descriptor.

In the second aspect of the present application, after the processor generates the data transmission request descriptor, the controller reads the target data from the first memory based on the data transmission request descriptor, and writes the target data into the second memory, only unidirectional transmission is required, so that data interaction is reduced, and a data transmission path is shortened, thereby improving transmission efficiency. In addition, under the condition that the controller initiates data transmission, the processor is not required to issue instructions such as loading, reading and the like, the processor is not required to pass through a computing core of the processor, the instruction set of the processor is not relied on, and the execution thread of the processor is released.

In a possible implementation manner of the second aspect, the data transmission request descriptor indicates one or more of the following information: the method comprises the steps of a source system address of target data, a destination system address of the target data, a data length of the target data, a completion queue address pointer, a completion queue depth and a completion status bit.

A third aspect of the present application provides a controller comprising a read unit and a write unit. A reading unit configured to read a data transmission request descriptor generated by the processor, the data transmission request descriptor being generated based on a data transmission request for requesting transmission of the target data; the reading unit is also used for reading target data from a first memory based on the data transmission request descriptor, the first memory stores the target data, and the first memory is a memory corresponding to the controller; and a writing unit for writing the target data into the second memory based on the data transfer request descriptor.

In a possible implementation manner of the third aspect, the data transmission request descriptor indicates one or more of the following information: the method comprises the steps of a source system address of target data, a destination system address of the target data, a data length of the target data, a completion queue address pointer, a completion queue depth and a completion status bit.

In a possible implementation manner of the third aspect, the controller further includes a determining unit, configured to describe, based on the data transmission request, whether the first memory stores the target data or not Fu Panduan.

In a possible implementation manner of the third aspect, the target data is stored in the first memory using an address interleaving technique.

In a possible implementation manner of the third aspect, the writing unit is specifically configured to send the target data to the second controller based on the data transmission request descriptor; and the second controller writes the target data into a second memory, wherein the second memory is a memory corresponding to the second controller.

A third aspect of the present application provides a controller for performing the method of the first aspect or any one of the possible implementation manners of the first aspect.

A fourth aspect of the present application provides a processor, comprising a determining unit and a generating unit. A determining unit configured to determine a data transmission request for requesting transmission of the target data; and a generation unit configured to generate a data transfer request descriptor based on the data transfer request, the data transfer request descriptor being configured to be provided to a storage device including a controller and a first memory, the controller being configured to read target data from the first memory and write the target data to the second memory based on the data transfer request descriptor.

In a possible implementation manner of the fourth aspect, the data transmission request descriptor indicates one or more of the following information: the method comprises the steps of a source system address of target data, a destination system address of the target data, a data length of the target data, a completion queue address pointer, a completion queue depth and a completion status bit.

A fourth aspect of the present application provides a processor for performing the method of the second aspect or any one of the possible implementations of the second aspect.

A fifth aspect of the present application provides a storage device, comprising a controller and a memory, the memory being configured to store instructions, the controller being configured to obtain the instructions stored in the memory, to perform the method described in the first aspect or any one of the possible implementations of the first aspect, or to perform the method described in the second aspect or any one of the possible implementations of the second aspect.

A sixth aspect of the present application provides a computing device, the computing device comprising a processor and a storage device, the storage device comprising a controller and a memory, characterized in that the storage device is configured to store instructions, the computing device being configured to obtain the instructions stored by the storage device, to perform the method described in the first aspect or any one of the possible implementations of the first aspect, or to perform the method described in the second aspect or any one of the possible implementations of the second aspect.

A seventh aspect of the present application provides a computer program product comprising instructions which, when run on a computer, cause a computing device to perform the method as described in the first aspect or any one of the possible implementations of the first aspect, or to perform the method as described in the second aspect or any one of the possible implementations of the second aspect.

An eighth aspect of the present application provides a chip system comprising at least one processor and a communication interface, the communication interface and the at least one processor being interconnected by a wire, the at least one processor being configured to execute a computer program or instructions to perform the method as described in the first aspect or any one of the possible implementations of the first aspect or to perform the method as described in the second aspect or any one of the possible implementations of the second aspect.

Drawings

FIG. 1 is a schematic diagram of a computer system according to an embodiment of the present application;

FIG. 2 is a schematic diagram of another architecture of a computer system according to an embodiment of the present application;

fig. 3 is a schematic diagram of an embodiment of a data transmission method according to an embodiment of the present application;

FIG. 4 is a flow chart of a processor generating a data transmission request descriptor according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a data transmission request queue and a completion queue according to an embodiment of the present application;

FIG. 6 is a schematic structural diagram of a controller according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a processor according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of a computing device according to an embodiment of the present application.

Detailed Description

The embodiment of the application provides a data processing method and a related device, which can initiate data transmission by a controller corresponding to a memory, so that a data transmission path can be shortened, and the data transmission efficiency is improved.

Embodiments of the present application will now be described with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some, but not all embodiments of the present application. As a person of ordinary skill in the art can know, with the development of technology and the appearance of new scenes, the technical solutions provided in the embodiments of the present application are applicable to similar technical problems.

In the embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of the following" or similar expressions thereof, means any combination of these items, including any combination of single or plural items. The terms first, second and the like in the description and in the claims of the present application and in the above-described figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and are merely illustrative of the manner in which the embodiments of the application described herein have been described for objects of the same nature. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Referring now to FIG. 1, therein is shown a schematic diagram of a computer system according to an embodiment of the present application.

As shown in fig. 1, the computer system includes a processor 101, a memory 102, and a memory 103. When data of the memory 102 is to be transferred to the memory 103, a load (load) instruction is sent to the memory 102 by the processor 101, the data is read from the memory 102, and then a store (store) instruction is sent to the memory 103, and the data is written into the memory 103, so that the data is carried from the memory 102 to the memory 103.

In addition, data handling between different addresses in the same memory also requires that a read/write operation be initiated by the processor 101, e.g., data needs to be transferred from an a address in the memory 102 to a B address in the memory 102, and then the processor reads the data from the a address and then writes the data to the B address.

It will be appreciated that fig. 1 is merely illustrative, and the number of processors and memories in the actual application may be more or less (but there is a minimum need for one processor and one memory), and the present invention is not limited thereto.

At present, when data interaction is performed between memories under CXL protocol scene, a processor is required to initiate read-write operation, the transmission path is long, the efficiency is low, and the execution thread of the processor is occupied for a long time.

In view of this, the embodiment of the application provides a data processing method, which can be applied to a CXL protocol scenario. Specifically, the controller connected with the memory executes the data transmission task, so that data carrying between the memories or between different addresses of the memories is realized, the data transmission path is shortened, the data transmission efficiency is improved, and the occupation of the execution thread of the processor is reduced.

Turning now to FIG. 2, a diagram illustrating an architecture of a computer system to which the above described data processing method is applied is shown. As shown in fig. 2, the computer system includes a processor, a storage device, and a forwarding module. The storage device comprises a controller and a memory, and the controller is connected with the memory. One controller may correspond to a plurality of memories (i.e., a plurality of memories are connected), and one memory corresponds to one controller. For example, the controller 203 corresponds to the memory 207 and the memory 208, and the controller 204 corresponds to the memory 209 and the memory 210.

The controller may be integrated into the processor or may be external to the processor. For example, the controller 205 is integrated into the processor, and the controller 204 is disposed outside the processor. In the case of the controller being integrated in the processor, the memory to which the controller is connected is a slave memory of the processor. For example, for the controller 205, its corresponding memory 211 is the slave memory of the processor. The controller executes a data transmission task according to the data transmission request determined by the processor, namely, reads target data from the first memory and writes the target data into the second memory.

The first memory and the second memory may be the same memory or different memories. When the first memory and the second memory are the same memory, the data transmission between the first memory and the second memory is the data handling between the local different addresses of the memories. When the first memory and the second memory are different memories, the controller corresponding to the first memory and the controller corresponding to the second memory may be the same or different. For example, when the first memory is the memory 207 and the second memory is the memory 208, the controllers corresponding to the first memory and the second memory are both the controller 203. When the first memory is the memory 207 and the second memory is the memory 209, the controllers corresponding to the first memory and the second memory are different, the first memory corresponds to the controller 203 and the second memory corresponds to the controller 204.

When the first memory and the second memory correspond to different controllers, the controller corresponding to the first memory needs to send the target data to the controller corresponding to the second memory through the forwarding module after the controller corresponding to the first memory reads the target data. For example, when the first memory is the memory 213 and the second memory is the memory 214, after the corresponding controller 201 reads the target data from the memory 213, the target data needs to be sent to the forwarding module 212, and then the forwarding module 212 sends the target data to the controller 202 corresponding to the memory 214. When the first memory and the second memory correspond to the same controller, the forwarding module is not needed to transmit data, for example, the first memory is the memory 207 and the second memory is the memory 208, and the data transmission process is that the corresponding controller 203 reads the target data from the memory 207 and then writes the target data into the memory 208.

The forwarding module is used for transmitting data among different devices of the computer system. The processor is externally provided with a forwarding module, and the processor also internally comprises the forwarding module. For devices that are not directly connected to the processor, the data is transmitted through a forwarding module external to the processor. The external forwarding module of the processor is a bus switching device, so that the interconnection of a plurality of devices can be realized, and the forwarding is performed when data are transmitted among different devices. For example, the forwarding module 212 connects the controller 201 and the controller 202, and connects the controller 201 and the controller 202 to the processor, and when the controller 201 needs to transmit data to the controller 202, or when the controller 201 needs to transmit data to the controller 203 connected to the processor, the forwarding module 210 receives the data sent by the controller 201, and forwards the data to the controller 202 or the forwarding module inside the processor. In the CXL protocol scenario, the forwarding module external to the processor may be a CXL Switch. For devices directly connected to the processor, such as the controller 203, or devices integrated in the processor, such as the controller 205, the data transfer needs to be performed by a forwarding module within the processor. Specifically, for the controller 203 connected to the processor, the forwarding module inside the processor is the root port of the processor when transmitting data. In the CXL protocol scenario, it may be a CXL ROOT PORT. When the external controller of the processor transmits data to the controller 205 integrated in the processor, the data needs to be transmitted through the root port of the processor and then through the forwarding module connected with the controller. If the data is transmitted between controllers integrated in the processor, for example, the controller 205 and the controller 206 transmit the data, the data transmission can be completed through the forwarding module connected between the controller 205 and the controller 206 without passing through the root port of the processor.

The data processing method provided in the embodiment of the present application is described below with reference to fig. 2 by taking the flowchart shown in fig. 3 as an example. Fig. 3 is an embodiment of a data processing method according to an embodiment of the present application, where the embodiment includes steps 301 to 307.

301. The processor determines a data transmission request.

When a computer system is running, data stored in memory often needs to be transferred between different addresses. The processor determines a data transfer request for requesting transfer of the target data. Specifically, the processor may generate the data transmission request according to the operation requirement of the system or the acquired instruction, or the processor may receive the generated data transmission request, for example, the acquired instruction includes the data transmission request. The data transmission request indicates information such as a source system address and a destination system address of the target data. The source system address of the target data is an address allocated by the processor to the target data in the computer system, and the first memory for storing the target data can be obtained according to the source system address of the target data. The target system address of the target data is the address of the target data which needs to be written in the computer system, and the second memory which needs to be written in the target data can be obtained according to the target system address of the target data. The data transmission request of the target data is a request for carrying the target data from the first memory to the second memory.

302. The processor generates a data transfer request descriptor based on the data transfer request.

The flow of the processor generating the data transfer request descriptor can be understood in conjunction with fig. 4. As shown in fig. 4, the flow includes steps S401 to S404.

S401, the processor acquires information of the storage device. The processor comprises an address preprocessing module, and the address preprocessing module is used for enumerating the storage device to acquire information of the controller and information of a memory (namely a connected memory) corresponding to the controller. The information of the controller comprises a system base address of the controller and corresponding memories of the controller. The information of the memories includes the topological relation among the memories, the system base address of the memories, the address length of the memories, etc. When address interleaving (address interleaving) is involved, the information of the memory also includes information of the number of address interleaving channels, address interleaving channel number, address interleaving granularity, and the like. Address interleaving refers to storing a segment of data in different memories, one memory being a memory channel. For example, the first 16 bytes are stored in the first memory, the next 16 bytes are stored in the second memory, and the next 16 bytes are stored in the third memory. Similarly, when all memories have stored the piece of data, the first memory is returned, and the next 16 bytes are stored by the first memory. By using address interleaving, parallel access to data can be realized, thereby improving the data transmission efficiency.

The address interleaving channel number refers to the number of memories available for the address interleaving memory scenario, the address interleaving channel number is the number of each memory, and the data are sequentially stored in the memories according to the size of the address interleaving channel number. The address interleaving granularity refers to the data size of each memory storing consecutive addresses, and as in the above example, the address interleaving granularity is 16 bytes, and furthermore, the address interleaving granularity may be 32 bytes, 64 bytes, etc., which is not particularly limited. However, the address interleaving granularity is typically a smaller amount of data to achieve faster processing of the data.

S402, the processor calculates a storage device for performing data transmission. The processor calculates a first memory in which the target data is located and a first controller connected with the first memory, and a second memory in which the target data is required to be written and a second controller connected with the second memory based on the acquired information of the storage device, the source system address, the destination system address and the data length of the target data. When address interleaving is involved, the target data is stored in a plurality of first memories and may need to be transferred to a plurality of second memories, and the processor needs to calculate each first memory and corresponding first controller in which the target data is located and each second memory and corresponding second controller in which the target data is written. It is understood that the number of second memories and the number of first memories may be the same or different. That is, even if the target data is stored in a plurality of first memories, the target data may be written to the same second memory.

S403, the processor generates a completion queue. When address interleaving is involved, the processor calculates a plurality of first memories in which target data is located. The processor generates a completion queue according to the number of the first memories, the completion queue including a plurality of data transfer completion descriptors, each data transfer completion descriptor corresponding to one of the first memories.

S404, the processor generates a data transmission request descriptor. The processor generates a data transmission request descriptor after calculating the first memory and the corresponding first controller and the second memory and the corresponding second controller. The data transmission request descriptor includes information such as a source system address of the target data, a destination system address of the target data, a data length, a system base address of the first memory, a system base address of the first controller, a system base address of the second memory, and a system base address of the second controller. When there is address interleaving, the target data is stored in a plurality of first memories, and one data transfer request descriptor may refer to the plurality of first memories.

The data transfer request descriptors are stored in a data transfer request queue, which is generated by the processor in the slave memory using the memory space in the slave memory with consecutive addresses. The data transmission request queue is a circular queue, and when the last data transmission request of the queue is completed, the processor modifies the processing pointer to be the head address of the queue so as to perform the next data transmission.

For each data transfer request descriptor, the processor generates a completion queue for storing the data transfer completion descriptors. The target data stored in a first memory corresponds to a data transfer completion descriptor indicating whether the target data stored in the first memory was successfully transferred to a second memory. When the target data is stored in only one first memory, only one data transfer completion descriptor is in the corresponding completion queue. When address interleaving is involved, the target data is stored in the plurality of first memories, the completion queue also has a corresponding plurality of data transfer completion descriptors, and the data transfer completion descriptors are arranged in order of address interleaving channel numbers from small to large. Similar to the data transfer request queue, the completion queue is also stored in the slave memory of the processor and uses the memory space in the slave memory that is address-consecutive.

The data transmission request queue and the completion queue may be understood in conjunction with fig. 5, that is, one data transmission request queue may include a plurality of data transmission request descriptors, one data transmission request descriptor corresponds to one completion queue, and may include a plurality of data transmission completion descriptors. Of course, the data transmission request queue may include only one data transmission request descriptor, and the completion queue may include only one data transmission completion descriptor, which is not limited in detail.

In addition, the data transfer request descriptor may include a completion queue address pointer, a completion queue depth, a completion status bit, a valid flag of the data transfer request descriptor, and the like, in addition to the source system address, the destination system address, and the data length described above. Where the completion queue address pointer indicates the first address of the completion queue stored in the slave memory of the processor, the completion queue may be addressed in a location by the data transfer request descriptor. The completion queue depth indicates the number of first memories in which the target data is stored and the completion status bit indicates whether the target data was successfully transferred to the second memory. The valid flag of the data transfer request descriptor indicates that the current data transfer request has not been completed, and the memory address used by the data transfer request descriptor is still to be used. When the data transfer is completed, the flag becomes invalid, indicating that the memory address used by the data transfer request descriptor is available for use by other data transfer request descriptors.

When the target data is stored in only one first memory, after the data transmission is completed, the data transmission completion descriptor in the completion queue is written into the completion state, and the completion state bit in the data transmission request descriptor is updated into the completion state, which indicates that the data transmission request is completed, and the next data transmission request in the data transmission request queue can be executed. When there are a plurality of first memories, the completion descriptor corresponding to each first memory needs to be updated to be in a completion state, so as to indicate that the execution of the data transmission request is completed.

303. The first controller reads the data transfer request descriptor.

The first controller is configured with a head address pointer of a data transmission queue. The first controller accesses the data transmission queue at fixed time according to the head address pointer of the data transmission queue, checks whether the data transmission request descriptor relates to the first controller, and if yes, reads the data transmission request descriptor.

Or when the processor calculates that the target data relates to the first controller, the processor can also send a message to inform the first controller, the message comprises an address pointer of a corresponding data transmission request descriptor, and the controller accesses a data transmission queue and reads the data transmission request descriptor according to the address pointer. The method of reading the data transmission request descriptor by the first controller is not particularly limited herein.

304. The first controller determines whether to transmit the target data based on the data transmission request descriptor.

The first controller stores information such as a system base address, an address length, a local address corresponding to a system address and the like of a corresponding first memory, and when address interleaving is involved, the first controller also stores address interleaving channel number, address interleaving granularity and the like. The system base address of the first memory is an address allocated by the processor to the first memory in the computer system.

After the first controller reads the data transmission request descriptor, the source system address, the destination system address and the data length of the target data can be obtained. The source system address of the target data indicates the memory in which the target data is located and the destination system address of the target data indicates the memory in which the target data needs to be written. The first controller judges whether the corresponding first memory stores the target data according to the source system address and the data length of the target data and the system base address and the address length of the stored first memory.

If the first controller determines that the target data is not stored in the first memory, the processor is indicated to calculate an error, the first memory does not participate in the transmission of the target data, and the processor recalculates the memory in which the target data is located.

If the first controller determines that the target data is stored in the first memory, then step 305 is performed, and the first controller sends the target data to the forwarding module. Specifically, the first controller converts the source system address of the target data into the local address of the first memory based on the source system address and the data length of the target data in combination with the mapping relation between the system address stored by the first controller and the local address of the memory, and reads the target data from the first memory.

In one possible implementation, reading the data transfer request descriptor, determining whether to transfer target data, performing target data transfer, and acquiring the operating state of the controller is accomplished by setting a set of peripheral component interconnect express (peripheral component interconnect express, PCI-e) specified vendor specific extended function (Designated Vendor-Specific Extended Capability, DVSEC) register sets in the controller. The DVSEC register set may include a control register and a status register, among others. The control register is configured with a head address of the data transmission request queue, a write pointer of the data transmission request queue, an enabling switch and the like, so that the controller can automatically read information of the data transmission request descriptor in the data transmission request queue, judge whether target data are stored in a corresponding memory or not, and transmit the target data. The status register is used for feeding back the status of the controller, the status of the register group, the currently executed data transmission request descriptor pointer, the error status and the like, so that the transmission of the target data can be stopped when the status fails.

The data transmission function is realized by introducing the DVSEC register group, so that the software processing flow is more standardized, and the data processing method provided by the embodiment of the application is easier to realize.

305. The first controller sends the target data to the forwarding module.

After the first controller reads the target data from the first memory, the target data is packaged and carries the target system address of the target data, and then the target data is sent to the forwarding module through the CXL interface.

When address interleaving is involved, the target data is stored in a plurality of first memories, the system address of the target data may be a discontinuous address segment, and the target data stored in each first memory may be related to a different second memory. At this time, the first controller needs to divide the target data according to the boundary of each address segment to form a plurality of data segments, and then sends the data segments to the forwarding module.

306. The forwarding module sends the target data to the second controller.

And the forwarding module forwards the target data to the second controller after receiving the target data. The forwarding module stores the system base address and the address length of the port where the second memory is located, and when address interleaving is involved, the forwarding module further comprises address interleaving channel numbers, address interleaving granularity and port numbers corresponding to the address interleaving channel numbers. The forwarding module analyzes the target data, and determines a target port for forwarding the target data according to a target system address carried by the target data and the data length and by combining the stored information, wherein the target port is the port where the second controller is located.

The following takes CXL protocol scenario as an example, and describes in detail the process of transmitting the target data by the forwarding module with reference to fig. 2. In the CXL protocol scenario, the forwarding module 212 is a CXL Switch, and the forwarding module within the processor includes a Root Port CXL Root Port.

When the first controller and the second controller are independently arranged outside the processor, the transmission of the target data is completed through CXL Switch and/or a forwarding module inside the processor. In a possible scheme, the transmission of the target data may be completed through a CXL Switch, where the CXL Switch receives the target data sent by the first controller 201, determines the destination port, and then sends the target data to the second controller 202. In another possible scheme, the transmission of the target data can be completed through the Root Port CXL Root Port of the processor, where the CXL Root Port receives the target data sent by the first controller 203, determines the destination Port, and then sends the target data to the second controller 204. In another possible scheme, the transmission of the target data is completed through the CXL Switch and the CXL Root Port, the CXL Switch receiving the target data sent by the first controller 201, sending the target data to the CXL Root Port, and then sending the target data to the second controller 203. Alternatively, the CXL Root Port receives the target data sent from the first controller 203, and forwards the target data to the CXL Switch, and the target data is sent to the second controller 201 by the CXL Switch.

When the first controller is independently arranged outside the processor and the second controller is integrated in the processor, the target data is transmitted through the CXL Switch and/or a forwarding module inside the processor. In a possible solution, the CXL Switch receives the target data sent by the first controller 201, sends the target data to the CXL Root Port, and forwards the target data to the internal processor forwarding module connected to the second controller 205 by the CXL Root Port, where the forwarding module sends the target data to the second controller 205. In another possible scheme, the CXL Root Port receives the target data sent by the first controller 203, and then forwards the target data to a forwarding module connected to the second controller 205 by the CXL Root Port, and the forwarding module sends the target data to the second controller 205. When the first controller is integrated in the processor and the second controller is independently disposed outside the processor, the transmission process of the target data is opposite, and will not be described herein.

When the first controller and the second controller are integrated in the processor, for example, the controller 205 and the controller 206, the processor internal forwarding module connected to the controller 205 and the controller 206 transmits the target data, that is, the forwarding module receives the target data sent by the first controller, and then sends the target data to the second controller.

307. The second controller writes the target data to the second memory.

The second controller stores information such as a system base address, an address length, a local address corresponding to a system address and the like of the corresponding second memory, and also stores address interleaving channel number, address interleaving granularity and the like when address interleaving is involved.

After receiving the target data, the second controller analyzes the packaged target data, and writes the target data into the second memory according to the target system address of the target data carried in the target data. Specifically, the second controller converts the destination system address of the target data into the local address of the second memory based on the destination system address and the data length of the target data in combination with the mapping relationship between the stored system address and the local address of the memory, and writes the target data into the second memory, so as to realize the transmission of the target data from the first memory to the second memory, and at this time, the second controller updates the completion status bits in the completion descriptor and the data transmission request descriptor into the completion status.

It is understood that the first controller and the second controller may be the same controller or different controllers. The data processing method provided in this embodiment may also be applied to data handling between different local addresses of the memories, where the first memory and the second memory are the same memory. When the controllers corresponding to the first memory and the second memory are the same controller (i.e., the first controller and the second controller are the same controller), or the first memory and the second memory are the same memory, the transmission of the target data does not need to pass through a forwarding module, and the controller reads the corresponding data from the source address and writes the corresponding data into the destination address.

In one possible implementation, the controller and forwarding module may implement address translation through a Host-managed Device Memory Decoder (HDM Decoder) Decoder of Host-managed device memory. For the controller, the address translation includes translating a system address of the target data to a local address of the memory, and for the forwarding module, the address translation includes translating the system address to a port number where the second controller is located.

The HDM Decoder is an address mapping module defined in CXL protocol, and stores system base address information, address length, address interleaving granularity, address interleaving channel number, local base address information of the memory, port number corresponding to the system address and the like which are distributed to the memory by the processor, so that the system address can be converted into a local address or the port number corresponding to the controller.

However, the HDM Decoder can only be used in a scenario where a processor initiates data reading and writing, but cannot be used in a scenario where a controller initiates data transmission. Therefore, the HDM Decoder is expanded, so that the HDM Decoder supports the scene that the controller initiates data transmission, and address conversion can be performed through the HDM Decoder when the controller initiates data transmission.

Illustratively, in the CXL protocol, the HDM Decoder is located at the transaction layer (Transaction Layer) of the CXL.cache sub-protocol and the CXL.mem sub-protocol, and does not support processing of data of the CXL.io protocol. The CXL.mem sub-protocol supports the processor to load and store the data of the memory, and the CXL.cache sub-protocol supports the processor to cache the data in the memory. The CXL.io sub-protocol is compatible with the PCIe protocol and interacts in the transaction layer packet (Transaction Layer Packet, TLP) format of PCIe, and supports Input/Output (I/O) devices to access data in memory. That is, the HDM Decoder may be used in a scenario where data is transferred between a processor and a memory, but may not be used in a scenario where data is transferred between an I/O device and a memory. When a memory-connected controller is located outside the processor, the controller may be located in an I/O device, i.e., the controller may not use an HDM Decoder for address translation when data is transferred with the memory.

In order to enable the HDM Decoder to support analysis of CXL.io sub-protocol data, the CXL.io sub-protocol data is converted from a system address to a local address or a port number where a controller is located, and the CXL protocol is improved in the embodiment, so that the HDM Decoder is used in the CXL.io sub-protocol. Specifically, the HDM Decoder may be set in the cxl.mem sub-protocol and the cxl.io sub-protocol, respectively, and the HDM Decoder configuration data in the cxl.io sub-protocol may be shared from the HDM decoders of the cxl.cache sub-protocol+the cxl.mem sub-protocol, where the configuration register is still located in a HDM Decoder Capability (Capability) register set in the registers for the cxl.cache sub-protocol and the cxl.mem sub-protocol, and the Capability register set may be a DVSEC register set. The processor only needs to configure the HDM Decoder of the CXL.cache sub-protocol and the CXL.mem sub-protocol once, so that the HDM Decoder can serve the CXL.mem sub-protocol and the CXL.io sub-protocol, that is, the HDM Decoder can process data in the CXL.mem sub-protocol and the CXL.io sub-protocol.

In addition, the HDM Decoder may be set only in the cxl.mem sub-protocol, and specifically, the modification is performed on the CXL protocol in this embodiment, so that the HDM Decoder in the cxl.mem sub-protocol is used to process data in the cxl.mem sub-protocol as well as the cxl.io sub-protocol. The content of the configuration of the HDM Decoder and the configuration registers used by the HDM Decoder by the processor are similar to those described above, and detailed descriptions thereof are omitted here.

When address interleaving is involved, the capacity register set used by the HDM Decoder needs to be added with address interleaving channel number register bits for indicating the channel number of the memory, and the address interleaving channel number register bits are configured by the processor, so that the position of the completion status bit of the data transmission request descriptor and the position of the completion descriptor can be determined through the channel number.

In this embodiment, after the controller reads the data transmission request descriptor, the controller reads the target data from the first memory and writes the target data into the second memory, and only unidirectional transmission is required, so that data interaction is reduced, and a data transmission path is shortened, thereby improving transmission efficiency. In addition, when the processor initiates data transmission, the transmission path of the data in the processor is longer, for example, the data needs to pass through multi-level cache, and the distance between the controller and the memory is often shorter, so that the data transmission is performed by the controller, the data transmission path can be further shortened, and the transmission efficiency is improved. In addition, under the condition that the controller performs data transmission, the processor is not required to issue instructions such as loading, reading and the like, the processor is not required to pass through a computing core of the processor, the instruction set of the processor is not relied on, and the execution thread of the processor is released. In this embodiment, by using the address interleaving technology, multiple segments of data of the target data may be transmitted in parallel, thereby further improving access bandwidth and efficiency.

The embodiments of the present application are described above in terms of methods, and the controllers in the embodiments of the present application are described below in terms of implementation of specific devices.

Referring to fig. 6, an embodiment of the present application provides a schematic diagram of a controller 600, wherein the controller 600 includes a read unit 601 and a write unit 602.

A reading unit 601 for reading a data transmission request descriptor generated by the processor, the data transmission request descriptor being generated based on a data transmission request for requesting transmission of target data.

The reading unit 601 is further configured to read the target data from a first memory based on the data transmission request descriptor, where the first memory stores the target data, and the first memory is a memory corresponding to the controller.

A writing unit 602, configured to write the target data into the second memory based on the data transfer request descriptor.

Optionally, the data transfer request descriptor indicates one or more of the following information: the method comprises the steps of a source system address of target data, a destination system address of the target data, a data length of the target data, a completion queue address pointer, a completion queue depth and a completion status bit.

Optionally, the controller 600 further includes a determining unit 603 for describing whether the first memory stores the target data based on the data transmission request Fu Panduan.

Optionally, the target data is stored in the first memory using an address interleaving technique.

Optionally, the writing unit 602 is specifically configured to send the target data to the second controller based on the data transmission request descriptor; and the second controller writes the target data into a second memory, wherein the second memory is a memory corresponding to the second controller.

The units in the controller 600 perform the operations of the controller in the embodiment shown in fig. 3, which are not described herein.

Referring to fig. 7, an embodiment of the present application provides a schematic diagram of a processor 700, where the processor 700 includes a determining unit 701 and a generating unit 702.

A determining unit 701 for determining a data transmission request for requesting transmission of the target data.

The generating unit 702 is configured to generate a data transfer request descriptor based on the data transfer request, the data transfer request descriptor being configured to be provided to a storage device, the storage device including a controller and a first memory, the controller being configured to read target data from the first memory and write the target data to the second memory based on the data transfer request descriptor.

The units in the processor 700 perform the operations of the processor in the embodiment shown in fig. 3, which are not described herein.

Referring now to FIG. 8, a schematic diagram of one possible architecture of a computing device 800 according to an embodiment of the present application includes a processor 801, a communication interface 802, a memory 803, and a bus 804. The processor 801, the communication interface 802, and the memory 803 are connected to each other through a bus 804. In the embodiment of the present application, the processor 801 is configured to control and manage actions of the controller, and the communication interface 802 is configured to support communication by the controller. A memory 803 for storing program codes and data of the controller.

The processor 801 may be a central processing unit, a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. Which may implement or perform the various exemplary logic blocks, modules, and circuits described in connection with this disclosure. A processor may also be a combination that performs a computational function, such as a combination comprising one or more microprocessors, a combination of a digital signal processor and a microprocessor, and so forth. Bus 804 may be a peripheral component interconnect standard (Peripheral Component Interconnect, PCI) bus or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, among others. The buses may be divided into address buses, data buses, control buses, etc. For ease of illustration, only one thick line is shown in fig. 8, but not only one bus or one type of bus.

Embodiments of the present application also provide a computer-readable storage medium comprising instructions that, when executed on a computer, cause the computer to perform the method of the embodiment shown in fig. 3 described above.

Embodiments of the present application also provide a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method of the embodiment shown in fig. 3 described above.

The embodiment of the application further provides a chip system, which comprises at least one processor and a communication interface, wherein the communication interface and the at least one processor are interconnected through a line, and the at least one processor is used for running a computer program or instructions to execute the method in the embodiment shown in fig. 3.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.

In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a read-only memory (ROM), a random access memory (RAM, random access memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Claims

1. A method of data processing, comprising:

the first controller reads a data transmission request descriptor generated by the processor, the data transmission request descriptor being generated based on a data transmission request for requesting transmission of target data;

the first controller reads the target data from a first memory based on the data transmission request descriptor, wherein the first memory stores the target data, and the first memory is a memory corresponding to the controller;

the first controller writes the target data to a second memory based on the data transfer request descriptor.

2. The method of claim 1, wherein the data transmission request descriptor indicates one or more of the following information: a source system address of target data, a destination system address of the target data, a data length of the target data, a completion queue address pointer, a completion queue depth, and a completion status bit.

3. The method according to any one of claims 1 or 2, wherein prior to the first controller reading the target data from the first memory based on the data transfer request descriptor, the method further comprises:

The first controller determines whether the first memory stores the target data based on the data transfer request descriptor.

4. A method according to any one of claims 1 to 3, wherein the target data is stored in the first memory using an address interleaving technique.

5. The method of any of claims 1 to 4, wherein the first controller writing the target data to a second memory based on the data transfer request descriptor, comprising:

the first controller sends the target data to a second controller based on the data transmission request descriptor;

and the second controller writes the target data into the second memory, wherein the second memory is a memory corresponding to the second controller.

6. A method of data processing, comprising:

the processor determines a data transmission request, wherein the data transmission request is used for requesting transmission of target data;

the processor generates a data transfer request descriptor based on the data transfer request, the data transfer request descriptor for provision to a storage device, the storage device including a first controller and a first memory, the first controller for reading the target data from the first memory and writing the target data to a second memory based on the data transfer request descriptor.

7. The method of claim 6, wherein the data transmission request descriptor indicates one or more of the following information: the method comprises the steps of a source system address of target data, a destination system address of the target data, a data length of the target data, a completion queue address pointer, a completion queue depth and a completion status bit.

8. A controller, comprising:

a reading unit configured to read a data transmission request descriptor generated by a processor, the data transmission request descriptor being generated based on a data transmission request for requesting transmission of target data;

the reading unit is further used for reading the target data from a first memory based on the data transmission request descriptor, wherein the first memory stores the target data, and the first memory is a memory corresponding to the controller;

and the writing unit is used for writing the target data into the second memory based on the data transmission request descriptor.

9. A processor, comprising:

a determining unit configured to determine a data transmission request for requesting transmission of target data;

A generation unit configured to generate a data transfer request descriptor based on the data transfer request, the data transfer request descriptor being configured to be provided to a storage device, the storage device including a controller and a first memory, the controller being configured to read the target data from the first memory and write the target data to a second memory based on the data transfer request descriptor.

10. A memory device, wherein the memory device comprises a controller and a memory;

the memory is used for storing instructions;

the controller is configured to execute instructions stored in the memory to implement the method of any one of claims 1 to 5 or to implement the method of claim 6 or 7.

11. A computing device comprising a processor and a storage device, the storage device comprising a controller and a memory, wherein the storage device is to store instructions, the processor to execute the instructions stored by the storage device to implement the method of any one of claims 1 to 5, or to implement the method of claim 6 or 7.