CN114238184B - Multifunctional DMA transmission method, device and storage medium - Google Patents
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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Abstract
The invention relates to a transmission method, a transmission device and a storage medium of a multifunctional DMA. According to the invention, a CPU configures corresponding DMA descriptor parameters in a descriptor register according to the DMA service demand, wherein the DMA descriptor parameters comprise mode parameters, and the mode parameters comprise a first mode, a second mode, a third mode and a fourth mode; the DMA controller obtains the DMA descriptor parameters from the descriptor register to form a DMA descriptor; the DMA controller arbitrates and selects a DMA channel for data processing, and obtains a DMA descriptor of the corresponding channel; acquiring DMA description Fu Namo type parameters, and determining a data processing strategy according to the type of the mode parameters; substituting other parameters in the DMA descriptor into a preset data processing strategy corresponding to the mode parameters for execution. The invention forms different data processing strategies based on DMA descriptors containing different mode parameters and related parameters to realize various functions such as data movement, data pattern setting, data CRC check code calculation, data transmission among caches and the like.
Description
Technical Field
The present invention relates to the field of DMA data transmission, and in particular, to a method and apparatus for transmitting a multi-functional DMA, and a storage medium.
Background
DMA (Direct Memory Access: direct memory access) is a data transfer technique that exchanges data directly with the system memory without passing through the CPU, and can realize memory-to-memory, device-to-memory and memory-to-device-to-data transfer, greatly reducing CPU workload, solving the problem of excessive consumption of CPU resources by data transfer through DMA, and making the CPU more focused on computation, control and the like.
In the prior art, the process of DMA is implemented by a DMA controller. The DMA controller has the following functions: a system HOLD (HOLD) signal can be issued to the CPU, issuing a bus take over request; after receiving the signal of allowing the CPU to take over, the DMA controller replaces the CPU to carry out bus control, enters a DMA mode and releases the CPU; after completing data transmission or generating errors, the DMA initiates an interrupt to the CPU and returns the bus control right to the CPU. DMA control data transfer involves two operations of reading and writing, and a DMA controller is required to address a memory and modify an address pointer so as to realize the reading and writing operation of the memory; the number of bytes for the current DMA transfer can be determined. The conventional DMA controller can only perform the above data transfer related operations, and has relatively single functions, and if it is required to perform consistency check on transferred data, an additional hardware unit for calculating the CRC check code is required to participate.
Disclosure of Invention
In order to solve the above technical problems or at least partially solve the above technical problems, the present invention provides a method, an apparatus and a storage medium for transmitting a multifunctional DMA.
In a first aspect, the present invention provides a method for transmitting a multifunctional DMA, including: the CPU configures corresponding DMA descriptor parameters in a descriptor register according to the DMA service demand, wherein the DMA descriptor parameters comprise mode parameters, and the mode parameters comprise a first mode, a second mode, a third mode and a fourth mode;
The DMA controller obtains the DMA descriptor parameters from the descriptor register to form a DMA descriptor;
the DMA controller arbitrates and selects a DMA channel for data processing, and obtains a DMA descriptor of the corresponding channel;
acquiring DMA description Fu Namo type parameters, and determining a data processing strategy according to the type of the mode parameters; substituting other parameters in the DMA descriptor into a preset data processing strategy corresponding to the mode parameters for execution.
Still further, the CPU supports at least four descriptor registers, through which the CPU configures DMA descriptor parameters containing four mode parameters, respectively.
Still further, the DMA descriptor parameters including the first mode further include: source address, destination address and transmission data length; the DMA descriptor parameters including the second mode further include: a data pattern, a data pattern length, and a destination address; the DMA descriptor parameters including the third mode further include: source address, data length and CRC initial value; the DMA descriptor parameters comprising the fourth mode also include a source buffer ID and a destination buffer ID.
Furthermore, the process of configuring the DMA descriptor parameters by the CPU to form the DMA descriptor and the process of acquiring the DMA descriptor by the DMA controller adopt an asynchronous design, a DMA descriptor cache is constructed, the DMA descriptor configured by the CPU is stored in the DMA descriptor cache, and the DMA controller acquires the required DMA descriptor from the DMA descriptor cache to control the execution of the corresponding data processing strategy.
Still further, the obtaining the DMA description Fu Namo type parameter, and determining the data processing policy according to the type of the mode parameter includes:
Acquiring DMA description Fu Namo type parameters and detecting the type of the mode parameters;
If the DMA description Fu Namo is in the first mode, the DMA controller forms a first data processing policy implementation,
If the DMA description Fu Namo is in the second mode, the DMA controller forms a second data processing policy implementation,
If the DMA description Fu Namo is in the third mode, the DMA controller forms a third data processing policy implementation,
If the DMA description Fu Namo is in the fourth mode, the DMA controller forms a fourth data processing policy implementation.
Further, the first data processing strategy obtains data to be transmitted according to the source address and the data transmission length, fragments the data to be transmitted according to the transmission capacity of the burst mode, writes the data with transmission into the destination address according to the fragments, and returns a completion mark when the data with transmission is completed;
The second data processing strategy segments the appointed data pattern according to the transmission capacity of the burst mode, repeatedly writes the content with the data pattern into the appointed destination address range according to the segments, and returns a completion mark when the length of the destination address range is an integer of the length of the data pattern;
The third data processing strategy confirms the data of the CRC check code to be calculated according to the source address and the data length, reads the data of the CRC check code to be calculated according to the transmission capacity slices according to the burst mode, calculates the CRC check code by utilizing the CRC initial value, and returns the CRC check code when the data processing strategy is finished;
And the fourth data processing strategy converts the source buffer zone ID and the destination buffer zone ID into a source buffer address and a destination buffer address respectively, acquires data to be transmitted from the source buffer address, fragments the data to be transmitted according to the transmission capacity of the burst mode, writes the data with transmission into the destination buffer address according to fragments, and returns a completion mark when the data with transmission is completed.
Further, each DMA descriptor includes a DMA descriptor ID, and the DMA descriptor ID is included in the result feedback information of the completion flag and the CRC check code, and indicates, through the DMA descriptor ID, the DMA descriptor corresponding to the data processing policy for completing the data transmission or the CRC check code calculation.
Further, the CPU configures the transmission capacity of the burst mode through the burst mode transmission capacity register according to the memory bit width or according to the bus bit width; the DMA controller acquires the transmission capacity of the burst mode from the burst mode transmission capacity register to perform the burst processing on the data.
In a second aspect, the present invention provides an apparatus for implementing a multi-function DMA transfer, comprising: the first configuration module is used for configuring DMA descriptor parameters of the DMA descriptor according to the DMA service requirements;
The second configuration module is used for configuring the data capacity of the burst mode;
The descriptor management module constructs a DMA descriptor cache, updates DMA descriptor parameters configured by the CPU to form a DMA descriptor, writes the DMA descriptor into the DMA descriptor cache, and acquires the DMA descriptor of the corresponding channel from the DMA descriptor cache;
And the execution module forms corresponding data processing strategy execution according to the DMA descriptor provided by the descriptor management module, feeds back the execution result of the data processing strategy to the descriptor management module, and deletes the completed DMA descriptor according to the execution result.
In a third aspect, the present invention provides a storage medium for implementing a method for transferring a multi-function DMA, where the storage medium for implementing a method for transferring a multi-function DMA stores at least one instruction, and reads and executes the instruction to implement the method for transferring a multi-function DMA.
Compared with the prior art, the technical scheme provided by the embodiment of the invention has the following advantages:
The invention controls the DMA controller to execute different data processing strategies through the DMA descriptors containing different mode parameters; when the mode parameter of the DMA descriptor is the first mode, the DMA controller transmits the data of the source address to the destination address to realize data movement; when the mode parameter of the DMA descriptor is the second mode, the DMA controller repeatedly transmits the data pattern to the destination address to realize setting of the data pattern; when the mode parameter of the DMA descriptor is the third mode, the DMA controller calculates CRC check codes of the appointed data, and the CRC check codes of the data are calculated; and when the mode parameter of the DMA descriptor is the fourth mode, the DMA controller transmits the cache data in the cache indicated by the source cache region ID to the cache indicated by the destination cache region ID, so that data transmission among caches is realized. Finally, the multifunctional DMA transmission is realized based on the DMA descriptor containing different mode parameters.
In the invention, the CPU supports at least four descriptor registers, the CPU respectively configures the DMA descriptor parameters containing four mode parameters through four different descriptor registers, and the CPU can configure the DMA descriptor parameters in parallel, thereby improving the efficiency of DMA transmission.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a flowchart of a method for transmitting a multifunctional DMA according to an embodiment of the present invention;
FIG. 2 is a flowchart of acquiring DMA description Fu Namo type parameters and determining a data processing policy according to the type of the mode parameters according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a transmission device for implementing multifunctional DMA according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a first configuration module and a second configuration module according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a descriptor management module according to an embodiment of the present invention;
Fig. 6 is a schematic diagram of an execution module according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Example 1
Referring to fig. 1, an embodiment of the present invention provides a method for transmitting a multi-functional DMA, including:
S100, a CPU configures corresponding DMA descriptor parameters in a descriptor register according to DMA service requirements, wherein the DMA descriptor parameters comprise mode parameters, and the mode parameters comprise a first mode, a second mode, a third mode and a fourth mode; in the implementation process, referring to fig. 4, the CPU supports at least four descriptor registers, and supports parallel configuration of DMA descriptor parameters including four mode parameters through four different descriptor registers.
In the implementation process, the DMA descriptor parameters including the first mode further include: source address, destination address, and transfer data length.
The DMA descriptor parameters including the second mode further include: the data pattern is the formulated data which needs to be written into the destination address, and the data pattern length is the length of the designated data.
The DMA descriptor parameters including the third mode further include: source address, data length and CRC initial value;
the DMA descriptor parameters comprising the fourth mode also include a source buffer ID and a destination buffer ID.
S200, the DMA controller acquires the DMA descriptor parameters from the descriptor register to form a DMA descriptor. In a specific implementation process, the DMA descriptor includes 128 bits, and a mode parameter, a source address, a destination address, a transmission data length, a data pattern length, a destination address, a source address, a data length, and a CRC initial value are configured in the 128-bit DMA descriptor by a preset format.
S300, the DMA controller arbitrates and selects a DMA channel for data processing, and obtains a DMA descriptor of the corresponding channel.
In the specific implementation process, the processes of configuring the DMA descriptor parameters to form the DMA descriptor by the CPU in step S100, step S200 and step S300 and obtaining the DMA descriptor by the DMA controller adopt asynchronous design, specifically, a DMA descriptor cache is constructed, the DMA descriptor configured by the CPU is stored in the DMA descriptor cache, and the DMA controller obtains the required DMA descriptor from the DMA descriptor cache to control the execution of the corresponding data processing strategy, and the two processes are mutually independent. The created descriptor cache address is specified by a register in the DMA controller.
S400, acquiring DMA description Fu Namo type parameters, and determining a data processing strategy according to the type of the mode parameters; in the specific implementation process, referring to fig. 2, the obtaining the DMA description Fu Namo type parameter, determining the data processing policy according to the type of the mode parameter includes:
S401, acquiring DMA description Fu Namo type parameters, and detecting the type of the DMA description Fu Zhongmo type parameters;
S402, if the DMA description Fu Namo is detected as the first mode, the DMA controller forms a first data processing strategy execution.
S403, if the DMA description Fu Namo is detected as the second mode, the DMA controller forms a second data processing strategy execution.
S404, if the DMA description Fu Namo is detected as the third mode, the DMA controller forms a third data processing strategy execution.
S405, if the DMA description Fu Namo is detected as the fourth mode, the DMA controller forms a fourth data processing strategy execution.
S500, substituting other parameters in the DMA descriptor into a preset data processing strategy corresponding to the mode parameter for execution.
Specifically, the first data processing strategy obtains data to be transmitted according to a source address and a data transmission length in the DMA descriptor, fragments the data to be transmitted according to the transmission capacity of the burst mode, writes the data with transmission into a destination address according to the fragments, and returns a completion flag when the data transmission is completed.
And the second data processing strategy segments the designated data pattern in the DMA descriptor according to the transmission capacity of the burst mode, repeatedly writes the content with the data pattern into the designated destination address range according to the segments, wherein the length of the destination address range is an integer multiple of the length of the data pattern, and returns an execution completion flag after the data pattern is set.
The third data processing strategy confirms the data of the CRC check code to be calculated according to the source address and the data length, reads the data of the CRC check code to be calculated according to the transmission capacity slices according to the burst mode, calculates the CRC check code by utilizing the CRC initial value, and returns the CRC check code when the data processing strategy is finished;
And the fourth data processing strategy converts the DMA description Fu Nayuan buffer zone ID and the destination buffer zone ID into a source buffer address and a destination buffer address respectively, acquires data to be transmitted from the source buffer address, fragments the data to be transmitted according to the transmission capacity of the burst mode, writes the data with transmission into the destination buffer address according to fragments, and returns a completion mark when the completion is completed.
In the implementation process, each DMA descriptor comprises a DMA descriptor ID, the result feedback information of the completion mark and the CRC check code comprises the DMA descriptor ID, and the DMA descriptor ID indicates the DMA descriptor corresponding to the data processing strategy for completing data transmission or CRC check code calculation.
The CPU configures the transmission capacity of the burst mode through a burst mode transmission capacity register according to the memory bit width or the bus bit width; the DMA controller acquires the transmission capacity of the burst mode from the burst mode transmission capacity register to perform the burst processing on the data.
Example 2
Referring to fig. 3, an embodiment of the present invention provides an apparatus for implementing a multi-function DMA transfer, including:
The first configuration module is used for configuring DMA descriptor parameters of the DMA descriptor according to the DMA service requirements;
The second configuration module is used for configuring the data capacity of the burst mode;
Specifically, referring to fig. 4, the first configuration module includes a CPU and a descriptor register, and the second configuration module includes a CPU and a burst mode transmission capacity register. The CPU configures corresponding DMA descriptor parameters in the descriptor register according to the DMA service requirement, and configures the data capacity of the burst mode according to the memory bit width or the bus bit width, wherein the data capacity of the burst mode does not exceed the memory bit width and the bus bit width.
The descriptor management module constructs a DMA descriptor cache, updates DMA descriptor parameters configured by the CPU to form a DMA descriptor, writes the DMA descriptor into the DMA descriptor cache, and acquires the DMA descriptor of the corresponding channel from the DMA descriptor cache; specifically, referring to fig. 5, the descriptor management module includes a descriptor management unit and a DMA descriptor buffer, where the descriptor management unit forms a corresponding DMA descriptor by using the DMA descriptor parameter configured by the first configuration module, and stores the DMA descriptor in the DMA descriptor buffer, and the descriptor management unit obtains the corresponding DMA descriptor from the DMA descriptor buffer to the execution module.
And the execution module forms corresponding data processing strategy execution according to the DMA descriptor provided by the descriptor management module, feeds back the execution result of the data processing strategy to the descriptor management module, deletes the completed DMA descriptor according to the execution result, and clears the DMA descriptor cache space to accommodate the new DMA descriptor.
Specifically, referring to fig. 6, the execution module includes a data processing policy selection configuration unit, where the data processing side path selection configuration unit configures a corresponding first data processing policy, a second data processing policy, a third data processing policy, and a fourth data processing policy according to the DMA descriptor, the data processing policy execution unit asynchronously executes each data processing policy, the data processing policy execution unit communicates a read channel and a write channel, and the data processing policy execution unit is connected to the first cache unit, the second cache unit, the third cache unit, and the fourth cache unit. The data processing strategy executing unit is connected with the descriptor management module and feeds back the data processing strategy executing result to the descriptor management module.
Specifically, the data processing strategy executing unit asynchronously processes the data acquisition process through the read channel and the data output process through the write channel in the first data processing strategy and the fourth data processing strategy; in the second data processing strategy, the process of acquiring the data pattern and outputting the data pattern through the writing channel is asynchronous; and in the third data processing strategy, the process of acquiring the data to be checked by CRC and the CRC checking through the read channel are asynchronous. And supporting the asynchronous process of the data processing strategy executing unit through the first cache unit, the fourth cache unit, the second cache unit and the third cache unit respectively.
The execution module monitors the states of the read channel and the write channel through the DMA channel management unit, selects the DMA channel for executing the data processing strategy according to the state arbitration, informs the descriptor management module, and the descriptor management module selects the corresponding DMA descriptor and feeds back the DMA descriptor to the DMA channel management unit.
Example 3
The embodiment of the invention provides a storage medium for realizing a transmission method of a multifunctional DMA, which stores at least one instruction, reads and executes the instruction to realize the transmission method of the multifunctional DMA.
The invention controls the DMA controller to execute different data processing strategies through the DMA descriptors containing different mode parameters; when the mode parameter of the DMA descriptor is the first mode, the DMA controller transmits the data of the source address to the destination address to realize data movement; when the mode parameter of the DMA descriptor is the second mode, the DMA controller repeatedly transmits the data pattern to the destination address to realize setting of the data pattern; when the mode parameter of the DMA descriptor is the third mode, the DMA controller calculates CRC check codes of the appointed data, and the CRC check codes of the data are calculated; and when the mode parameter of the DMA descriptor is the fourth mode, the DMA controller transmits the cache data in the cache indicated by the source cache region ID to the cache indicated by the destination cache region ID, so that data transmission among caches is realized. Finally, the multifunctional DMA transmission is realized based on the DMA descriptor containing different mode parameters.
In the invention, the CPU supports at least four descriptor registers, the CPU respectively configures the DMA descriptor parameters containing four mode parameters through four different descriptor registers, and the CPU can configure the DMA descriptor parameters in parallel, thereby improving the efficiency of DMA transmission.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (7)
1. A method for transferring a multi-function DMA, comprising: the CPU configures corresponding DMA descriptor parameters in a descriptor register according to DMA service requirements, wherein the DMA descriptor parameters comprise mode parameters, the mode parameters comprise a first mode, a second mode, a third mode and a fourth mode, and the DMA descriptor parameters comprising the first mode further comprise: the source address, the destination address, and the transfer data length, including the DMA descriptor parameters of the second mode, further include: the data pattern, the data pattern length and the destination address, and the DMA descriptor parameters including the third mode further include: the source address, the data length and the CRC initial value, and the DMA descriptor parameters comprising the fourth mode also comprise a source buffer zone ID and a destination buffer zone ID;
The DMA controller obtains the DMA descriptor parameters from the descriptor register to form a DMA descriptor;
the DMA controller arbitrates and selects a DMA channel for data processing, and obtains a DMA descriptor of the corresponding channel;
Acquiring DMA description Fu Namo type parameters, and determining a data processing strategy according to the type of the mode parameters; substituting other parameters in the DMA descriptor into a preset data processing strategy corresponding to the mode parameters for execution, wherein the method comprises the following steps: acquiring DMA description Fu Namo type parameters and detecting the type of the mode parameters; if the DMA description Fu Namo type parameter is in the first mode, the DMA controller forms a first data processing strategy to execute, the first data processing strategy obtains data to be transmitted according to a source address and a data transmission length, the data to be transmitted is fragmented according to the transmission capacity of the burst mode, the data to be transmitted is written into a destination address according to the fragments, and a completion mark is returned when the completion is completed;
If the DMA description Fu Namo type parameter is in the second mode, the DMA controller forms a second data processing strategy to execute, the second data processing strategy slices the appointed data pattern according to the transmission capacity of the burst mode, the content of the data pattern is repeatedly written into the appointed destination address range according to the slices, and when the length of the destination address range is an integer of the length of the data pattern, a completion mark is returned;
If the DMA description Fu Namo type parameter is in a third mode, the DMA controller forms a third data processing strategy to execute, the third data processing strategy confirms the data of the CRC check code to be calculated according to the source address and the data length, reads the data of the CRC check code to be calculated according to the transmission capacity of the burst mode in a slicing way, calculates the CRC check code by utilizing the CRC initial value, and returns the CRC check code when the data is finished;
If the DMA description Fu Namo parameter is in the fourth mode, the DMA controller forms a fourth data processing policy to execute, the fourth data processing policy converts the source buffer ID and the destination buffer ID into a source buffer address and a destination buffer address respectively, then obtains data to be transmitted from the source buffer address, and fragments the data to be transmitted according to the transmission capacity of the burst mode, writes the data to be transmitted into the destination buffer address according to fragments, and returns a completion flag when the completion is completed.
2. The method of claim 1, wherein the CPU supports at least four descriptor registers, and wherein the CPU configures DMA descriptor parameters including four mode parameters through four different descriptor registers, respectively.
3. The method according to claim 1, wherein the CPU configures DMA descriptor parameters to form DMA descriptors and the DMA controller obtains DMA descriptors using an asynchronous design, constructs a DMA descriptor cache, stores the DMA descriptors configured by the CPU in the DMA descriptor cache, and the DMA controller obtains DMA descriptors from the DMA descriptor cache to control execution of the corresponding data processing policy.
4. The method according to claim 1, wherein each DMA descriptor includes a DMA descriptor ID, and the DMA descriptor ID is included in the result feedback information of the completion flag and the CRC check code, and the DMA descriptor ID indicates the DMA descriptor corresponding to the completed data processing policy.
5. The transmission method of the multifunctional DMA according to claim 1, wherein the CPU configures a transmission capacity of the burst mode through a transmission capacity register of the burst mode according to a memory bit width or a bus bit width; the DMA controller acquires the transmission capacity of the burst mode from the burst mode transmission capacity register to perform the burst processing on the data.
6. An apparatus for implementing a multi-function DMA transfer, comprising: the first configuration module is configured to configure DMA descriptor parameters of the DMA descriptor according to DMA service requirements, wherein the DMA descriptor parameters include mode parameters, the mode parameters include a first mode, a second mode, a third mode and a fourth mode, and the DMA descriptor parameters including the first mode further include: the source address, the destination address, and the transfer data length, including the DMA descriptor parameters of the second mode, further include: the data pattern, the data pattern length and the destination address, and the DMA descriptor parameters including the third mode further include: the source address, the data length and the CRC initial value, and the DMA descriptor parameters comprising the fourth mode also comprise a source buffer zone ID and a destination buffer zone ID;
The second configuration module is used for configuring the data capacity of the burst mode;
The descriptor management module constructs a DMA descriptor cache, updates DMA descriptor parameters configured by the CPU to form a DMA descriptor, writes the DMA descriptor into the DMA descriptor cache, and acquires the DMA descriptor of the corresponding channel from the DMA descriptor cache;
The execution module forms corresponding data processing strategy execution according to the DMA descriptor provided by the descriptor management module, and comprises the following steps: acquiring DMA description Fu Namo type parameters and detecting the type of the mode parameters; if the DMA description Fu Namo type parameter is in the first mode, the DMA controller forms a first data processing strategy to execute, the first data processing strategy obtains data to be transmitted according to a source address and a data transmission length, the data to be transmitted is fragmented according to the transmission capacity of the burst mode, the data to be transmitted is written into a destination address according to the fragments, and a completion mark is returned when the completion is completed; if the DMA description Fu Namo type parameter is in the second mode, the DMA controller forms a second data processing strategy to execute, the second data processing strategy slices the appointed data pattern according to the transmission capacity of the burst mode, the content of the data pattern is repeatedly written into the appointed destination address range according to the slices, and when the length of the destination address range is an integer of the length of the data pattern, a completion mark is returned; if the DMA description Fu Namo type parameter is in a third mode, the DMA controller forms a third data processing strategy to execute, the third data processing strategy confirms the data of the CRC check code to be calculated according to the source address and the data length, reads the data of the CRC check code to be calculated according to the transmission capacity of the burst mode in a slicing way, calculates the CRC check code by utilizing the CRC initial value, and returns the CRC check code when the data is finished; if the DMA description Fu Namo type parameter is in the fourth mode, the DMA controller forms a fourth data processing strategy to execute, the fourth data processing strategy converts the source buffer zone ID and the destination buffer zone ID into a source buffer address and a destination buffer address respectively, then obtains data to be transmitted from the source buffer address, and fragments the data to be transmitted according to the transmission capacity of the burst mode, writes the data to be transmitted into the destination buffer address according to fragments, and returns a completion mark when the completion is completed; and the execution module feeds back the execution result of the data processing strategy to the descriptor management module, and the descriptor management module deletes the completed DMA descriptor according to the execution result.
7. A storage medium for implementing a method for transferring a multifunctional DMA, wherein the storage medium for implementing a method for transferring a multifunctional DMA stores at least one instruction, and a computer reads and executes the instruction to implement a method for transferring a multifunctional DMA according to any one of claims 1 to 5.
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