CN114238184A - Multifunctional DMA transmission method, device and storage medium - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
Abstract
The invention relates to a transmission method and a device of a multifunctional DMA and a storage medium. The CPU configures corresponding DMA descriptor parameters in a descriptor register according to DMA service requirements, wherein the DMA descriptor parameters comprise mode parameters, and the mode parameters comprise a first mode, a second mode, a third mode and a fourth mode; the DMA controller acquires DMA descriptor parameters from the descriptor register to form a DMA descriptor; the DMA controller arbitrates and selects a DMA channel for data processing, and obtains a DMA descriptor of the corresponding channel; obtaining a mode parameter in a DMA descriptor, and determining a data processing strategy according to the type of the mode parameter; and substituting other parameters in the DMA descriptor into a preset data processing strategy corresponding to the mode parameter for execution. The invention forms different data processing strategies based on the DMA descriptors containing different mode parameters and related parameters to realize multiple functions of data movement, data pattern setting, data CRC check code calculation, data transmission between caches and the like.
Description
Technical Field
The present invention relates to the field of DMA data transmission, and in particular, to a method and an apparatus for transmitting a multifunctional DMA, and a storage medium.
Background
DMA (Direct Memory Access) is a data transfer technology that exchanges data directly with a system Memory without a CPU, and can realize data transfer from a Memory to a Memory, from a device to a Memory, and from a Memory to a device, thereby greatly reducing the workload of the CPU.
In the prior art, the process of DMA is implemented by a DMA controller. The DMA controller has the following functions: can send out system HOLD (HOLD) signal to CPU, make bus take-over request; after receiving a takeover permission signal sent by the CPU, the DMA controller replaces the CPU to perform bus control, enters a DMA mode and liberates the CPU; after finishing data transmission or generating errors, the DMA initiates interruption to the CPU, and returns the bus control right to the CPU. DMA control data transfer relates to two operations of reading and writing, and a DMA controller is required to address a memory and modify an address pointer to realize the reading and writing operation of the memory; the number of bytes of this DMA transfer can be determined. The conventional DMA controller can only perform the operations related to the data transfer, has a relatively single function, and needs an additional hardware unit for calculating the CRC check code to participate if the transferred data needs to be checked for consistency.
Disclosure of Invention
In order to solve the above technical problems, or at least partially solve the above technical problems, the present invention provides a method, an apparatus, and a storage medium for transferring a multifunctional DMA.
In a first aspect, the present invention provides a method for transferring a multifunctional DMA, including: the CPU configures corresponding DMA descriptor parameters in a descriptor register according to DMA service requirements, wherein the DMA descriptor parameters comprise mode parameters, and the mode parameters comprise a first mode, a second mode, a third mode and a fourth mode;
the DMA controller acquires DMA descriptor parameters from the descriptor register to form a DMA descriptor;
the DMA controller arbitrates and selects a DMA channel for data processing, and obtains a DMA descriptor of the corresponding channel;
obtaining a mode parameter in a DMA descriptor, and determining a data processing strategy according to the type of the mode parameter; and substituting other parameters in the DMA descriptor into a preset data processing strategy corresponding to the mode parameter for execution.
Further, the CPU supports at least four descriptor registers, and the CPU configures the DMA descriptor parameters including the four mode parameters through four different descriptor registers, respectively.
Further, the DMA descriptor parameter comprising the first mode further comprises: source address, destination address and transmission data length; the DMA descriptor parameters including the second mode further include: data pattern, data pattern length, and destination address; the DMA descriptor parameters including the third mode further include: source address, data length and CRC initial value; the DMA descriptor parameters containing the fourth mode also include the source buffer ID and the destination buffer ID.
Furthermore, the process of the CPU configuring the DMA descriptor parameter to form the DMA descriptor and the process of the DMA controller acquiring the DMA descriptor adopt an asynchronous design, a DMA descriptor cache is constructed, the DMA descriptor configured by the CPU is stored in the DMA descriptor cache, and the DMA controller acquires the required DMA descriptor from the DMA descriptor cache to control the execution of the corresponding data processing policy.
Further, the obtaining the mode parameter in the DMA descriptor, and determining the data processing policy according to the type of the mode parameter includes:
obtaining a mode parameter in a DMA descriptor, and detecting the type of the mode parameter;
if the mode parameter in the DMA descriptor is the first mode, the DMA controller forms a first data processing policy enforcement,
if the mode parameter in the DMA descriptor is the second mode, the DMA controller forms a second data processing strategy execution,
if the mode parameter in the DMA descriptor is a third mode, the DMA controller forms a third data processing policy implementation,
and if the mode parameter in the DMA descriptor is the fourth mode, the DMA controller forms a fourth data processing strategy to execute.
Furthermore, the first data processing strategy acquires data to be transmitted according to a source address and a data transmission length, divides the data to be transmitted into fragments according to the transmission capacity of a burst mode, writes the data to be transmitted into a destination address according to the fragments, and returns a completion flag when the completion is finished;
the second data processing strategy divides the appointed data pattern into pieces according to the transmission capacity of the burst mode, repeatedly writes the content with the data pattern into an appointed destination address range according to the pieces, and returns a completion mark when the length of the destination address range is the integral completion of the length of the data pattern;
the third data processing strategy confirms the data of the CRC to be calculated according to the source address and the data length, reads the data of the CRC to be calculated according to the transmission capacity fragmentation according to the burst mode, calculates the CRC by using the initial value of the CRC, and returns the CRC when the calculation is finished;
and the fourth data processing strategy respectively converts the source buffer area ID and the destination buffer area ID into a source cache address and a destination cache address, acquires the data to be transmitted from the source cache address, divides the data to be transmitted into fragments according to the transmission capacity of a burst mode, writes the data to be transmitted into the destination cache address according to the fragments, and returns a completion mark when the completion is finished.
Furthermore, each kind of DMA descriptor includes a DMA descriptor ID, the result feedback information of the completion flag and the CRC check code includes the DMA descriptor ID, and the DMA descriptor ID indicates the DMA descriptor corresponding to the data processing policy for completing the data transfer or the CRC check code calculation.
Furthermore, the CPU configures the transmission capacity of the burst mode through a burst mode transmission capacity register according to the memory bit width or according to the bus bit width; the DMA controller acquires the transmission capacity of the burst mode from the burst mode transmission capacity register to perform fragmentation processing on the data.
In a second aspect, the present invention provides an apparatus for implementing multifunctional DMA transfer, including: the first configuration module is used for configuring DMA descriptor parameters of the DMA descriptors according to DMA service requirements;
a second configuration module to configure a data capacity of a burst mode;
the descriptor management module is used for constructing a DMA descriptor cache, updating DMA descriptor parameters configured by the CPU to form DMA descriptors, writing the DMA descriptors into the DMA descriptor cache, and acquiring the DMA descriptors of corresponding channels from the DMA descriptor cache;
and the execution module forms a corresponding data processing strategy execution according to the DMA descriptor provided by the descriptor management module, feeds back the execution result of the data processing strategy to the descriptor management module, and deletes the completed DMA descriptor according to the execution result.
In a third aspect, the present invention provides a storage medium for implementing a multifunctional DMA transfer method, where the storage medium stores at least one instruction, and reads and executes the instruction to implement the multifunctional DMA transfer method.
Compared with the prior art, the technical scheme provided by the embodiment of the invention has the following advantages:
in the invention, the DMA controller is controlled to execute different data processing strategies by the DMA descriptor containing different mode parameters; when the mode parameter of the DMA descriptor is a first mode, the DMA controller transmits the data of the source address to the destination address to realize data transfer; when the mode parameter of the DMA descriptor is a second mode, the DMA controller repeatedly transmits the data pattern to the destination address to realize the setting of the data pattern; when the mode parameter of the DMA descriptor is a third mode, the DMA controller calculates the CRC of the appointed data to realize the calculation of the CRC of the data; and when the mode parameter of the DMA descriptor is in a fourth mode, the DMA controller transmits the cache data in the cache indicated by the source cache region ID to the cache indicated by the destination cache region ID, so as to realize data transmission between the caches. Finally, the DMA transfer with multiple functions is realized based on the DMA descriptor containing different mode parameters.
The CPU supports at least four descriptor registers, the CPU respectively configures DMA descriptor parameters containing four mode parameters through four different descriptor registers, and the CPU can configure the DMA descriptor parameters in parallel, thereby improving the DMA transmission efficiency.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a flowchart of a multifunctional DMA transfer method according to an embodiment of the present invention;
fig. 2 is a flowchart for acquiring a mode parameter in a DMA descriptor and determining a data processing policy according to a type of the mode parameter according to an embodiment of the present invention;
FIG. 3 is a diagram of a transmission apparatus for implementing a multifunctional DMA according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a first configuration module and a second configuration module according to an embodiment of the present invention;
FIG. 5 is a diagram of a descriptor management module according to an embodiment of the present invention;
fig. 6 is a schematic diagram of an execution module according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Example 1
Referring to fig. 1, an embodiment of the present invention provides a method for transmitting a multifunctional DMA, including:
s100, a CPU configures corresponding DMA descriptor parameters in a descriptor register according to DMA service requirements, wherein the DMA descriptor parameters comprise mode parameters, and the mode parameters comprise a first mode, a second mode, a third mode and a fourth mode; in a specific implementation process, referring to fig. 4, the CPU supports at least four descriptor registers, and supports parallel configuration of DMA descriptor parameters including four mode parameters through four different descriptor registers.
In a specific implementation process, the DMA descriptor parameters including the first mode further include: source address, destination address, and transmission data length.
The DMA descriptor parameters including the second mode further include: the data pattern comprises a data pattern, a data pattern length and a destination address, wherein the data pattern is set data needing to be written into the destination address, and the data pattern length is the length of specified data.
The DMA descriptor parameters including the third mode further include: source address, data length and CRC initial value;
the DMA descriptor parameters containing the fourth mode also include the source buffer ID and the destination buffer ID.
S200, the DMA controller acquires the DMA descriptor parameter from the descriptor register to form a DMA descriptor. In a specific implementation process, the DMA descriptor includes 128 bits, and the mode parameter, the source address, the destination address and the transmission data length, the data pattern length and the destination address, the source address, the data length and the CRC initial value, and the source buffer ID and the destination buffer ID are configured in the 128-bit DMA descriptor through a preset format.
S300, the DMA controller arbitrates and selects a DMA channel for data processing, and obtains a DMA descriptor of the corresponding channel.
In a specific implementation process, asynchronous design is adopted for processes of configuring DMA descriptor parameters by the CPU in step S100, step S200 and step S300 to form DMA descriptors and obtaining the DMA descriptors by the DMA controller, specifically, a DMA descriptor cache is constructed, the DMA descriptors configured by the CPU are stored in the DMA descriptor cache, the DMA controller obtains the required DMA descriptors from the DMA descriptor cache to control execution of corresponding data processing strategies, and the two processes are independent of each other. The descriptor cache address created is specified by a register in the DMA controller.
S400, obtaining a mode parameter in the DMA descriptor, and determining a data processing strategy according to the type of the mode parameter; in a specific implementation process, referring to fig. 2, the obtaining the mode parameter in the DMA descriptor and determining the data processing policy according to the type of the mode parameter includes:
s401, obtaining a DMA descriptor internal mode parameter, and detecting the type of the mode parameter in the DMA descriptor;
s402, if the mode parameter in the DMA descriptor is detected to be the first mode, the DMA controller forms a first data processing strategy to execute.
S403, if the mode parameter in the DMA descriptor is detected to be the second mode, the DMA controller forms a second data processing strategy to execute.
S404, if the mode parameter in the DMA descriptor is detected to be the third mode, the DMA controller forms a third data processing strategy to execute.
S405, if the DMA descriptor internal mode parameter is detected to be the fourth mode, the DMA controller forms a fourth data processing strategy to execute.
And S500, substituting other parameters in the DMA descriptor into a preset data processing strategy corresponding to the mode parameters for execution.
Specifically, the first data processing strategy acquires data to be transmitted according to a source address and a data transmission length in the DMA descriptor, fragments the data to be transmitted according to the transmission capacity of the burst mode, writes the data to be transmitted to a destination address according to the fragments, and returns a completion flag when data transmission is completed.
And the second data processing strategy divides the data pattern appointed in the DMA descriptor into slices according to the transmission capacity of the burst mode, repeatedly writes the content with the data pattern into an appointed destination address range according to the slices, wherein the length of the destination address range is integral multiple of the length of the data pattern, and returns an execution completion mark after the data pattern is set.
The third data processing strategy confirms the data of the CRC to be calculated according to the source address and the data length, reads the data of the CRC to be calculated according to the transmission capacity fragmentation according to the burst mode, calculates the CRC by using the initial value of the CRC, and returns the CRC when the calculation is finished;
and the fourth data processing strategy respectively converts the source buffer area ID and the destination buffer area ID in the DMA descriptor into a source cache address and a destination cache address, acquires the data to be transmitted from the source cache address, divides the data to be transmitted into fragments according to the transmission capacity of a burst mode, writes the data to be transmitted into the destination cache address according to the fragments, and returns a completion mark when the completion is completed.
In a specific implementation process, each DMA descriptor comprises a DMA descriptor ID, the result feedback information of the completion flag and the CRC check code comprises the DMA descriptor ID, and the DMA descriptor ID indicates the DMA descriptor corresponding to the data processing strategy for completing data transmission or CRC check code calculation.
The CPU configures the transmission capacity of the burst mode through a burst mode transmission capacity register according to the memory bit width or the bus bit width; the DMA controller acquires the transmission capacity of the burst mode from the burst mode transmission capacity register to perform fragmentation processing on the data.
Example 2
Referring to fig. 3, an embodiment of the present invention provides an apparatus for implementing multifunctional DMA transfer, including:
the first configuration module is used for configuring DMA descriptor parameters of the DMA descriptors according to DMA service requirements;
a second configuration module to configure a data capacity of a burst mode;
specifically, referring to fig. 4, the first configuration module includes a CPU and a descriptor register, and the second configuration module includes a CPU and a burst mode transmission capacity register. And the CPU configures corresponding DMA descriptor parameters in the descriptor register according to the DMA service requirements, and configures the data capacity of the burst mode according to the memory bit width or the bus bit width, wherein the data capacity of the burst mode does not exceed the memory bit width and the bus bit width.
The descriptor management module is used for constructing a DMA descriptor cache, updating DMA descriptor parameters configured by the CPU to form DMA descriptors, writing the DMA descriptors into the DMA descriptor cache, and acquiring the DMA descriptors of corresponding channels from the DMA descriptor cache; specifically, referring to fig. 5, the descriptor management module includes a descriptor management unit and a DMA descriptor cache, the descriptor management unit forms a corresponding DMA descriptor by using the DMA descriptor parameter configured by the first configuration module, and stores the DMA descriptor in the DMA descriptor cache, and the descriptor management unit obtains the corresponding DMA descriptor from the DMA descriptor cache to the execution module.
And the execution module forms a corresponding data processing strategy execution according to the DMA descriptor provided by the descriptor management module, feeds back the data processing strategy execution result to the descriptor management module, deletes the completed DMA descriptor according to the execution result, and stores a new DMA descriptor in the cleared DMA descriptor cache space.
Specifically, referring to fig. 6, the execution module includes a data processing policy selection configuration unit, where the data processing side path selection configuration unit configures, according to the DMA descriptor, a corresponding first data processing policy, a corresponding second data processing policy, a corresponding third data processing policy, and a corresponding fourth data processing policy, the data processing policy execution unit asynchronously executes each data processing policy, the data processing policy execution unit communicates with the read channel and the write channel, and the data processing policy execution unit is connected to the first cache unit, the second cache unit, the third cache unit, and the fourth cache unit. The data processing strategy execution unit is connected with the descriptor management module and feeds back a data processing strategy execution result to the descriptor management module.
Specifically, the data processing policy executing unit is used for asynchronizing the processes of acquiring data through a read channel and outputting data through a write channel in the first data processing policy and the fourth data processing policy; in the second data processing strategy, the processes of acquiring the data pattern and outputting the data pattern through the writing channel are asynchronous; and in the third data processing strategy, the process of acquiring the data to be CRC through the read channel is asynchronous with the process of CRC. And the asynchronous process of the data processing strategy execution unit is supported by the first cache unit, the fourth cache unit, the second cache unit and the third cache unit respectively.
The execution module monitors the states of the read channel and the write channel through the DMA channel management unit, selects the DMA channel executing the data processing strategy according to the state arbitration, and informs the descriptor management module, and the descriptor management module selects the corresponding DMA descriptor and feeds the descriptor back to the DMA channel management unit.
Example 3
The embodiment of the invention provides a storage medium for realizing a transmission method of a multifunctional DMA, wherein the storage medium for realizing the transmission method of the multifunctional DMA stores at least one instruction, and reads and executes the instruction to realize the transmission method of the multifunctional DMA.
In the invention, the DMA controller is controlled to execute different data processing strategies by the DMA descriptor containing different mode parameters; when the mode parameter of the DMA descriptor is a first mode, the DMA controller transmits the data of the source address to the destination address to realize data transfer; when the mode parameter of the DMA descriptor is a second mode, the DMA controller repeatedly transmits the data pattern to the destination address to realize the setting of the data pattern; when the mode parameter of the DMA descriptor is a third mode, the DMA controller calculates the CRC of the appointed data to realize the calculation of the CRC of the data; and when the mode parameter of the DMA descriptor is in a fourth mode, the DMA controller transmits the cache data in the cache indicated by the source cache region ID to the cache indicated by the destination cache region ID, so as to realize data transmission between the caches. Finally, the DMA transfer with multiple functions is realized based on the DMA descriptor containing different mode parameters.
The CPU supports at least four descriptor registers, the CPU respectively configures DMA descriptor parameters containing four mode parameters through four different descriptor registers, and the CPU can configure the DMA descriptor parameters in parallel, thereby improving the DMA transmission efficiency.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A transmission method of a multifunctional DMA (direct memory access), comprising the following steps: the CPU configures corresponding DMA descriptor parameters in a descriptor register according to DMA service requirements, wherein the DMA descriptor parameters comprise mode parameters, and the mode parameters comprise a first mode, a second mode, a third mode and a fourth mode;
the DMA controller acquires DMA descriptor parameters from the descriptor register to form a DMA descriptor;
the DMA controller arbitrates and selects a DMA channel for data processing, and obtains a DMA descriptor of the corresponding channel;
obtaining a mode parameter in a DMA descriptor, and determining a data processing strategy according to the type of the mode parameter; and substituting other parameters in the DMA descriptor into a preset data processing strategy corresponding to the mode parameter for execution.
2. The method of claim 1, wherein the CPU supports at least four descriptor registers, and the CPU configures the DMA descriptor parameters including four mode parameters through four different descriptor registers, respectively.
3. The method for transferring a multifunctional DMA according to claim 1, wherein the DMA descriptor parameter including the first mode further includes: source address, destination address and transmission data length; the DMA descriptor parameters including the second mode further include: data pattern, data pattern length, and destination address; the DMA descriptor parameters including the third mode further include: source address, data length and CRC initial value; the DMA descriptor parameters containing the fourth mode also include the source buffer ID and the destination buffer ID.
4. The method for transferring a multifunctional DMA according to claim 1, wherein the process of the CPU configuring DMA descriptor parameters to form DMA descriptors and the process of the DMA controller acquiring DMA descriptors adopt asynchronous design, a DMA descriptor cache is constructed, the DMA descriptors configured by the CPU are stored in the DMA descriptor cache, and the DMA controller acquires the required DMA descriptors from the DMA descriptor cache to control the execution of the corresponding data processing strategies.
5. The method for transferring multifunctional DMA according to claim 1, wherein the obtaining of the mode parameter in the DMA descriptor and the determining of the data processing policy according to the type of the mode parameter comprises:
obtaining a mode parameter in a DMA descriptor, and detecting the type of the mode parameter;
if the mode parameter in the DMA descriptor is the first mode, the DMA controller forms a first data processing policy enforcement,
if the mode parameter in the DMA descriptor is the second mode, the DMA controller forms a second data processing strategy execution,
if the mode parameter in the DMA descriptor is a third mode, the DMA controller forms a third data processing policy implementation,
and if the mode parameter in the DMA descriptor is the fourth mode, the DMA controller forms a fourth data processing strategy to execute.
6. The method according to claim 5, wherein the first data processing policy obtains data to be transmitted according to a source address and a data transmission length, and fragments the data to be transmitted according to a transmission capacity of a burst mode, writes the data to be transmitted to a destination address according to the fragments, and when the completion is completed, returns a completion flag;
the second data processing strategy divides the appointed data pattern into pieces according to the transmission capacity of the burst mode, repeatedly writes the content with the data pattern into an appointed destination address range according to the pieces, and returns a completion mark when the length of the destination address range is the integral completion of the length of the data pattern;
the third data processing strategy confirms the data of the CRC to be calculated according to the source address and the data length, reads the data of the CRC to be calculated according to the transmission capacity fragmentation according to the burst mode, calculates the CRC by using the initial value of the CRC, and returns the CRC when the calculation is finished;
and the fourth data processing strategy respectively converts the source buffer area ID and the destination buffer area ID into a source cache address and a destination cache address, acquires the data to be transmitted from the source cache address, divides the data to be transmitted into fragments according to the transmission capacity of a burst mode, writes the data to be transmitted into the destination cache address according to the fragments, and returns a completion mark when the completion is finished.
7. The method for transferring a multifunctional DMA according to claim 6, wherein each DMA descriptor includes a DMA descriptor ID, the result feedback information of the completion flag and the CRC check code includes the DMA descriptor ID, and the DMA descriptor ID indicates the DMA descriptor corresponding to the completed data processing policy.
8. The method for transferring multifunctional DMA according to claim 1, wherein the CPU configures the transfer capacity of the burst mode through the burst mode transfer capacity register according to the memory bit width or the bus bit width; the DMA controller acquires the transmission capacity of the burst mode from the burst mode transmission capacity register to perform fragmentation processing on the data.
9. An apparatus for implementing a multifunctional DMA transfer, comprising: the first configuration module is used for configuring DMA descriptor parameters of the DMA descriptors according to DMA service requirements;
a second configuration module to configure a data capacity of a burst mode;
the descriptor management module is used for constructing a DMA descriptor cache, updating DMA descriptor parameters configured by the CPU to form DMA descriptors, writing the DMA descriptors into the DMA descriptor cache, and acquiring the DMA descriptors of corresponding channels from the DMA descriptor cache;
and the execution module forms a corresponding data processing strategy execution according to the DMA descriptor provided by the descriptor management module, feeds back the execution result of the data processing strategy to the descriptor management module, and deletes the completed DMA descriptor according to the execution result.
10. A storage medium for implementing a transfer method of a multifunctional DMA, the storage medium storing at least one instruction, the instruction being read and executed to implement the transfer method of a multifunctional DMA according to any one of claims 1 to 8.
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| CN109766296A (en) * | 2019-01-08 | 2019-05-17 | 郑州云海信息技术有限公司 | A kind of data processing method, device, system and dma controller |
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| CN115563038A (en) * | 2022-10-24 | 2023-01-03 | 苏州雄立科技有限公司 | Data processing system, method and data processing equipment based on DMA controller |
| CN115563038B (en) * | 2022-10-24 | 2023-11-07 | 苏州雄立科技有限公司 | Data processing system, method and data processing equipment based on DMA controller |
| CN115422101A (en) * | 2022-11-04 | 2022-12-02 | 山东云海国创云计算装备产业创新中心有限公司 | DMA driving system, method, equipment and readable storage medium |
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