CN115114042A - Storage data access method and device, electronic equipment and storage medium - Google Patents

Abstract

The application discloses a storage data access method, a storage data access device, electronic equipment and a storage medium, and belongs to the technical field of computers. The storage data access method is applied to a first functional core in a many-core system, the many-core system comprises a plurality of functional cores, and the method comprises the following steps: receiving a first write-back request, wherein the first write-back request carries a first target global address of data to be written back; determining a target storage space pointed to by the first target global address; when the target storage space is in an unlocked state, setting the target storage space to be in a locked state until the data to be written back is successfully written back; wherein the target storage space is located in the first functional core, and in the locked state, access requests other than the first writeback request to the target storage space are denied. The method and the device can improve the operating efficiency of the many-core system.

Description

Storage data access method, device, electronic device and storage medium

technical field

The present application belongs to the field of computer technology, and specifically relates to a method, apparatus, electronic device and storage medium for accessing stored data.

Background technique

Many-core systems have multiple functional cores. In the related art, when multiple functional cores in a many-core system need to access the same stored data, there is a problem of data delay, so that the operation efficiency of the many-core system is low.

SUMMARY OF THE INVENTION

The purpose of the embodiments of the present application is to provide a storage data access method, apparatus, electronic device and storage medium, which can solve the problem of low operation efficiency of many-core systems caused by data delay in the storage data access method in the related art.

In order to solve the above technical problems, this application is implemented as follows:

In a first aspect, an embodiment of the present application provides a method for accessing stored data, which is applied to a first functional core in a many-core system, and the method includes:

receiving a first write-back request, wherein the first write-back request carries the first target global address of the data to be written back;

determining the target storage space pointed to by the first target global address;

When the target storage space is in an unlocked state, set the target storage space to a locked state until the data to be written back is successfully written back;

The target storage space is located in the first functional core, and in the locked state, access requests to the target storage space other than the first write-back request are rejected.

In a second aspect, an embodiment of the present application provides a storage data access device, which is applied to a first functional core in a many-core system, and the device includes:

a first receiving module, configured to receive a first write-back request, wherein the first write-back request carries the first target global address of the data to be written back;

a first determining module, configured to determine the target storage space pointed to by the first target global address;

a setting module, configured to set the target storage space to a locked state when the target storage space is in an unlocked state, until the data to be written back is successfully written back;

The target storage space is located in the first functional core, and in the locked state, access requests to the target storage space other than the first write-back request are rejected.

In a third aspect, embodiments of the present application provide an electronic device, the electronic device includes a processor, a memory, and a program or instruction stored on the memory and executable on the processor, the program or instruction being The processor implements the steps of the method according to the first aspect when executed.

In a fourth aspect, an embodiment of the present application provides a readable storage medium, where a program or an instruction is stored on the readable storage medium, and when the program or instruction is executed by a processor, the steps of the method according to the first aspect are implemented .

In a fifth aspect, an embodiment of the present application provides a chip, the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is configured to run a program or an instruction, and implement the first aspect the method described.

In this embodiment of the present application, the first functional core receives a first write-back request, wherein the first write-back request carries a first target global address of data to be written back; and the target pointed to by the first target global address is determined storage space; when the target storage space is in an unlocked state, set the target storage space to a locked state until the data to be written back is successfully written back; wherein, the target storage space is located in the first function In the core, in the locked state, access requests to the target storage space other than the first writeback request are denied. In this way, the private storage space in the first functional core can be used as a shared storage space to be accessed by the second functional core and write data, and then different shared data can be scattered and stored in the private storage space of different functional cores In this way, the problem of long waiting time and uncertain waiting time when multiple functional cores access the global shared storage space caused by storing a large amount of shared data in the global shared storage space is avoided, which improves the many-core system. operating efficiency.

Description of drawings

1 is a flowchart of a method for accessing stored data provided by an embodiment of the present application;

2 is a schematic diagram of data interaction of a remote access write-back processing unit capable of applying a method for accessing stored data provided by an embodiment of the present application;

3 is a schematic diagram of data interaction between a first functional core and a second functional core in a method for accessing stored data provided by an embodiment of the present application;

4 is a schematic diagram of data interaction in a first functional core in a method for accessing stored data provided by an embodiment of the present application;

5 is a schematic diagram of data interaction of a dual-mode memory interface to which a storage data access method provided by an embodiment of the present application can be applied;

6 is a structural diagram of a storage data access device provided by an embodiment of the present application;

FIG. 7 is a structural diagram of an electronic device provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

The terms "first", "second" and the like in the description and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances so that the embodiments of the present application can be practiced in sequences other than those illustrated or described herein, and distinguish between "first", "second", etc. The objects are usually of one type, and the number of objects is not limited. For example, the first object may be one or more than one. In addition, "and/or" in the description and claims indicates at least one of the connected objects, and the character "/" generally indicates that the associated objects are in an "or" relationship.

In a many-core system, the smallest unit with complete computing power that can be independently scheduled is called a functional core (referred to as "core"), and each functional core has its own storage and computing resources. Multiple functional cores are included in the same many-core system. And each functional core may need to perform calculations based on shared data. In the related art, the following two ways can be used to realize that multiple functional cores obtain the same shared data:

The first method is to set a global shared storage space. The global shared storage space is set outside the functional core, and can be set outside the chip where the functional core is located. In applications, when the functional core needs to obtain target data from the global shared storage space , send a read request to the global shared storage space through the shared memory bus, and transmit the target data through the shared memory bus. During this process, if other functional cores also need to access the global shared storage space, they need to wait for this functional core. After successfully acquiring the above target data, it can respond to the read requests of other functional cores.

Similarly, when multiple functional cores need to update the data in the global shared storage space, they also need to send a write-back request to the global shared storage space through the shared memory bus, and transmit the data to be updated through the shared memory bus. In this process, at the same time, the global shared storage space can only respond to the write-back request of one functional core, and other functional cores also need to wait.

It can be seen from the above that in the application scenario where multiple functional cores access the global shared storage space at the same time, it is necessary to determine a core to obtain the right to use through competition arbitration, so that a core that has obtained the right to use the global shared storage space through the shared memory bus. To obtain storage data, other cores that have not obtained the right to use will need to continue to wait, so that it takes a long time for the core to access the global shared storage space. In addition, data needs to be transmitted between the functional core and the global shared storage space through the shared memory bus, and the data delay time is not fixed or even unpredictable, which easily causes congestion of the shared memory bus and significantly reduces the many-core system. operation efficiency.

Method 2: Copy the shared data into the private storage space of each functional core that needs to use the shared data. Since the private storage space is only used by this functional core, external functional cores cannot access the private space of other functional cores. In implementation, when the shared data needs to be updated, the shared data to be updated needs to be written to each private storage space where the data is stored, that is, multiple functional cores respectively perform write-back operations to the local private storage.

As can be seen from the above, in this embodiment, when running an algorithm with shared data (such as a large neural network), the shared data needs to be copied to the private memory of each functional core and updated respectively, which is a waste of resources. In the application scenarios of large arrays or large shared data, private memory cannot meet the requirements of storage and operation efficiency, thus limiting the application scope of many-core systems.

In order to solve the above technical problems, the embodiment of the present application converts the global address and the corresponding private address, so that the external functional core can access the private storage space of other functional cores through the global address, and write data back to the private storage space. , to update the data stored in this private storage space. In this way, on the one hand, it can avoid copying the shared data into the private memory of each core, so as to reduce the waste of resources and improve the application scope of the many-core system; Many-core system operating efficiency.

The storage data access method, storage data access device, electronic device, and readable storage medium provided by the embodiments of the present application will be described in detail below with reference to the accompanying drawings through specific embodiments and application scenarios thereof.

Please refer to FIG. 1 , which is a flowchart of a method for accessing stored data provided by an embodiment of the present application. The method for accessing stored data can be applied to the first functional core in a many-core system. As shown in FIG. 1 , the method for accessing stored data The following steps can be included:

Step 101: Receive a first write-back request, wherein the first write-back request carries a first target global address of data to be written back.

Step 102: Determine the target storage space pointed to by the first target global address.

Step 103: When the target storage space is in an unlocked state, set the target storage space to a locked state until the data to be written back is successfully written back; wherein, the target storage space is located in the first function. In the core, in the locked state, access requests to the target storage space other than the first writeback request are denied.

In implementation, the above-mentioned functional cores may also be referred to as "cores" or "cores". The functional cores are the smallest units in the many-core system that can be independently scheduled and have complete computing capabilities, and each functional core has respective storage computing resources, and the private storage spaces in each functional core have the same private address, for example: the number of private storage spaces of the first functional core is N, and the N storage space identifiers in the first functional core are respectively is 0 to N-1, the number of private storage spaces of the second functional core is also N, and the identifiers of the N storage spaces in the second functional core are also respectively 0 to N-1.

The above-mentioned global address is unique in the many-core system, and it can point to the target private storage space located in the target functional core in the many-core system, for example: the global address is the core identifier of the first functional core and the first functional core. A combination of storage space identifiers for the target storage space in the core.

In practical applications, a functional core may include multiple storage spaces, so that the multiple storage spaces in the functional core can be in different states, for example, part of the storage space is in a locked state, and another part is in an unlocked state. This part of the storage space in the locked state can still be accessed.

As an optional implementation manner, the first writeback request includes at least one of the following:

a write-back request sent by the first data path of the first functional core;

A writeback request sent by the second functional core;

Wherein, the second functional core is a functional core different from the first functional core in the many-core system.

The above-mentioned second functional core can be understood as any functional core other than the first functional core in the many-core system, that is, an external functional core of the first functional core, and the number of the second functional core can be one Can also be more than one.

The write-back request sent by the first data path of the first functional core can be understood as: the first functional core uses the global address to update the data stored in the first functional core.

It should be noted that, in practical applications, the first functional core can also directly use the private address to privately access the data stored in the first functional core to update the data stored in the private address in the first functional core. This is not specifically limited.

In addition, the write-back request sent by the second functional core can be understood as: the external functional core uses the global address to globally access the data stored in the first functional core, so as to update the data stored in the first functional core and the global address The data of the corresponding private address.

In implementation, the same storage space in the first functional core can only respond to one of global access and private access at the same time, for example, the storage space can be switched to be in the first working mode (which Also referred to as "global mode") and/or in a second working mode (which may also be referred to as "private mode"). Wherein, in the first working mode, the global address in the received access request is converted into a private address, so as to access the data in the target storage space based on the private address (that is, in this working mode, only responding to The global access to the target storage space, and the response can be refused for private access); in the second working mode, the data in the target storage space is accessed based on the private address in the received access request (that is, in this working mode Respond only to private access to the target storage space, and can deny the response for global access).

In addition, the private storage space (that is, the memory slice) of the first functional core may include one or more, wherein, if there are multiple private storage spaces (that is, the memory slice) of the first functional core, it may be a part of the private storage space (that is, the memory slice). The private storage space works in the private mode, and the other part works in the global mode, wherein the private storage space in the private mode is only accessible by the first functional core, and the private storage space in the global mode is only accessible by the first functional core. Two functional core access.

The above-mentioned setting the target storage space to a locked state until the data to be written back is successfully written back can be specifically: setting the target storage space to a locked state to deny subsequent received accesses to the target storage space, and to start Write the data to be written back into the target storage space, and when the data to be written back has been written to the target storage space, release the locked state of the target storage space, so that the function core can access the target storage space from the The storage space obtains the updated data.

The refusal of subsequent received access to the target storage space may be: the function core and external function cores other than the first function core, access the memory area corresponding to the first target global address in the target storage space. Otherwise, the subsequent received access to the target storage space is rejected, and it can also be: during the lock-up period, the function core and the external function core other than the first function core, the target storage space and the first function core The access to the memory area corresponding to the target global address will be stored in the request message queue, and the request in the request message queue will be processed after the write-back operation is completed, that is, the access request will be postponed until the lock state of the target storage space is released. implement.

As an optional embodiment, the method further includes:

When the target storage space is locked, perform at least one of the following operations:

rejecting the first writeback request;

The first write-back request is added to a message queue to respond to the first write-back request when the target storage space is switched to an unlocked state.

The above-mentioned response to the first write-back request may have the same meaning as step 103, which is not repeated here.

In addition, the above-mentioned target storage space is in a locked state, which can be understood as: other data to be written back is being written into the target storage space, that is, the data in the target storage space is being updated.

In this implementation manner, when the data in the target storage space is being updated, rejecting the first write-back request or waiting for the target storage space to switch to the unlocked state, and then responding to the first write-back request, can avoid The problem of data confusion caused by the target storage space responding to write-back requests or read requests of multiple functional cores at the same time can improve the data reliability of the storage data access method.

As an optional implementation manner, setting the target storage space to a locked state until the data to be written back is successfully written back includes:

Setting the target storage space to a locked state, and receiving the data to be written back;

updating the data in the target storage space according to the data to be written back;

After the update is completed, the locked state of the target storage space is released.

As an optional implementation manner, the determining of the target storage space pointed to by the first target global address includes:

According to the mapping relationship between the global address and the private address, determine the third private address corresponding to the first target global address;

A target storage space corresponding to the third private address in the first functional core is determined.

Wherein, the above-mentioned third private address indicates a start write address of the data to be written back in the private memory of the first functional core, so that the above-mentioned data to be written back is written back from the start address. In addition, setting the target storage space corresponding to the third private address to the locked state can be understood as setting the memory slice where the third private address is located to the locked state.

In this implementation manner, after converting the global address into a private address, the private memory of the first functional core is accessed by using the private address, so as to update the data in the private memory. Wherein, after converting the global address into a private address, using the private address to access the private memory of the first functional core is the same as the process of locally accessing the private memory of the functional core in the prior art, which will not be repeated here. The difference lies in that, in the embodiment of the present application, the external function core performs global access to the private memory of the function core through the global address.

It should be noted that in practical applications, there may be multiple write-back operations, and it is necessary to set resource locks on the memory areas targeted by each write-back operation, so that the memory areas are locked before the data update is completed. Down. At this time, a locked address space recording area may be set to record the memory area in a locked state in the locked address space recording area.

For example, the format of a record in the above-mentioned locked address space record area can be the format shown in Table 1 below:

Table 1

memory start address memory length Request a verification number Quantity updated Other Information

Wherein, the above-mentioned memory start address may indicate the start address of the data to be written back in the target storage space, the above-mentioned memory length may indicate the data length of the data to be written back, and the above-mentioned request core number may indicate the request to the destination The target storage space of the core writes the identifier of the functional core of the data to be written back, the above-mentioned updated quantity can indicate the length of the data that has been written into the target storage space in the above-mentioned data to be written back, and the above-mentioned other information can be used to add Additional information, etc.

In an implementation, the above-mentioned locked address space recording area may be located in the first functional core. During the process of writing data by the second functional core to the target storage space pointed to by the first target global address, the data to be written back can be sent to the first functional core in a time-sharing manner in the form of a data packet, and the data in the data packet is successfully After writing back to the target storage space, the updated quantity (in bytes (ie, bytes) as a unit) of the data to be written back in the record area of the locked address space will be updated. In this way, when the number of updates is consistent with the data length of the data to be written back, it is determined that the data to be written back has been written, and at this time, the locked state of the target storage space can be released, and the target storage space can be deleted in the locked address space recording area. The lock record of the space.

It should be noted that the first functional core may further include a memory area that is not in a locked state, and the memory area not in a locked state can be accessed by the first functional core or other functional cores.

Further, the first write-back request also carries the storage length of the data to be written back, and the updating of the data in the target storage space according to the data to be written back includes:

In the process of writing the data to be written back into the target storage space, obtain the length of the updated data in the target storage space;

When the length of the updated data in the target storage space matches the storage length of the data to be written back, it is determined that the update is completed.

In implementation, the first target global address may indicate the starting write address of the data to be written back, or, after the first target global address is converted into a corresponding first private address, the first private address indicates the data to be written back. Write back the starting write address of the data in the target memory space. At this time, the termination address of the data to be written back can be calculated according to the data length of the data to be written back and the first private address, and the write address of the data being written in the target storage space can be obtained in real time. Then, the length of the updated data in the target storage space matches the storage length of the data to be written back, which can be understood as: when the write address is consistent with the termination address of the data to be written back, it can be determined that the write address is to be written back. When the write-back of the data is completed, it is determined that the update is completed.

Of course, in actual use, the amount of data that has been written in the target storage space can also be obtained in real time through the counter. The matching of the storage lengths of the data can be understood as: when the data volume of the written data is the same as the data volume of the data to be written back, it can be determined that the data to be written back has been written back, that is, it is determined that the update is completed.

In this embodiment, whether the update is completed can be determined by comparing whether the length of the updated data in the target storage space matches the storage length of the data to be written back, so that the above target can be released as soon as possible when the update is completed. The lock status of the storage space.

As an optional implementation manner, the first writeback request is an access request initiated by a second functional core in the many-core system, and the method further includes:

Send notification signaling to the second functional core, where the notification signaling is used to notify the second functional core that the data to be written back is successfully written back.

In practical applications, when the second functional core does not receive the above notification signaling, the second functional core can re-send the write-back request to avoid the failure to write the data to be written back and the excessive writing delay. If the data to be written back fails to be written back in time due to the long or the write request being rejected, the second function check will mistakenly believe that the data to be written back has been written back, thereby improving the reliability of the stored data access method. .

The following takes the remote access write-back processing unit capable of applying the stored data access method provided by the embodiment of the present application as an example to illustrate the stored data access method provided by the embodiment of the present application:

As shown in FIG. 2 , the first functional core includes: a routing module 21 , a signaling buffer 22 , a data packet buffer 23 , a remote access writeback processing unit 24 and a memory area 25 , wherein the remote access writeback processing unit 24 includes : Lock the address space recording area 241 and the control logic 242 .

Specifically, the remote access write-back processing unit 24 is connected to the routing module 21 through the signaling buffer 22 and the data packet buffer 23 respectively. The DMA in the processing unit 24 is connected to the memory area 25 , and the control logic 242 in the remote access write-back processing unit 24 is connected to the locked address space recording area 241 and the memory area 25 respectively.

In a specific implementation, the control logic 242 is used to control operations such as query, update, addition and deletion of lock records in the lock address space record area 241. In addition, the control logic 242 receives a global access request from an external function core. When the destination address of the global access request is obtained by analysis, and whether the memory space corresponding to the destination address is in a locked state is queried from the locked address space recording area 241, if it is in a locked state, the global access request is rejected.

In implementation, the routing module 21 receives the write-back request signaling sent by the external functional core through the on-chip network, and the write-back request signaling is transmitted to the control logic 242 through the signaling buffer, and the control logic 242 sends the write-back request signal. The global address carried in the command is converted into a private address, and according to the information carried in the write-back request signaling and the usage of the storage space corresponding to the private address, it is judged whether to reject the write-back request signaling. In the case of rejecting the write-back request signaling, the global address carried in the write-back request signaling can be converted into a private address, and the memory space corresponding to the above-mentioned private address in the memory area 25 is set to a locked state, and then allow The data packets received from the on-chip network via the routing module 21 and the data packet buffer 23 are written into the storage space corresponding to the above-mentioned private address in the memory area 25 .

It should be noted that, in the implementation, a memory access (Direct Memory Access, DMA) subunit may be set between the data packet buffer 23 and the memory area 25, and the DMA subunit is controlled by the control logic 242 to control the When the logic unit 242 determines that the storage space of the data to be accessed is in an unlocked state based on the locked address space recording area 241, it controls the DMA subunit to be in a normal working state, that is, allows the functional core to access the memory area 25 and is in an unlocked state. Storage space; in addition, when the control logic 242 determines that the storage space of the data to be written back is in a locked state based on the locked address space recording area 241, the control DMA subunit is in a prohibited access working state, that is, the functional core is denied access to the memory area. 25 and locked storage space.

It should be noted that the direction of the arrow in the embodiment shown in FIG. 2 indicates the transmission direction of signaling or the data to be written back in the process of requesting the functional core to write the data to be written back into the first functional core.

As an optional implementation manner, before the receiving the first writeback request, the method further includes:

receiving a first read request, wherein the first read request carries a second target global address;

When it is determined that the target storage space indicated by the second target global address is located in the first functional core and the target storage space is not in a locked state, the second target storage space is determined according to the mapping relationship between the global address and the private address. The first private address corresponding to the target global address, and the first target data corresponding to the first private address in the target storage space is transmitted.

In application, any functional core in the many-core system can obtain data from the private memory (including the above-mentioned target storage space) of the first functional core based on the conversion between the global address and the private address, and perform calculation according to the data , so that after the calculation result is obtained, the data in the private memory of the first functional core can be updated according to the calculation result.

In other words, in this implementation manner, any functional core in the many-core system can read and update the data stored in the private memory of the first functional core based on the conversion between the global address and the private address, and can When the private memory of the first functional core is in a locked state, other access requests for accessing the private memory can be rejected, so as to avoid transmitting the data before the update or not completing the update during the process of updating the data in the private memory of the first functional core. data, thereby improving data reliability.

In the embodiment of the present application, in the process of updating the data in the private memory of the first functional core, the private memory of the first functional core is set to a locked state, so as to avoid some functions of the private memory in the process of updating the data in the private memory. The core obtains the data before the update or not completely updated from the private memory, thereby causing the problem of inconsistent data in the many-core system. Therefore, the storage data access method provided by the embodiment of the present application improves the operation efficiency of the many-core system. At the same time, it can also improve the data reliability of the many-core system.

As an optional implementation manner, the first read request, the first target data, the first write back request, and the data to be written back are transmitted through an on-chip network or an on-chip bus, and the many-core Any two functional cores in the system are connected through the on-chip network or on-chip bus.

For example, as shown in FIG. 3 , a communication connection is established between the requesting core 31 (ie the second functional core) and the destination core 32 (ie the first functional core) through the on-chip/inter-chip network 33, wherein the requesting core 31 specifically includes: The first private memory 311 , the first dual-mode memory interface 312 , the first route 313 and the data path 314 , and the destination core 32 specifically includes: the second private memory 321 , the second dual-mode memory interface 322 and the second route 323 . When the requesting core 31 needs to read the target data stored in the private memory 324 of the destination core 32, the data path 314 in the requesting core 31 sends the data to the on-chip/inter-chip network 33 through the second dual-mode memory interface 322 and the first route 313 The read request carries the core identifier of the requesting core 31 and the global address of the request to read the data, and the destination core 32 receives the read request from the on-chip/inter-chip network 33 through the second route 323. When recognizing that the core identifier in the read request is inconsistent with the core identifier of the destination core 32, the modulo memory interface 322 converts the global address in the read request into a private address, and stores the second private memory 321 in the private address. The destination data of the address is transmitted to the on-chip/inter-chip network 33 through the second route 323, so that the request core 31 obtains the target data from the on-chip/inter-chip network 33 through the first route 313, thereby realizing the request core 31 from the destination core 32. The private memory of the fetch target data.

It should be noted that the direction of the arrow in the embodiment shown in FIG. 3 represents the signaling or the transmission direction of the target data in the process that the request core 31 obtains the target data from the private memory 324 of the destination core 32 .

In this embodiment, the request signaling and data packets between the first functional cores are transmitted through the on-chip network or the on-chip bus, which can avoid waiting time when multiple second functional cores access the private memory of the first functional core at the same time. .

Of course, in specific implementation, any two functional cores in the many-core system may also be connected through other networks, such as a short-range communication network, etc., which are not specifically limited here.

In addition, in an optional implementation manner, when the number of the second functional cores is multiple, that is, when multiple external functional cores access the private storage space of the first functional core respectively, the first functional core A functional core may also respond to read requests of a plurality of second functional cores one by one.

In addition, the above-mentioned mapping relationship between the global address and the private address may be: a mapping table between the private address and the global address, and during operation, the private address corresponding to the global address is queried in the mapping table. Of course, the conversion relationship between the private address and the global address may also be pre-stored, so as to dynamically convert the global address into the corresponding private address during the running process.

Certainly, the above-mentioned mapping relationship between the global address and the private address may further include: a mapping relationship determined according to the conversion relationship between the global address and the private address.

As an optional implementation manner, the mapping relationship between the global address and the private address is determined in the following manner:

In the case where the many-core system includes S chips, the target functional core where the corresponding private address is located and the target chip where the target functional core is located are indicated based on each global address, so that the global address corresponding to each private address is address, to determine the mapping relationship;

or,

When the many-core system includes one chip, and the chip includes a functional core array arranged in J rows and P columns, each global address refers to the target functional core where the corresponding private address is located, and the target functional core. The position of the function core in the entire column of the function core is used to determine the mapping relationship according to the global address corresponding to each private address.

In an optional implementation manner, the target functional core where the corresponding private address is indicated based on each global address, and the target chip where the target functional core is located, so that according to the global address corresponding to each private address, Determining the mapping relationship can be understood as: the mapping relationship includes the conversion relationship between the global address and the private address, and the conversion relationship is based on the target function core where the private address is located, and the target chip where the target function core is located. to achieve the corresponding global address. In other words, it can also be understood as: the global address carries the corresponding private address, the identity of the functional core where the private address is located, and the identity of the chip where the functional core is located.

For example: when the many-core system includes S chips, the mapping relationship between the global address and the private address is determined by the following formula:

p=(qV+c)×N+k

Wherein, the p represents the global address, the k represents the private address, the c represents the identity of the functional core corresponding to the k, the q represents the identity of the chip where the functional core corresponding to the c is located, and the N represents The total number of private addresses in the functional cores corresponding to the k, and the V represents the total number of functional cores in each chip.

Of course, in the specific implementation, in addition to expressing the mapping relationship between the global address and the private address through the above formula, the private address, the chip identification and the function core identification can also be combined and arranged to form the global address. way to express the mapping relationship between global addresses and private addresses.

In another optional implementation manner, the based on each global address refers to the target function core where the corresponding private address is located, and the position of the target function core in the entire column of The global address corresponding to the address, and determining the mapping relationship, can be understood as: the global address carries the identifier of the function core where the corresponding private address is located, and the arrangement position of the function core in the function core array.

For example: when the many-core system includes one chip, and the chip includes a functional core array arranged in J rows and P columns, the mapping relationship between the global address and the private address is determined by the following formula:

p=(Px+y)×N+k

Wherein, the p represents the global address, the k represents the private address, the x represents the row identifier of the functional core corresponding to the k in the functional core array, and the y represents the functional core corresponding to the k in the The column identifier in the functional core array, and the N represents the total number of private addresses in the functional cores corresponding to the k.

Of course, in the specific implementation, in addition to expressing the mapping relationship between the global address and the private address through the above formula, the global address can also be expressed in a way of jointly forming the global address by arranging the private address and the chip location in combination. Mapping relationship with private addresses.

In this embodiment, the preset address is associated with the global address through the chip ID, the functional core ID, and the functional core location, etc., so that the global address can be associated with the private address in the application according to the chip ID, the functional core ID, and the functional core location. The mutual conversion is performed, thereby simplifying the process of determining the first private address corresponding to the second target global address.

As an optional embodiment, the method further includes:

Receive a second read request sent by a first data path, wherein the first data path is located in the first functional core, the second read request carries a second private address, and the second private address is located in the target storage space;

When it is determined that the target storage space is not in a locked state, second target data corresponding to the second private address in the target storage space is transmitted to the first data path.

This embodiment is applicable to an application scenario in which the first functional core reads data from the local private memory. At this time, as long as the target storage space indicated by the second private address is not in a locked state, the first functional core can directly send data to the local private memory. The memory sends a private address to access its private memory without sending the global address corresponding to the private address. In implementation, the second read request may also carry the identifier of the first functional core, so that the target storage space can be based on The identification of the first functional core determines that the second read request is a local access request, so as to identify the second private address instead of mistakenly considering the second private address as a global address.

For example, as shown in FIG. 4, the computing module in the first functional core 41 can send a read request to the private memory 413 of the first functional core through the dual-mode memory interface 412 through the data path 411, and the read request carries the target The private address of the data, so that the private memory 413 feeds back the target data stored in the private address to the computing module through the dual-mode memory interface 412 and the core data path 411 .

It should be noted that the direction of the arrow in the embodiment shown in FIG. 4 indicates the direction of signaling or the transmission of the target data in the process that the first functional core 41 obtains the target data from the private memory 413 of the functional core.

It should be noted that, in this embodiment, the first data path in the first functional core sends a second read request carrying a private address to the target storage space of the first functional core, so as to read from the target storage space The realization process of the data is the same as the process of reading data from the local private memory by the functional core in the prior art, and will not be described in detail here.

It should be noted that, in practical applications, the first functional core may include multiple memory slices, so that some memory slices in the first functional core may be accessed by this functional core, and other memory slices may be accessed by external functional cores. . However, the same memory slice can only respond to one of the local access request and the global access request (ie, the first read request) at the same time.

As an optional implementation manner, the working mode of the target storage space includes a first working mode and a second working mode;

Wherein, in the first working mode, reject the second read request to the target storage space until the first read request completes a response; in the second working mode, reject the target storage space the first read request of the storage space until the second read request completes the response;

The method also includes at least one of the following:

According to the control instruction, determine the working mode of the target storage space;

In response to the first read request, determining that the working mode is the first working mode;

In response to the second read request, it is determined that the operating mode is the second operating mode.

In one embodiment, the above-mentioned determination of the working mode of the target storage space according to the control instruction can be understood as: the working mode of the target storage space is determined according to the instruction of the preset control instruction, and is not affected by the received Impact of Access Requests.

In this implementation manner, the working mode of the target storage space can be adjusted through a preset control instruction, so as to control whether the data in the target storage space can be accessed only by this functional core or by other functional cores.

Case 1

When the memory of the functional core works in the global mode (ie, the first working mode), the memory can only be accessed globally by the external functional core, and the access of the functional core will be denied. In this global mode, the received read request carries the global address, which is recorded by the global address mapping table and is responsible for translating the global address to the private address, and finally uses the private address to access the memory.

It should be noted that, in the above global mode, the memory of all functional cores forms a large-capacity logical memory. When performing global access, there is no need to specify which core of which chip the accessed memory is located, and only the global address can be used to access. .

Case 2

In the case that the memory of the functional core works in the private mode (ie, the above-mentioned second working mode), the memory can only be accessed locally by the functional core, and the global access of the external functional core will be denied. In this private mode, the memory can only be accessed by the functional core, so the access latency is fixed and predictable.

In another implementation manner, in response to the first read request, it is determined that the working mode is the first working mode; in response to the second read request, it is determined that the working mode is the The second working mode can be understood as: whether to work in the first working mode or the second working mode is determined according to whether the received access request is a private request or a global request.

Specifically, rejecting the second read request to the target storage space until the first read request completes the response can be understood as: in the first working mode, only responding to the global access to the target storage space, And when all the global access responses are completed, you can switch to the second working mode to respond to the private access to the target storage space in the second working mode; or, when all the global access responses are completed, you can Respond directly to private access to the target storage space without going through a mode switch.

Correspondingly, the above-mentioned rejection of the first read request to the target storage space until the second read request completes the response can also be understood as: in the second working mode, only private access to the target storage space is performed. response, and when all the private access responses are completed, you can switch to the first working mode to respond to the global access to the target storage space in the first working mode; or, when all the private access responses are completed , you can directly respond to the global access of the target storage space without going through the mode switch.

In this implementation manner, the working mode of the target storage space can be determined according to the type of the received read request, so that it is convenient to switch the working mode of the target storage space according to different read requests, so that the target storage space and the received match the read request.

E.g:

After receiving the first read request carrying the global address, the method further includes:

In response to the first read request, the target storage space is set to a first working mode, wherein, in the first working mode, the target storage space rejects the access request of the first functional core, until the second read request completes the response;

After receiving the second read request carrying the private address, the method further includes:

In response to the second read request, the target storage space is set to a second working mode, wherein, in the second working mode, the target storage space rejects an access request from an external functional core until the The second read request completes the response.

It should be noted that if the target storage space receives both a local access request carrying a private address and a global access request carrying a global address at the same time, arbitration can also be used to give priority to the local access request and the global access request. one of the responses.

In other words, if other functional cores other than the first functional core in the many-core system need to acquire or write data to the private memory of the first functional core, the conditions that need to be met include: read requests sent by other functional cores. Or the write-back request carries a global address indicating the storage space to be accessed, the storage space to be accessed in the first functional core is in the first working mode, and the storage space to be accessed is in an unlocked state, the storage space to be accessed Indicates the storage space for data to be acquired or data to be updated.

When the first functional core needs to acquire or write data to the private memory of the functional core, the conditions to be satisfied include: the storage space to be accessed is in an unlocked state, and the storage space to be accessed indicates that the storage is to be acquired or updated. storage space for data; and, in the first working mode, the read request or write-back request sent by the first functional core carries a global address indicating the storage space to be accessed, or, in the second working mode, the first The read request or write back request sent by the functional core carries the private address indicating the storage space to be accessed.

As an optional implementation manner, when the time difference between the reception of the first read request and the second read request is less than a preset time, the first read request is determined through arbitration or a preset priority. At least one of the fetch request and the second read request is responded to.

Wherein, the preset time may be any length of time such as 0.1s (second), 1 second, etc., which is not specifically limited herein.

Wherein, determining the response to at least one of the first read request and the second read request based on the preset time can be understood as: pre-setting the priority of the first read request If it is set to be higher than the priority of the second read request, the first read request will be responded to first, and the second read request can be rejected, or the response to the first read request can be completed after the response of the first read request is completed. The second read request responds; in the case where the priority of the second read request is set to be greater than the priority of the first read request in advance, the second read request is given priority. In response, the first read request may be rejected, or the first read request may be responded to after the second read request response is completed.

Taking the target storage space including a dual-mode memory interface for switching the target storage space between the private mode and the global mode as an example, the response process of the above-mentioned local access request and the above-mentioned global access request is exemplified below:

In this embodiment, the many-core system includes: a first functional core, a second functional core, and an on-chip network 50 connecting the first functional core and the second functional core.

Wherein, as shown in FIG. 5 , the first functional core includes: a data path 51, a memory 52, a routing module 53 and a dual-mode memory interface 54, the routing module 53 is connected to the on-chip network 50; the dual-mode memory interface 54 includes a target location resolver 541 , a mode switcher 542 , an address mapping table storage module 543 , a request signaling packetizer 544 , a request signaling depacketizer 545 , a data packetizer 546 and a data depacketizer 547 .

Specifically, the target location parser 541 is connected to the data path 51, the memory 52 mode switch 542, the address mapping table storage module 543, the request signaling packetizer 544, the request signaling unpacker 545, the data packetizer 546 and the data packetizer 546. The depacketizers 547 are respectively connected, and the mode switcher 542, the address mapping table storage module 543, the request signaling packetizer 544, the request signaling depacketizer 545, the data packetizer 546, and the data depacketizer 547 are respectively connected to the router Module 53 is connected.

It should be noted that the structure of the second functional core may be the same as the structure of the first functional core, and details are not described herein again. In addition, the direction of the arrow in the embodiment shown in FIG. 5 indicates the transmission direction of signaling or target data in the process that the memory 52 of the first functional core is accessed locally or globally.

In one case, if the dual-mode memory interface 54 is in the private mode, the target location parser 541 directly accesses the memory 52 according to the private address provided by the data generating unit in the data path 51, that is, the second read request carries The private address of the target data, and the memory 52 directly outputs the returned data packet of the target data to the data path 51 .

In another case, if the dual-mode memory interface 54 is in the global mode, when the data path 51 sends a read request to the target location parser 541, the target location parser 541 is used to store the memory in the module 543 according to the address mapping table. The stored address mapping table determines whether the destination address in the read request sent by the data path 51 is located in this functional core or in other external functional cores, so as to determine whether the read request to be generated is a local access request or a global access request.

Wherein, if the destination address in the read request is located in the functional core, it is determined that the read request is a local access request, so that the memory 52 is directly accessed according to the private address in the local access request.

In addition, if the destination address in the read request is located in other external functional cores, it is determined that the read request is a global access request, and at this time, the target location resolver 541 sends the request location in the global access request to the requester The signaling packager 544 forms a global access request signaling package by the request signaling packager 544, and sends the global access request signaling package to the routing module 53, and the routing module 53 will send the request signaling package from the request signaling package. The global access request signaling packet received by the packetizer 544 is sent to the on-chip network 50, so as to send the global access request signaling packet to the storage location of the data to be read through the on-chip network 50, so that the destination of the storage location is located. When the function core returns a data packet in response to the global access request signaling packet, the routing module 53 receives the returned data packet from the network-on-chip 50, and the data unpacker 547 unpacks the data packet to obtain the target data (ie The data to be read by this functional core), and then the target location parser 541 also parses the target data, and sends the target data to the memory 52 or the data path 51 according to the parsed information.

At the same time, the routing module 53 is also responsible for receiving the global access request signaling packet sent by the external functional core to the functional core from the network-on-chip 50, and the request signaling unpacker 545 unpacks the global access request signaling packet, so as to Obtain information such as the global address and data length of the global access request signaling packet. And send this information to the target location parser 541 . In this way, the target location resolver 541 will translate the global address of the global access request into a private address, so as to access the memory 52 through the private address, and return the access result (ie, target data) of the memory 52 to the data packetizer 546, After the target data is formed into a data packet by the data packetizer 546, it is sent to the on-chip network 50 through the routing module 53. At this time, the requester of the target data will receive the data packet of the target data from the on-chip network 50. Specifically, In the requester of the target data, the data packets received by the routing module are unpacked in the data unpacker, and the relevant data packets are sent to the target location parser. The parsed information sends the data in the data packet to the memory or data path. The requester of the target data processes the received target data the same as the processing process of this functional core after receiving the data packet. Repeat.

In implementation, the format of the above request signaling packet may be as shown in Table 2 below:

Table 2

Wherein, the signaling identifier is used to distinguish different signaling; the target functional core address is used to indicate the address of the functional core where the memory storing the data to be accessed is located; the data starting global address represents the starting global address of the data to be accessed, the The starting global address plus the above data length can represent the ending global address of the data to be accessed; in the case where the storage space where the data to be accessed is accessed by multiple functional cores at the same time, the target location parser can arbitrate based on the above priority , to determine the response to the access request signaling with the highest priority; additional information can be added through the above additional information field.

It should be noted that the arrangement position of each sub-signal in the above-mentioned request signaling packet can be exchanged, and may also include other than the above-mentioned signaling identifier, target function core address, data starting global address, priority and additional information fields. Other sub-information is not exhaustive here.

In addition, in implementation, the format of the above data packet may be as shown in Table 3 below:

table 3

Wherein, the above-mentioned data packet identifier is used to distinguish different data packets; the above-mentioned data body represents the specific data (that is, the data to be accessed) in the data packet; in addition, the above-mentioned target function core address, data starting global address, data length and additional For the specific meanings of the information fields, refer to the specific meanings of the target function core address, data starting global address, data length and additional information fields in the request signaling packet format shown in Table 2 above, which will not be repeated here.

In the related art, when there is a set of weights to be used for many pictures, the pictures are respectively input into multiple function cores for processing respectively. In application, since this set of weights needs to be used for many function cores, The private memory of each functional core can only be accessed by this functional core, so the entire set of weights must be stored in all functional cores that need to use the weights, so as to process pictures layer by layer.

In the embodiment of the present application, the set of weights may be stored in only one or a few functional cores (for example, only each weight value in the set of weights is stored in the functional cores that need to use the weight value respectively. , instead of having the function core store the entire set of weights), when a function core needs to use an unstored weight value, it can obtain it from other function cores that store the weight value through global access.

As can be seen from the above, through the storage data access method provided by the embodiments of the present application, when running an algorithm with shared data (such as a large-scale neural network), there is no need to copy the shared data into the private memory of each functional core, and it is possible to Reduce resource waste and make many-core systems with large arrays and shared data more widely applicable, supporting both high-speed and sparse modes. In addition, unlike the shared data in the prior art, which needs to be transmitted through a shared memory center line, in the embodiment of the present application, the signaling and data of global access are transmitted through the on-chip network, on-chip bus or inter-chip network, which can reduce signaling and data. The waiting time of data transmission can improve the operation efficiency of the many-core system.

In this embodiment of the present application, the first functional core receives a first write-back request sent by the second functional core, where the first write-back request carries the first target global address of the data to be written back; in response to the The first write-back request sets the target storage space pointed to by the first target global address to a locked state until the data to be written back is successfully written back, wherein the target storage space is located in the first functional core , in the locked state, the target storage space denies access by functional cores other than the second functional core, and in the unlocked state, the target storage space can be accessed by any function in the many-core system nuclear access. In this way, the private storage space in the first functional core can be used as a shared storage space to be accessed by the second functional core and write data, and then different shared data can be scattered and stored in the private storage space of different functional cores In this way, the problem of long waiting time and uncertain waiting time when multiple functional cores access the global shared storage space caused by storing a large amount of shared data in the global shared storage space is avoided, which improves the many-core system. operating efficiency.

It should be noted that, in the stored data access method provided by the embodiments of the present application, the execution subject may be a stored data access device, or a control module in the stored data access device for executing the stored data access method. In the embodiment of the present application, the storage data access device provided by the embodiment of the present application is described by taking the storage data access device executing the load storage data access method as an example.

Please refer to FIG. 6 , which is a structural diagram of a storage data access device provided by an embodiment of the present application. The storage data access device 600 is applied to the first functional core in a many-core system. As shown in FIG. 6 , the storage data access device 600 Apparatus 600 includes:

a first receiving module 601, configured to receive a first write-back request, wherein the first write-back request carries a first target global address of data to be written back;

a first determining module 602, configured to determine the target storage space pointed to by the first target global address;

A setting module 603, configured to set the target storage space to a locked state when the target storage space is in an unlocked state, until the data to be written back is successfully written back; wherein, the target storage space is located in the In the first functional core, in the locked state, access requests to the target storage space other than the first write-back request are rejected.

Optionally, the storage data access device 600 further includes:

a second receiving module, configured to receive a first read request, wherein the first read request carries a second target global address;

The first transmission module is configured to, when it is determined that the target storage space indicated by the second target global address is located in the first functional core and the target storage space is not in a locked state, according to the mapping between the global address and the private address relationship, determining the first private address corresponding to the second target global address, and transmitting the first target data corresponding to the first private address in the target storage space.

Optionally, the first read request, the first target data, the first write-back request, and the data to be written back are transmitted through an on-chip network or an on-chip bus, and any two in the many-core system are transmitted. The functional cores are connected through the on-chip network or on-chip bus.

Optionally, the storage data access device 600 further includes:

A third receiving module, configured to receive a second read request sent by a first data path, wherein the first data path is located in the first functional core, and the second read request carries a second private address ;

A second transmission module, configured to transmit the second target data corresponding to the second private address in the target storage space to the first data path when it is determined that the target storage space is not in a locked state.

Optionally, the setting module 603 includes:

a locking unit, configured to set the target storage space to a locked state and receive the data to be written back;

an update unit, configured to update the data in the target storage space according to the data to be written back;

An unlocking unit, configured to release the locked state of the target storage space after the update is completed.

Further, the first write-back request also carries the storage length of the data to be written back, and the update unit includes:

a writing subunit, configured to acquire the data length that has been updated in the target storage space in the process of writing the data to be written back into the target storage space;

A determination subunit, configured to determine that the update is completed when the length of the data that has been updated in the target storage space matches the storage length of the data to be written back.

Optionally, the first determining module 602 includes:

a first determining unit, configured to determine a third private address corresponding to the first target global address according to the mapping relationship between the global address and the private address;

The second determining unit is configured to determine the target storage space corresponding to the third private address in the first functional core.

Optionally, the first write-back request is an access request initiated by a second functional core in the many-core system, and the storage data access device 600 further includes:

A sending module, configured to send notification signaling to the second functional core, wherein the notification signaling is used to notify the second functional core that the data to be written back is successfully written back.

Optionally, the storage data access device 600 further includes:

An execution module, configured to perform at least one of the following operations when the target storage space is in a locked state:

rejecting the first writeback request;

The first write-back request is added to a message queue to respond to the first write-back request when the target storage space is switched to an unlocked state.

Optionally, the first writeback request includes at least one of the following:

a write-back request sent by the first data path of the first functional core;

A writeback request sent by the second functional core;

Wherein, the second functional core is a functional core different from the first functional core in the many-core system.

Optionally, the mapping relationship between the global address and the private address is determined in the following manner:

In the case where the many-core system includes S chips, the target functional core where the corresponding private address is located and the target chip where the target functional core is located are indicated based on each global address, so that the global address corresponding to each private address is address, to determine the mapping relationship;

or,

When the many-core system includes one chip, and the chip includes a functional core array arranged in J rows and P columns, each global address refers to the target functional core where the corresponding private address is located, and the target functional core. The position of the function core in the entire column of the function core is used to determine the mapping relationship according to the global address corresponding to each private address.

Optionally, the working mode of the target storage space includes a first working mode and a second working mode;

Wherein, in the first working mode, reject the second read request to the target storage space until the first read request completes a response; in the second working mode, reject the target storage space the first read request of the storage space until the second read request completes the response;

The storage data access device 600 further includes at least one of the following:

a second determining module, configured to determine the working mode of the target storage space according to the control instruction;

a third determining module, configured to, in response to the first read request, determine that the working mode is the first working mode;

A fourth determining module, configured to determine that the working mode is the second working mode in response to the second read request.

Optionally, in the case that the receiving time difference between the first read request and the second read request is less than a preset time, determine whether the first read request and the At least one of the second read requests responds.

The storage data access device 600 provided in this embodiment of the present application can perform each process performed by the first functional core in the method embodiment shown in FIG. 1 , and can improve the operation efficiency of the many-core system and save storage resources. The beneficial effects of the illustrated method embodiments are the same, and are not repeated here in order to avoid repetition.

The device for accessing stored data in this embodiment of the present application may be a device, or may be a component, an integrated circuit, or a chip in a terminal. The apparatus may be a mobile electronic device or a non-mobile electronic device. Exemplarily, the mobile electronic device may be a mobile phone, a tablet computer, a notebook computer, a palmtop computer, an in-vehicle electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (personal digital assistant). assistant, PDA), etc., the non-mobile electronic device may be a personal computer (personal computer, PC), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiment of the present application.

The device for accessing stored data in this embodiment of the present application may be a device having an operating system. The operating system may be an Android (Android) operating system, an ios operating system, or other possible operating systems, which are not specifically limited in the embodiments of the present application.

The storage data access device provided in the embodiment of the present application can implement each process implemented by the method embodiment shown in FIG. 1 , and to avoid repetition, details are not repeated here.

Optionally, as shown in FIG. 7 , an embodiment of the present application further provides an electronic device 700, including a processor 701, a memory 702, a program or instruction stored in the memory 702 and executable on the processor 701, When the program or instruction is executed by the processor 701, each process of the above-mentioned storage data access method embodiment can be realized, and the same technical effect can be achieved. In order to avoid repetition, details are not repeated here.

It should be noted that the electronic devices in the embodiments of the present application include the aforementioned mobile electronic devices and non-mobile electronic devices.

The embodiments of the present application further provide a readable storage medium, where a program or an instruction is stored on the readable storage medium, and when the program or instruction is executed by a processor, each process of the above embodiment of the stored data access method is implemented, and can achieve The same technical effect, in order to avoid repetition, will not be repeated here.

Wherein, the processor is the processor in the electronic device described in the foregoing embodiments. The readable storage medium includes a computer-readable storage medium, such as a computer read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and the like.

An embodiment of the present application further provides a chip, where the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is configured to run a program or an instruction to implement the above embodiment of the method for accessing stored data and can achieve the same technical effect, in order to avoid repetition, it will not be repeated here.

It should be understood that the chip mentioned in the embodiments of the present application may also be referred to as a system-on-chip, a system-on-chip, a system-on-a-chip, or a system-on-a-chip, or the like.

It should be noted that, herein, the terms "comprising", "comprising" or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements, It also includes other elements not expressly listed or inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in the reverse order depending on the functions involved. To perform functions, for example, the described methods may be performed in an order different from that described, and various steps may also be added, omitted, or combined. Additionally, features described with reference to some examples may be combined in other examples.

From the description of the above embodiments, those skilled in the art can clearly understand that the method of the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is better implementation. Based on this understanding, the technical solution of the present application can be embodied in the form of a software product in essence or in a part that contributes to the prior art, and the computer software product is stored in a storage medium (such as ROM/RAM, magnetic disk, CD-ROM), including several instructions to make a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) execute the methods described in the various embodiments of this application.

The embodiments of the present application have been described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific embodiments, which are merely illustrative rather than restrictive. Under the inspiration of this application, without departing from the scope of protection of the purpose of this application and the claims, many forms can be made, which all fall within the protection of this application.

Claims (10)

1. a storage data access method, applied to the first functional core in the many-core system, is characterized in that, the method comprises: receiving a first write-back request, wherein the first write-back request carries the first target global address of the data to be written back; determining the target storage space pointed to by the first target global address; When the target storage space is in an unlocked state, set the target storage space to a locked state until the data to be written back is successfully written back; The target storage space is located in the first functional core, and in the locked state, access requests to the target storage space other than the first write-back request are rejected. 2. The storage data access method according to claim 1, wherein before the receiving the first write-back request, the method further comprises: receiving a first read request, wherein the first read request carries a second target global address; When it is determined that the target storage space indicated by the second target global address is located in the first functional core and the target storage space is not in a locked state, the second target storage space is determined according to the mapping relationship between the global address and the private address. The first private address corresponding to the target global address, and the first target data corresponding to the first private address in the target storage space is transmitted. 3. The storage data access method according to claim 2, wherein the method further comprises: receiving a second read request sent by a first data path, wherein the first data path is located in the first functional core, and the second read request carries a second private address; When it is determined that the target storage space is not in a locked state, second target data corresponding to the second private address in the target storage space is transmitted to the first data path. 4. The method according to claim 1, wherein the setting the target storage space to a locked state until the data to be written back is successfully written back comprises: Setting the target storage space to a locked state, and receiving the data to be written back; updating the data in the target storage space according to the data to be written back; After the update is completed, the locked state of the target storage space is released. 5 . The method according to claim 4 , wherein the first write-back request carries the storage length of the data to be written back, and the storage length of the data to be written back is stored in the target storage space according to the data to be written back. 6 . updated data, including: In the process of writing the data to be written back into the target storage space, obtain the length of the updated data in the target storage space; When the length of the updated data in the target storage space matches the storage length of the data to be written back, it is determined that the update is completed. 6. storage data access method according to claim 2 or 5, is characterized in that, the mapping relation of described global address and private address, is determined by the following way: In the case where the many-core system includes S chips, the target functional core where the corresponding private address is located and the target chip where the target functional core is located are indicated based on each global address, so that the global address corresponding to each private address is address, to determine the mapping relationship; or, When the many-core system includes one chip, and the chip includes a functional core array arranged in J rows and P columns, each global address refers to the target functional core where the corresponding private address is located, and the target functional core. The position of the function core in the entire column of the function core is used to determine the mapping relationship according to the global address corresponding to each private address. 7. The storage data access method according to claim 3, wherein the working mode of the target storage space comprises a first working mode and a second working mode; Wherein, in the first working mode, reject the second read request to the target storage space until the first read request completes a response; in the second working mode, reject the target storage space the first read request of the storage space until the second read request completes the response; The method also includes at least one of the following: According to the control instruction, determine the working mode of the target storage space; In response to the first read request, determining that the working mode is the first working mode; In response to the second read request, it is determined that the operating mode is the second operating mode. 8. A storage data access device, applied to the first functional core in a many-core system, wherein the device comprises: a first receiving module, configured to receive a first write-back request, wherein the first write-back request carries the first target global address of the data to be written back; a first determining module, configured to determine the target storage space pointed to by the first target global address; a setting module, configured to set the target storage space to a locked state when the target storage space is in an unlocked state, until the data to be written back is successfully written back; The target storage space is located in the first functional core, and in the locked state, access requests to the target storage space other than the first write-back request are rejected. 9. An electronic device, characterized in that it comprises a processor, a memory, and a program or instruction that is stored on the memory and can be run on the processor, and the program or instruction is implemented when the processor is executed. The steps of the storage data access method according to any one of claims 1-7. 10. A readable storage medium, wherein a program or an instruction is stored on the readable storage medium, and when the program or instruction is executed by a processor, the storage according to any one of claims 1-7 is implemented The steps of the data access method.

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