JP2001318766A - Disk array device and cache memory control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a disk array device and a cache memory control method for executing second and succeeding pieces of write command processing without putting loads on the processor of a main controller. SOLUTION: This disk array device is composed of two controllers and executes the double write of write data in the two controllers without using the hardware of a shared memory. The write data are held in both of the two controllers and a means is provided for making the write data held in the other one of the two controllers mutually referable when a fault is generated in one of the controllers.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory control technique for a disk array device having a two-controller structure and having no shared memory hardware. By holding
The present invention relates to a disk array device and a cache memory control method that can be executed in a subsequent write command process without imposing a load on a processor of a mate controller.

[0002]

2. Description of the Related Art Conventionally, as a technique of double writing of write data, for example, a cache memory is provided independently of two controllers to form a shared memory structure which can be accessed from both controllers, and a cache memory in a controller is used. And a method of transmitting cache data to a mate controller by some method is disclosed.

As such a prior art, there is, for example, a cache memory control system described in Japanese Patent Application Laid-Open No. 10-222423 (first prior art). FIG. 5 is a functional block diagram for explaining a cache memory control method according to the first related art. Referring to FIG. 5, the cache memory control method according to the first related art is an MP system in which a processor 100, a processor 200, a shared memory 300, and an input / output control device 400 are connected to a shared bus 10.

The processor 100 includes a cache memory 110 controlled by a write-back method, a cache memory control circuit 120 for controlling an address signal line, a data signal line, a control signal line, and the like input / output to / from the cache memory 110; A copy tag 130 for storing a copy of the address part and the state part of the memory 110; address signal lines and data signal lines input / output to / from the copy tag 130;
Copy tag control circuit 140 for controlling control signal lines and the like
An arithmetic control circuit 150 for controlling arithmetic processing and program execution; and a bus interface circuit 1 for controlling an interface between the arithmetic control circuit 150 and the shared bus 10
60, a copy tag control circuit 140 and a bus interface circuit 160 which detect an access request on the shared bus 10 and
And a bus monitoring circuit 170 for instructing the bus. The cache memory 110 includes an address section 111 for storing an upper address of each stored block, a state section 112 for storing a state value of each block, and a data section 113 for storing data of each block. . The upper address here refers to an upper bit string excluding a bit string specifying a byte position in a block and a bit string specifying a block position in a cache memory when the address is viewed as a bit string. The address part 111 and the state part 112 are collectively called a tag part. The copy tag 130 stores a copy of the tag portion of the cache memory 110, and stores a copy of the address portion 111 of the cache memory 110 and a state of storing a copy of the status portion 112 of the cache memory 110. And a section 132. The status section 112 of the cache memory 110 and the status section 132 of the copy tag 130 can store four status values for each block. The four status values are an invalid status, a shared status, an exclusive match status, and an exclusive change status. The cache memory control circuit 120 outputs a signal for notifying the copy tag 130 of the transition of an arbitrary block of the cache memory 110 to the exclusive change state and the position of the block via the signal line 121.

[0005] The processor 200 has the same configuration as the processor 100, and the components of the processor 200 are also the same as the corresponding components of the processor 100. That is, the processor 200 includes the address unit 21
1. A cache memory 210 including a state unit 212 and a data unit 213, and a cache memory control circuit 22.
0, a copy tag 230 including an address section 231 and a state section 232, a copy tag control circuit 240, an arithmetic control circuit 250, and a bus interface circuit 260.
And a bus monitoring circuit 270.

[0006] The shared memory 300 is connected to the shared bus 10 and can respond to a memory read access or a memory write access requested on the shared bus 10 from the processor 100, the processor 200, and the input / output control device 400. Device.

The input / output control device 400 has an interface with a specific input / output device, for example, a magnetic disk device (not shown), and the shared memory 30 via the shared bus 10.
It is a device that can read / write to 0.

The shared bus 10 includes control signal lines such as an address signal line, a data signal line, a read / write command signal line, a bus arbitration signal line, a timing signal line, and the like, which enable each connected device to access each other. It is a bus including. In particular, the shared bus 10 has a change signal line 511 for notifying whether the response data to the read request has been changed by the processor and a shared signal for notifying whether the response data to the read request is shared by a plurality of processors. And a signal line 512.

As another prior art, for example, there is a control method of a main storage device described in Japanese Patent Application Laid-Open No. 6-67979 (second prior art). FIG. 6 is a functional block diagram for explaining a control method of the main storage device according to the second conventional technique.

Referring to FIG. 6, a main storage device according to a second prior art includes an active information processing system (hereinafter referred to as SYSA) 61.
1 and a standby information processing system (SYSB) 612 that takes over the processing when a failure occurs. SYSA611
Denotes a processor (hereinafter referred to as CPU) 1a, a copy-back cache memory (hereinafter referred to as CBCM) 2a connected to the CPU 1a by an address bus 5a and a data bus 6a,
M2a has a main storage device (hereinafter MEM) 3a connected by an address bus 7a and a data bus 8a, and a copyback buffer device (hereinafter CBBM) 4a connected to the CPU 1a by an address bus 5a and a data bus 6a. It is composed.

The SYSB 612 includes a processor (hereinafter, CPU) 1b, a copy-back cache memory (hereinafter, CBCM) 2b connected to the CPU 1b by an address bus 5b and a data bus 6b, and an address bus 7b and a data bus 8b to the CBCM 2b. It comprises a main storage device (hereinafter MEM) 3b connected thereto, and a copyback buffer device (hereinafter CBBM) 4b connected to the CPU 1b via an address bus 5b and a data bus 6b.

CBBM 4a of SYSA 611 is SYSB
Address bus 9a and data bus 1
0a, and CBBM4b of SYSB612 is S
The address bus 9b and the data bus 10b are connected to the MEM 3a of the YSA 611 via the address bus 9b and the data bus 10b, and this application example has a system configuration in which the SYSA 611 and the SYSB 612 are symmetrically connected to each other.

As described above, in the second prior art, a cache memory is arranged in a controller, and write data is transmitted from a CPU to a copy-back cache memory (CBCM) as a mechanism for transmitting write data to a mate controller by hardware. Although write data is intercepted by the CBBM and transmitted to the mate controller, for example, a PCI bus (Peripheral Compon
In the case where a general-purpose bus such as ent Interconnect bus (system bus / local bus) is used, since the specification of interception is not defined, the internal bus is constituted by the original bus.

As a third prior art, for example, FIG.
A disk array device as shown in FIG. FIG. 7 is a functional block diagram for explaining a disk array device of the third related art. That is, the disk array device of the third prior art includes two controllers 21 between the host computer 11 and the disks 15,.
31. The host computer 11 and the controllers 21 and 31 are connected by general-purpose buses 12 and 13 such as a SCSI (small computer system interface) bus, for example. Controllers 21, 31 and disks 15,..., 18
Are connected by a general-purpose bus 14 such as a SCSI bus, for example.

The controller 21 includes a microprocessor 23, a memory 27 for caching read or write data and storing processor control information, an interface chip 22 for controlling communication with the host computer 11, a disk 15,. , 18 are controlled, and each chip in the controller is connected by an internal bus 25.

Similarly, the controller 31 includes a microprocessor 33 and a memory 3 for caching read or write data and storing control information of the processor.
7, an interface chip 32 for controlling the communication with the host computer 11, and an interface chip 36 for controlling the communication with the disks 15,..., 18, and each chip in the controller is connected by an internal bus 35. .

[0017]

However, according to the first prior art, the shared memory 300 is formed on an independent board (package) so as not to be removed together due to replacement of a controller by a fault. In consideration of the failure of the memory, the shared memory 300 needs to be duplicated, and there is a disadvantage that the circuit configuration is large and the cost is high, and there is a problem that it is difficult to adopt it in a small-sized system.

In the second prior art, since the internal bus is composed of an original bus, if a general-purpose bus can be adopted, an interface chip or the like can be freely selected from general-purpose products, and a high-performance device can be provided. Although there is an advantage that it can be obtained at a low price, there is a problem that such a configuration is difficult with an original bus.

In the third prior art, since the dual-purpose writing uses the disk-side general-purpose bus 14, there is a problem that processing overhead is large, and a load is imposed on the processor of the mate controller. There were also problems.

The present invention has been made in view of such a problem, and an object of the present invention is to seed a mate controller segment and retain its cache address and bitmap to thereby execute the second and subsequent operations. It is an object of the present invention to provide a disk array device and a cache memory control method that can be executed without imposing a load on a processor of a mate controller in a write command process.

[0021]

The gist of the present invention described in claim 1 of the present invention is that write data is double-written by two controllers without using hardware of a shared memory. A disk array device that holds write data in both of the two controllers and exchanges the write data held in the other of the two controllers when a failure occurs in one of the controllers. There is a disk array device having means for making it possible to refer to. The gist of the invention described in claim 2 of the present invention resides in that both the two controllers are provided between a host computer and a disk, and both the host computer and the two controllers are connected by a general-purpose bus. 2. The disk array device according to claim 1, wherein both the two controllers and the disk are connected by a general-purpose bus. According to a third aspect of the present invention, each of the two controllers includes a microprocessor, a memory for caching read or write data and storing control information of the processor, and the host computer. A first interface chip for controlling communication with the
A second interface chip for controlling communication with the disk;
3. The disk array device according to claim 1, further comprising a DMA controller capable of transmitting data to an arbitrary address of the memory of the other controller. The gist of the invention described in claim 4 of the present invention is that segment management information, a bitmap, and a write cache are defined in the memory that manages a cache in segment units. Item 3
Above. The gist of the invention according to claim 5 of the present invention is that the segment management information holds a state of each segment, and includes a seeds flag indicating a state of a seed, a logical unit number, and a logical block address. An own bitmap address indicating both bitmap storage positions of the own controller, an own cache address indicating a cache position of the own controller, and another bitmap address indicating the other bitmap storage position of the two controllers;
5. The disk array device according to claim 4, further comprising another cache address indicating the other cache position of said two controllers. The gist of the invention described in claim 6 of the present invention is that the bitmap is a map indicating at which position in the cache corresponding to each segment valid data exists. 5. The disk array device according to item 5.
The gist of the invention according to claim 7 of the present invention resides in the disk array device according to claim 6, wherein the write cache is a cache memory corresponding to each segment. The gist of the invention described in claim 8 of the present invention is that when one of the controllers receives a write command from the host computer,
Referring to the segment management information of the self, it is confirmed whether or not a hit has occurred in the segment which is itself seeded. If the hit has not been found, a seed command is transmitted to the other of the two controllers via the general-purpose bus to execute the segment. And receives write data from the host computer, stores the write data in its own write cache, updates its bitmap corresponding to the storage location to a valid state, and writes its own write cache data and its own Sending the bitmap to the write cache and the bitmap on the other side of the two controllers via the DMA controller of the other of the two controllers to receive a write command, and one of the controllers If two segments are hit, Without transmitting a seed command to the other of the rollers, it receives write data from the host computer, stores it in its own write cache, updates its bitmap corresponding to the storage location to a valid state, and updates its own bitmap. 8. The data of the write cache and the bitmap of its own are transmitted to the other write cache and the bitmap of the two controllers via the other DMA controller of the two controllers. Above. Further, the gist of the invention described in claim 9 of the present invention resides in a disk array device which is constituted by two controllers and executes double writing of write data by the two controllers without using hardware of a shared memory. On the other hand, the method includes a step of holding write data in both of the two controllers and enabling cross-reference of the write data held in the other of the two controllers when a failure occurs in one of the controllers. The present invention resides in a cache memory control method. The gist of the invention described in claim 10 of the present invention resides in that a memory provided in each of the two controllers for caching read or write data on a segment basis and storing control information of a processor has segment management information. And a step of defining a bitmap and a write cache. According to an eleventh aspect of the present invention, the segment management information holds a state of each segment, and includes a seeds flag indicating a state of a seed, a logical unit number, and a logical block address. An own bitmap address indicating both bitmap storage positions of the own controller, an own cache address indicating a cache position of the own controller, and another bitmap address indicating the other bitmap storage position of the two controllers; 11. The cache memory control method according to claim 10, further comprising another cache address indicating the other cache position of the two controllers. The gist of the invention described in claim 12 of the present invention is that the bitmap is a map indicating at which position in the cache corresponding to each segment valid data exists. 11 is a cache memory control method according to the present invention. The gist of the invention according to claim 13 of the present invention resides in the cache memory control method according to claim 12, wherein the write cache is a cache memory corresponding to each segment. Further, claim 14 of the present invention
The gist of the invention described in (1) is that, when a write command is received from the host computer, one of the controllers refers to the segment management information of the controller and checks whether a hit has occurred in a segment of its own Process and, if no hits are made, through the general-purpose bus.
Transmitting a seed command to the other controller to seed the segment; receiving write data from the host computer, storing the write data in its own write cache, and validating its bitmap corresponding to the storage location. And transmitting the data of its own write cache and its own bitmap to the write cache and the bitmap on the other side of the two controllers via the other DMA controller of the two controllers. Receiving a write command from the host computer without transmitting a seed command to the other of the two controllers when one of the controllers hits a segment that is being seeded. The light cap A step of updating the bit map of a self-enable state corresponding to the stored Shrewsbury the storage position, the other D of the data and its the bitmap own the write cache the two controllers
14. The cache memory control method according to claim 13, further comprising a step of transmitting the other of the two controllers to the write cache and the bitmap via an MA controller.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the disk array device 50 having a two-controller configuration and having no hardware of a shared memory, the present invention relates to a mate controller (in other words, a double controller for protecting write data from a failure). For example, the processor of the partner controller is not loaded.

Since the write data is stored in the memory in the controller, if the write cache is used in a one-controller configuration, the write data is lost due to the failure of the controller. On the other hand, if the write data is stored in both controllers in a two-controller configuration, the write data will not be lost even if one of the controllers fails. Such a mechanism for holding write data in both controllers is called double writing. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a functional block diagram for explaining a disk array device 50 according to a first embodiment of the present invention. The disk array device 50 of the present embodiment includes two controllers 21, 3 between the host computer 11 and the disks 15,.
1.

Host computer 11 and controller 2
1, 31 are, for example, SCSI (square: small
It is connected by general-purpose buses 12 and 13 such as a computer system interface bus.

The controllers 21, 31 and the disk 15,
.., 18 are general-purpose buses 1 such as SCSI buses.
4 are connected.

The controller 21 includes a microprocessor 23, a memory 27 for caching read or write data and storing processor control information, an interface chip 22 for controlling communication with the host computer 11, a disk 15,. , 18 that can transmit data to an arbitrary address in the memory 27 of the own controller 21 to an arbitrary address in the memory 27 of the mate controller.
It has an MA controller 24, and each chip in the controller 21 is connected by an internal bus 25.

Similarly, the controller 31 includes a microprocessor 33 and a memory 3 for caching read or write data and storing control information of the processor.
7, an interface chip 32 for controlling communication with the host computer 11, an interface chip 36 for controlling communication with the disks 15,..., 18, and data at an arbitrary address in the memory 37 of the controller 31 of the own controller. A DMA controller 34 capable of transmitting to an arbitrary address of the memory 37;
Each chip in 1 is connected by an internal bus 35.

FIG. 2 is a definition diagram of information stored in the memories 27 and 37 of FIG. In the present invention, the cache is managed in units called segments, and the memories 27 and 37 are used.
Defines segment management information 41 and 44, bitmaps 42 and 45, and write caches 43 and 46. The segment management information 41, 44 holds the state of each segment, and includes a seed flag indicating the state of the seed, a LUN (logical unit number), and an LBA.
(Logical block address), its own bitmap address indicating the bitmap storage position of its own controller,
It has its own cache address indicating the cache position of its own controller, another bitmap address indicating the bitmap storage position of its mate controller, and another cache address indicating the cache position of its mate controller. The bitmaps 42 and 45 are maps that indicate where valid data exists in the cache corresponding to each segment, where 0 is invalid and 1 is valid. The write caches 43 and 46 are the cache memories themselves corresponding to each segment.

The controller 21 is the host computer 1
When a write command is received from the controller 1, it is checked whether or not the segment itself has been hit by referring to the segment management information 41. If not, a seed command is sent to the controller 31 via the general-purpose bus 14. Send and seed the segment. Thereafter, the write data is received from the host computer 11 and stored in the write cache 43, and the bitmap 42 corresponding to the storage location is updated to 1. Then, write cache 4
3 and the bit map 42 are transferred to the DMA controller 2
4 and 34 to the write cache 46 and the bitmap 45 of the memory 37 of the controller 31. In the processing so far, the microprocessor 33 of the controller 31 operates by transmitting and receiving the seed command.

Subsequently, when a write command is received and a segment hit by itself is hit, write data is received from the host computer 11 and stored in the write cache 43 without transmitting a seed command to the controller 31. Then, the bitmap 42 corresponding to the storage location is updated to 1. Thereafter, the data of the write cache 43 and the bit map 42 are transmitted to the write cache 46 and the bit map 45 of the controller 31 via the DMA controllers 24 and 34.

As described above, according to the first embodiment, in the second and subsequent write commands, the controller 3
Since the write command processing can be executed without imposing a load on one processor 33, the performance of the entire apparatus is improved.

Next, the operation of the disk array device 50 (cache memory control method) will be described. In the operation of the present embodiment, an example is shown in which a write command is received from the host computer 11 and is double-written. Further, in the present embodiment, the effect is exerted in the second and subsequent write command processing, and therefore, a case where the write command is received twice consecutively will be described.

FIG. 3 is a flowchart for explaining write processing in the cache memory control method according to the first embodiment of the present invention.
The flow of processing when a write command is received twice using the SI interface is shown.

The controller 21 receives a write command from the host computer 11 (step S51: write command reception), and judges hit or miss of the segment with reference to its own segment management information 41 (step S52: hit / miss judgment). ). Since it is the first command, it is missed and a seed command is issued to the controller 31 via the general-purpose bus 14 (step S53: SCSI command is issued with SCSI), and at the same time, L is used as its parameter.
Send UN and LBA.

The controller 31 that has received it seeds its own empty segment and enters the segment management information 4
4, a flag indicating a seed state, an LUN, an LBA, an address of the seeded cache, and an address for storing the corresponding bitmap 42, 45 are registered (step S54: registered in the segment management information 44). A seeds completion report is executed (step S5).
5: Seed completion report by SCSI), and at the same time, the cache address and the bitmap storage address are transmitted as the response information. The controller 21 stores, in its own segment management information 41, a flag indicating the seed state, the LUN and LBA, the address of the cache seeded by itself, the address for storing the corresponding bitmaps 42 and 45, and the address of the cache seeded by the mate controller. And the addresses for storing the corresponding bitmaps 42 and 45 are registered (step S56: registered in the segment management information 44).

Thereafter, write data is received from the host computer 11 at the cache address of its own seed (step S57: write data reception), and the corresponding bit map 42 is updated (step S5).
8: Bitmap update).

The write data is transferred to the DMA controller 2
4 and 34, the data is directly transferred to the cache address of the controller 31 (step S5).
9: write data transfer by DMA), bit map 4
2 and 45 are transferred to the bitmap 45 of the controller 31 via the DMA controllers 24 and 34 (step S60: bitmap transfer by DMA), thereby completing the double writing and completing the first write command at the same time. I do.

Subsequently, when a second write command is received (step S61: write command reception), a hit / miss determination of the segment is performed with reference to the own segment management information 41 (step S62: hit / miss determination). If it hits, the host computer 11 can receive the write data from the host computer 11 to the cache address being seeded without exchanging the seeds as in the first time (step S63: write data reception).

Thereafter, the corresponding bit map 42
Is updated (step S64: bitmap update), and the same write data and the same bitmaps 42 and 45 are transferred to the controller 31 as in the first time (step S6).
5: Write data transfer by DMA, step S66: DM
A, bitmap transfer), thereby completing the double writing and simultaneously completing the second write command.

Comparing these processings, in the first command processing (step S67), while processing of the seed command is performed and it takes time,
In the second and subsequent command processing (step S68), there is no exchange of the seed command, the processing time is reduced, and it is understood that the processor of the controller 31 is not loaded.

FIG. 4 is a flowchart for explaining write processing in each of the controllers 21 and 31 of the disk array device 50 according to the first embodiment of the present invention. Is shown.

With reference to FIG. 4, what processing each processor performs will be described. After execution of step S71 (processing of the controller 21), the controller 21
Receives a write command from the host computer 11 (step S72: receives a write command from the host computer 11), and determines whether or not it has hit a segment being seeded (step S7).
3: Hit the segment during seeds? ).

Here, if it is the first time, a mistake is made (No in step S73), so a segment seed command is issued to the controller 31 by SCSI (step S74: S
The segment seed command is issued to the controller 31 by CSI.)

The controller 31 receives the seed command (step S82: processing of the controller 31 → step S83: receives a segment seed command from the controller 21 by SCSI) and updates its own segment management information 44 (step S84: The segment management information 44 is updated), and a notification of the success of the segment seed is transmitted to the controller 21 (step S85: a notification of the success of the segment seed is transmitted to the controller 21 by SCSI).

The controller 21 receives the notification (step S75: receives a notification of the success of the segment seed from the controller 31 by SCSI) and updates its own segment management information 41 (step S76: updates the segment management information 41). The write data is received from the host computer 11 (step S77: write data is received from the host computer 11), and the bitmap 42 is updated accordingly (step S78: update of the bitmap 42).

Thereafter, the write data is transmitted to the controller 31 by DMA (step S79: the write data is transmitted to the controller 31 by DMA), and then the bit map 42 is transmitted (step S80: to the controller 31 by DMA). The bitmap 42 is transmitted) and the completion is reported to the host computer 11 (step S81: completion report to the host computer 11).

After the second time, a hit is determined in the hit determination of the seeding segment (step S73: hit in the seeding segment?) (Yes in step S73).
s), seeds-related processing (step S74: issue a segment seeds command to the controller 31 by SCSI,
Step S75: Receiving notification of the success of the segment seed from the controller 31 by the SCSI, and skipping the step S76: updating the segment management information 41). As a result, the processing of the controller 31 (step S82) is not performed, so that the load on the microprocessor 33 is not applied.

As described above, according to the first embodiment, the segment of the mate controller is seeded and its cache address and the bitmaps 42 and 45 are held, so that in the second and subsequent write command processing, This can be executed without imposing a load on the processor of the mate controller. As a result, there is an effect that the performance of the entire apparatus can be improved.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described.
An embodiment will be described. The same parts as those already described in the first embodiment are denoted by the same reference numerals, and the duplicate description will be omitted.

The second embodiment of the present invention includes controllers 21 and 3 in addition to the basic configuration of the first embodiment.
It is characterized in that it has a configuration in which one can be increased. Specifically, a general-purpose bus such as a SCSI bus for transmitting a seed command and data in its own memories 27 and 37 are transmitted to an arbitrary controller 2.
A DMA controller (not shown) capable of directly transmitting data to the memories 27 and 37 of the first and third memories is provided.

The processing flow is the same as that of the first embodiment.
This is basically the same as the case of the controller configuration, and the first time, the controller transmits a seed command to the controllers 21 and 31 that are going to write twice to seed the segment and
After the first time, the double writing is executed without the seeding process.

It should be noted that the present invention is not limited to the above embodiments, and it is clear that the embodiments can be appropriately modified within the scope of the technical idea of the present invention. Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment, and can be set to numbers, positions, shapes, and the like suitable for carrying out the present invention. In each drawing, the same components are denoted by the same reference numerals.

[0054]

Since the present invention is configured as described above, the segments of the mate controller are seeded and their cache addresses and bitmaps are retained, so that the mate controller can be used in the second and subsequent write command processing. This can be executed without imposing a load on the processor, and as a result, the performance of the entire apparatus can be improved.

[Brief description of the drawings]

FIG. 1 is a functional block diagram for explaining a disk array device according to a first embodiment of the present invention.

FIG. 2 is a definition diagram of information stored in a memory of FIG. 1;

FIG. 3 is a flowchart illustrating a write process in the cache memory control method according to the first embodiment of the present invention.

FIG. 4 is a flowchart for explaining a write process in each controller of the disk array device according to the first embodiment of the present invention.

FIG. 5 is a functional block diagram for explaining a cache memory control method according to the first related art.

FIG. 6 is a functional block diagram for explaining a control method of a main storage device according to a second conventional technique.

FIG. 7 is a functional block diagram for explaining a disk array device of a third conventional technique.

[Explanation of symbols]

 11: Host computer 12, 13, 14 ... General-purpose bus 15, ..., 18 ... Disk 21, 31 ... Controller 22, 26, 32, 36 ... Interface chip 23, 33 ... Microprocessor 24, 34 ... DMA controller 25, 35 ... Internal buses 27, 37 Memory 41, 44 Segment management information 42, 45 Bitmap 43, 46 Write cache 50 Disk array device

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 12/16 310 G06F 12/16 310J 320 320L G11B 19/02 501 G11B 19/02 501F

Claims (14)

[Claims] 1. A disk array device comprising two controllers and performing double writing of write data by the two controllers without using hardware of a shared memory, wherein the write data is written to the two controllers. A disk array device which has means for holding the data in both of them and making it possible to cross-reference write data held in the other of the two controllers when a failure occurs in one of the controllers. 2. The apparatus has both the two controllers between a host computer and a disk, wherein both the host computer and the two controllers are connected by a general-purpose bus, and both the two controllers are connected to the disk. 2. The disk array device according to claim 1, wherein the disks are connected by a general-purpose bus. 3. Each of the two controllers includes:
A microprocessor, a memory for caching read or write data and storing control information of the processor, a first interface chip for controlling communication with the host computer, and a second interface chip for controlling communication with the disk 3. An interface chip and a DMA controller capable of transmitting data at an arbitrary address of the memory to an arbitrary address of the other one of the two controllers.
The disk array device according to item 1. 4. The disk array device according to claim 3, wherein segment management information, a bitmap, and a write cache are defined in the memory that manages a cache in segment units. 5. The segment management information holds a state of each segment, and includes a seeds flag indicating a state of a seed, a logical unit number, a logical block address, and a bitmap storage location of both the own controller. Its own bitmap address, its own cache address indicating its own cache position,
5. The disk array device according to claim 4, comprising another bitmap address indicating the other bitmap storage position of the two controllers, and another cache address indicating the other cache position of the two controllers. 6. The disk array device according to claim 5, wherein the bit map is a map indicating in which position in the cache corresponding to each segment valid data exists. 7. The disk array device according to claim 6, wherein said write cache is a cache memory corresponding to each segment. 8. When one of the controllers receives a write command from the host computer, the one of the controllers refers to the segment management information of the controller to confirm whether or not the controller is hit by a segment of its own. If not, a seed command is transmitted to the other of the two controllers via the general-purpose bus to seed the segment, write data is received from the host computer and stored in the write cache of the host computer, and the corresponding write position is stored. Update its bitmap to a valid state,
The data of its own write cache and its bitmap are stored in the D of the other of the two controllers.
A write command is transmitted to the write cache and the bitmap on the other side of the two controllers via the MA controller, and a write command is received. Without transmitting a seed command to the other side, it receives write data from the host computer, stores it in its own write cache, updates its bitmap corresponding to the storage location to a valid state, and writes its write 8. The bitmap of claim 2, wherein the data of the cache and the bitmap of its own are transmitted to the write cache and the bitmap of the other of the two controllers via the DMA controller of the other of the two controllers. Disk array device. 9. A disk array device comprising two controllers and performing double writing of write data by the two controllers without using hardware of a shared memory, writes the write data to the two controllers. A cache memory control method, comprising the steps of: holding a write data held by both controllers; and enabling a write data held by the other of the two controllers to be cross-referenced when a failure occurs in one of the controllers. 10. A segment management information, a bit map, and a write cache are defined in a memory provided in each of the two controllers for caching read or write data in segment units and storing control information of a processor. 10. The cache memory control method according to claim 9, comprising a step. 11. The segment management information holds a state of each segment, and includes a seeds flag indicating a state of a seed, a logical unit number, a logical block address, and a bitmap storage position of both the own controller. , The own cache address indicating the cache position of the own controller, the other bitmap address indicating the other bitmap storage position of the two controllers, and the other cache position of the two controllers. 11. The cache memory control method according to claim 10, further comprising another cache address. 12. The cache memory control method according to claim 11, wherein the bit map is a map indicating in which position in the cache corresponding to each segment valid data exists. 13. The cache memory control method according to claim 12, wherein said write cache is a cache memory corresponding to each segment. 14. Upon receiving a write command from the host computer, one of the controllers refers to the segment management information of the controller to confirm whether or not the controller has hit a segment being seeded;
Sending a seed command to the other of the two controllers via the general-purpose bus if the hit has not occurred, and receiving the write data from the host computer and storing the read data in its own write cache; Updating its bitmap corresponding to a position to a valid state; and updating the data of its write cache and its bitmap via the other DMA controller of the two controllers.
Receiving a write command by transmitting to the write cache and the bitmap on the other side of one controller; and transmitting a seed command to the other of the two controllers when one of the controllers hits a segment being seeded. Receiving the write data from the host computer without transmitting the data, storing the write data in the write cache of the host computer, and updating the bit map of the write cache corresponding to the storage location to a valid state; 14. The method of claim 13, further comprising transmitting the bitmap of the two controllers to the write cache and the bitmap of the other of the two controllers via a DMA controller of the other of the two controllers. Cache memory control method.