KR20180023543A - Apparatus and method for providing memory via serial communication - Google Patents

Abstract

An electronic device according to various embodiments of the present invention includes a central processing unit (CPU), a plurality of memory modules, and a serial hub connected to at least one line for performing serial communication with the CPU and each of the plurality of memory modules. The CPU is configured to send a signal to the serial hub. The serial hub can be configured to determine a first memory module for the CPU among the plurality of memory modules based on the signal.

Description

[0001] APPARATUS AND METHOD FOR PROVIDING MEMORY VIA SERIAL COMMUNICATION [0002]

This disclosure relates generally to data communication, and more specifically, to an apparatus and method for providing memory to a central processing unit (CPU) through serial communication.

Conventionally, the interface between a central processing unit (CPU) and a memory module is a parallel bus interface. In such a parallel bus interface structure, the speed of data transferred between the CPU and the memory module is determined by the physical distance between the CPU and the memory module. Therefore, when performing a high-speed data transfer in the parallel bus interface, the CPU position and the memory module position have design limitations.

On the other hand, when a memory module is added to an electronic device, the added memory module increases the distance to the CPU from the existing memory module. That is, the added memory module does not perform as expected.

On the other hand, when performing high-speed data transfer, the CPU and the memory module generate more heat than other devices in the electronic device. In order to transfer data at high speed, the distance between the CPU and the memory module must be relatively short, so that heat can be concentrated in a relatively narrow space. This heat can increase the power consumption of the CPU and the memory module in the electronic device.

Based on the above discussion, the disclosure provides an apparatus and method for efficiently providing.

The present disclosure also provides an apparatus and method for connecting to a central processing unit (CPU) and a memory module via a serial link.

According to various embodiments of the present disclosure, an electronic device includes a central processing unit (CPU), a plurality of memory modules, and at least one memory module for performing serial communication with the CPU and each of the plurality of memory modules And a serial hub connected to the line. The CPU is configured to send a signal to the serial hub and the serial hub can be configured to determine a first memory module for the CPU from among the plurality of memory modules based on the signal.

According to various embodiments of the present disclosure, a method of operating an electronic device includes the steps of: receiving a signal from a CPU of the electronic device, the serial hub of the electronic device; Determining a first memory module for the CPU from among the plurality of memory modules. The serial hub may be connected to at least one line for performing serial communication with the CPU and each of the plurality of memory modules.

According to various embodiments of the present disclosure, an electronic device includes a first board including a CPU, a second board including a first memory module, a second memory module, and a serial relay . The CPU may be configured to send a signal to the serial relay. The serial relay may be configured to amplify the signal and to transmit the amplified signal to the first memory module. The first memory module may be configured to transmit the amplified signal to the second memory module. Wherein the serial relay is connected to the CPU and the first memory module as at least one line for performing serial communication and the second memory module is at least one line for performing serial communication, Module.

The apparatus and method according to various embodiments of the present disclosure may be implemented by connecting a central processing unit (CPU) and a memory module via a serial link, thereby eliminating design constraints, It is possible to operate efficiently.

The effects obtainable from the present disclosure are not limited to the effects mentioned above, and other effects not mentioned can be clearly understood by those skilled in the art from the description below will be.

Figure 1 shows a block diagram of an electronic device according to various embodiments of the present disclosure.
Figure 2 shows a block diagram of an electronic device comprising two central processing units (CPUs) in accordance with various embodiments of the present disclosure.
FIG. 3 illustrates an example of memory sharing of an electronic device according to various embodiments of the present disclosure.
Figure 4 illustrates an example of memory / ethernet switching of an electronic device according to various embodiments of the present disclosure.
5 illustrates an example of signal exchange between a memory module and a serial hub in accordance with various embodiments of the present disclosure.
Figure 6 illustrates an example of the functional configuration of a serial hub in accordance with various embodiments of the present disclosure.
FIG. 7 illustrates an example of a read operation or a write operation of an electronic device according to various embodiments of the present disclosure.
Figure 8 shows an example of a hierarchical structure for memory / Ethernet switching.
9 shows a flow of an electronic device according to various embodiments of the present disclosure.
10 illustrates a flow of memory sharing of an electronic device in accordance with various embodiments of the present disclosure.
11 illustrates the flow of Ethernet communication of an electronic device according to various embodiments of the present disclosure.
12 shows an example of a connection between a serial relay and a target device.
13 shows an example of the connection of a serial relay and a plurality of target devices.
14 illustrates embodiments of a serial relay in accordance with various embodiments of the present disclosure.

The terms used in this disclosure are used only to describe certain embodiments and may not be intended to limit the scope of other embodiments. The singular expressions may include plural expressions unless the context clearly dictates otherwise. Terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by one of ordinary skill in the art. The general predefined terms used in this disclosure may be interpreted as having the same or similar meaning as the contextual meanings of the related art and, unless explicitly defined in the present disclosure, include ideally or in an excessively formal sense . In some cases, the terms defined in this disclosure can not be construed to exclude embodiments of the present disclosure.

In the various embodiments of the present disclosure described below, a hardware approach is illustrated by way of example. However, the various embodiments of the present disclosure do not exclude a software-based approach, since various embodiments of the present disclosure include techniques that use both hardware and software.

Hereinafter, various embodiments of the present document will be described with reference to the accompanying drawings. It is to be understood that the embodiments and terminologies used herein are not intended to limit the invention to the particular embodiments described, but to include various modifications, equivalents, and / or alternatives of the embodiments. In connection with the description of the drawings, like reference numerals may be used for similar components. The singular expressions may include plural expressions unless the context clearly dictates otherwise.

In this document, the expressions "A or B" or "at least one of A and / or B" and the like may include all possible combinations of the items listed together. Expressions such as " first, "" second," " first, "or" second, " But is not limited to those components. When it is mentioned that some (e.g., first) component is "(functionally or communicatively) connected" or "connected" to another (second) component, May be connected directly to the component, or may be connected through another component (e.g., a third component).

In this document, the term " configured to (or configured) to "as used herein is intended to encompass all types of hardware, software, , "" Made to "," can do ", or" designed to ". In some situations, the expression "a device configured to" may mean that the device can "do " with other devices or components. For example, a processor configured (or configured) to perform the phrases "A, B, and C" may be implemented by executing one or more software programs stored in a memory device or a dedicated processor (e.g., an embedded processor) , A general purpose processor (e.g., a central processing unit (CPU) or an application processor) capable of performing the corresponding operations.

An electronic device according to various embodiments of the present document may be an apparatus including a CPU and a memory. Portable multimedia player (PMP), MP3 player, medical device, camera, mobile phone, mobile phone, video phone, electronic book reader, desktop PC, laptop PC, netbook computer, workstation, server, PDA , A base station (BS), a base station (eNodeB, eNB) supporting long term evolution (LTE), or a wearable device. Wearable devices may be of the type of accessories (eg, watches, rings, bracelets, braces, necklaces, glasses, contact lenses or head-mounted-devices (HMD) (E.g., a skin-pads or tattoo), or a bio-implantable circuit. In some embodiments, the electronic device may be, for example, a television, a digital video disk (Such as Samsung HomeSync ^TM , Apple TV ^TM , and Samsung Electronics), refrigerator, air conditioner, vacuum cleaner, oven, microwave oven, washing machine, air cleaner, set- top box, home automation control panel, Or Google TV ^™ ), a game console (eg, Xbox ^™ , PlayStation ^™ ), an electronic dictionary, an electronic key, a camcorder, or an electronic frame.

In an alternative embodiment, the electronic device may be any of a variety of medical devices (e.g., various portable medical measurement devices such as a blood glucose meter, a heart rate meter, a blood pressure meter, or a body temperature meter), magnetic resonance angiography (MRA) A navigation system, a global navigation satellite system (GNSS), an event data recorder (EDR), a flight data recorder (FDR), an automobile infotainment device, a marine electronic equipment (For example, marine navigation systems, gyro compasses, etc.), avionics, security devices, head units for vehicles, industrial or domestic robots, drones, ATMs at financial institutions, of at least one of the following types of devices: a light bulb, a fire detector, a fire alarm, a thermostat, a streetlight, a toaster, a fitness device, a hot water tank, a heater, a boiler, . According to some embodiments, the electronic device may be a piece of furniture, a building / structure or part of an automobile, an electronic board, an electronic signature receiving device, a projector, or various measuring devices (e.g., Gas, or radio wave measuring instruments, etc.). In various embodiments, the electronic device is flexible or may be a combination of two or more of the various devices described above. The electronic device according to the embodiment of the present document is not limited to the above-described devices. In this document, the term user may refer to a person using an electronic device or a device using an electronic device (e.g., an artificial intelligence electronic device).

As used herein, the term "module " includes units comprised of hardware, software, or firmware and may be used interchangeably with terms such as, for example, logic, logic blocks, components, or circuits. A "module" may be an integrally constructed component or a minimum unit or part thereof that performs one or more functions. "Module" may be implemented either mechanically or electronically, for example, by application-specific integrated circuit (ASIC) chips, field-programmable gate arrays (FPGAs) And may include programmable logic devices. At least some of the devices (e.g., modules or functions thereof) or methods (e.g., operations) according to various embodiments may be implemented with instructions stored in a computer-readable storage medium (e.g., memory) . When the instruction is executed by the CPU, the processor may perform a function corresponding to the instruction. The computer-readable recording medium may be a hard disk, a floppy disk, a magnetic medium such as a magnetic tape, an optical recording medium such as a CD-ROM, a DVD, a magnetic-optical medium such as a floppy disk, The instructions may include code that is generated by the compiler or code that may be executed by the interpreter. Modules or program modules according to various embodiments may include at least one or more of the components described above Operations that are performed by modules, program modules, or other components, in accordance with various embodiments, may be performed in a sequential, parallel, iterative, or heuristic manner, or at least in part Some operations may be executed in a different order, omitted, or other operations may be added.

Figure 1 shows a block diagram of an electronic device according to various embodiments of the present disclosure. The electronic device may be electronic device 100. Hereinafter, terms such as "part" and "group" refer to a unit for processing at least one function or operation, which may be implemented by hardware, software, or a combination of hardware and software have.

FIG. 1 defines terms necessary to describe various embodiments. (E.g., a configuration, an operation), a term (e.g., a request, a call) that refers to a signal, a term that refers to control information used in the following description, , Terms referring to network entities, terms referring to messages (e.g., commands, packets, signals), and terms referring to components (e.g., modules, . Accordingly, the present invention is not limited to the following terms, and other terms having equivalent technical meanings can be used.

The electronic device 100 according to various embodiments may be a device including a central processing unit (CPU) and a memory. For example, the electronic device 100 may be a desktop computer. As another example, the electronic device 100 may be a server. As another example, the electronic device 100 may be a laptop computer. As another example, the electronic device 100 may be a set-top box. As another example, the electronic device 100 may be a portable device (e.g., a smart phone, a wearable device).

Referring to FIG. 1, the electronic device 100 according to various embodiments may include a CPU 110, a serial hub 120, and a memory module 130, a memory module 140, and a module 150. The serial hub 120 may have a structure capable of providing various combinations of paths according to an applied configuration signal. The serial hub 120 may be referred to as a configurable serial hub. The CPU 110, the memory module 130, the memory module 140, and the module 150 may be operatively coupled to the serial hub 120.

The CPU 110 may be referred to in various terms. For example, the CPU 110 may be referred to as a central processing unit. As another example, the CPU 110 may be referred to as a processor. As another example, the CPU 110 may be referred to as a micro processor unit (MPU).

The CPU 110 may include at least one core. When the CPU 110 includes one core, the CPU 110 may be referred to as a sink core. If the CPU 110 comprises two, four, or eight cores, it may be referred to as a dual core, a quad core, or an octa core, respectively. The at least one core may perform various operations in the CPU 110.

The CPU 110 may include a register, an arithmetic logic unit, a control unit, and a CPU internal bus. The register may store a command to be processed by the CPU 110. The arithmetic logic unit may perform comparison, judgment, and calculation. The control unit can internally control the CPU 110 in order to interpret and properly execute commands. The CPU internal bus can connect the register, the arithmetic logic operation unit, and the control unit.

The CPU 110 may include a memory controller. The memory controller may perform a function of managing data in the memory module. For example, the memory controller may generate instructions to control operations of the memory module (e.g., program execution, read operation, write operation, erase operation). As another example, the memory controller may output a command to the memory module to control the operation of the memory module. The memory controller and the memory module may transmit and receive data through a memory interface. The memory interface may provide for the exchange of data between the memory controller and the memory module. In the following description, the CPU 110 is described as including a memory controller, but various embodiments are not limited to these descriptions. That is, the memory controller may be formed of hardware separate from the CPU 110.

The memory module 130 may be hardware that provides memory. The memory module 130 may be hardware that provides a memory for allocating to an application running on an electronic device. Memory module 130 may be referred to in various terms. For example, memory module 130 may be referred to as a memory device. In another example, the memory module 130 may be referred to as a volatile memory. As another example, the memory module 130 may be referred to as a random access memory (RAM). The RAM may be a term including a dynamic RAM (DRAM), a static RAM (SRAM), and a synchronous DRAM (SDRAM). In the following description, the memory module 130 is described as being a non-volatile memory, but the invention is not limited to this description. The memory module 130 may be implemented as a non-volatile memory (e.g., one time programmable ROM (OTPROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), mask ROM, flash ROM, Such as a solid state drive (SSD)) or an external memory (e.g., a flash drive such as CF (compact flash), secure digital (SD), Micro-SD, Mini- extreme digital, multi-media card (MMC), memory stick, etc.).

The memory module 130 may store instructions or data related to at least one other component of the electronic device 100. [ For example, the memory module 130 may store data received from the CPU 110 on a command to be executed by the CPU 110 and data requested by the CPU 110. The memory module 130 may store data managed by the memory controller.

The serial hub 120 may be connected to the memory module 130. The serial hub 120 may be connected to the memory module 130 via at least one serial line 160. The serial hub 120 may perform serial communication with the memory module 130 through the at least one serial line 160. The link to the serial communication may be referred to as a serial link. The serial hub 120 may be a memory interface implemented as a serial protocol for the serial communication.

In some embodiments, the at least one serial line 160 may include a transmit serial line 161, a receive serial line 163, and a ground serial line 165. The transmission serial line 161 may be a line for transmitting a signal from the serial hub 120 to the memory module 130. The reception serial line 163 may be a line through which data is transmitted from the memory module 130 to the serial hub 120. The grounding serial line 165 may be a line for matching the reference of the voltage level of the serial hub 120 and the memory module 130.

The serial communication is a method of sequentially transmitting a plurality of bits through one line, unlike a parallel method of simultaneously transmitting a plurality of bits through a plurality of lines. The one line may be referred to as a serial line. The electronic device 100 may reduce the occurrence of crosstalk between lines through the at least one serial line 130 connecting the CPU 110 and the memory module 130. [ Also, the electronic device 100 can solve the problem of synchronization of bits through the serial communication.

The serial hub 120 may be connected to the memory module 140. The memory module 140 may be a memory module that performs the same function as the memory module 130. The serial hub 120 and the memory module 140 may be connected through at least one serial line. The serial hub 120 can perform serial communication with the memory module 140 independently of the memory module 130 by using a serial communication method instead of a parallel bus method.

The serial hub 120 may additionally be coupled to the module 150. The module 150 may be an additional mountable module. In some embodiments, the module 150 may be a memory module that provides the same functionality as the memory module 130. In some other embodiments, the module 150 may be an Ethernet module. The Ethernet module may be a module for performing communication with another electronic device.

The serial hub 120 may be connected to the CPU 110 and the memory modules 130 and 140 through a serial communication interface instead of the parallel bus interface so as to solve the problem of limitation due to the physical distance between the CPU 110 and the memory modules 130 and 140 have. In addition, the serial hub 120 may provide a single interface between the memory controller and the memory modules 130 and 140 of the CPU 110. When adding or changing a module (e.g., a memory module, a memory controller, an Ethernet module), the serial hub 120 can provide scalability without building a new interface.

Although not shown in FIG. 1, additional modules may be coupled to the serial hub 120. Although FIG. 1 shows connection with modules only through a serial line, various embodiments are not limited. The serial hub 120 may be connected to an additional memory module in a conventional parallel bus mode (for example, a 64-bit bus type, a 32-bit bus type).

Figure 2 shows a block diagram of an electronic device including two CPUs in accordance with various embodiments of the present disclosure. The electronic device may be the electronic device 100 of FIG.

2, the electronic device 100 may include the CPU 110, the CPU 210, the serial hub 120, and the memory modules 221, 222, 223, 224, 225, and 226 of FIG. The CPU 210 may be a CPU that provides the same functions as the CPU 110. Each of the memory modules 221, 222, 223, 224, 225, and 226 may be a memory module that provides the same functions as the memory module 130 of FIG.

The electronic device 100 may be an electronic device supporting a multi-CPU (multi-CPU) system. Accordingly, the electronic device 100 supporting the multi-CPU system may include the CPU 110 and the CPU 210. [ 2 and the following description are based on two CPUs, but the various embodiments are not limited to these descriptions.

The serial hub 120 may be connected to the CPU 110 and the CPU 210 through a serial line, respectively. The serial line connecting the CPU 110 and the serial hub 120 may be referred to as a first serial line. The CPU 110 can transmit the first signal to the serial hub 120 through the first serial line. The serial line connecting the CPU 210 and the serial hub 120 may be referred to as a second serial line. The CPU 210 can transmit the second signal to the serial hub 120 through the second serial line.

The serial hub 120 can exchange signals between the CPU 110 and the CPU 210 through the first serial line or the second serial line. Through the signal exchange, arbitration and negotiation between the CPU 110 and the CPU 210 may be performed or a master-slave relationship between the CPUs may be established.

In some embodiments, the CPU 110 may be set as a master CPU through communication between the CPU 110 and the CPU 210, and the CPU 210 may be determined as a slave CPU. The CPU 110, as a master CPU, can configure a memory range. Here, the memory range may be a range for a memory area to be allocated. The CPU 110 may transmit information on the set memory range to the serial hub 120. [ The serial hub 120 may determine an area of memory to be provided to the CPU 110 or the CPU 210 based on the information on the memory range. In other words, the serial hub 120 can set paths between the CPUs 110 and 210 and the memory modules 221, 222, 223, 224, 225, and 226 according to the memory range.

The serial hub 120 may perform a redundancy operation between the CPU 110 and the CPU 210. The serial hub 120 may receive a control signal for setting a duplication protocol from the CPU 110 or the CPU 210 for the duplication operation. Accordingly, the serial hub 120 can set a redundancy protocol for the CPU 110 and the CPU 210 based on the control signal. Based on the redundancy protocol, a takeover from the CPU 110 to the CPU 210 may occur. Specifically, the CPU 110 can perform operations through the memory of the memory module 226 provided from the serial hub 120. During the execution of the operation, the CPU 110 may stop the operation. For example, it may happen that the CPU 110 enters an abnormal state, a change in the algorithm subject is requested, or a CPU change is required depending on the capabilities of the CPUs. If the operation of the CPU 10 is interrupted, the serial hub 120 may cause the CPU 210 to perform the operation subsequently. The serial hub 120 may provide the memory of the memory module 226 to the CPU 210 for performing the operation. The process of copying the memory allocated to the processing operation of the CPU 110 to the memory to be allocated to the operation of the CPU 210 through the serial hub 120 may be omitted. That is, the serial hub 120 can perform a redundancy operation without further use of another memory module.

For the duplication operation, the serial hub 120 may be configured to perform a takeover from the CPU 110 to the CPU 210. Here, the takeover may mean an operation in which an object managing 'operation' is changed. Through the reallocation of a memory module (e.g., memory module 226) as described above, a takeover from the CPU 110 to the CPU 210 can be performed without unnecessary copying. The serial hub 120 may be configured to perform the takeover from the CPU 110 to the CPU 210 within a shortened time.

Although FIG. 2 shows two CPUs (CPU 110 and CPU 210), a further CPU may be connected to the serial hub 120. The serial hub 120 has a structure for being connected with a CPU in a serial manner, and the serial hub 120 can expand the CPU.

FIG. 3 illustrates an example of memory sharing of an electronic device according to various embodiments of the present disclosure. The electronic device may be the electronic device 100 of FIG. The serial hub 120 of the electronic device 100 may perform memory sharing. The memory sharing means that a plurality of CPUs share a memory module or share memory resources in a memory module. The serial hub 120 may perform memory sharing between the CPU 110 and the CPU 210.

In the following description, a memory for the memory modules 221, 222, and 223 is allocated to the application of the CPU 110, and a memory for the memory modules 224, 225, and 226 is allocated to the application of the CPU 210, Describes a situation in which the object of memory allocation is changed. The memory interface between the serial hub 120 and the memory modules 221, 222, 223, 224, 225 and 226 is implemented as a serial interface so that the CPU 110 can operate Can be combined. Similarly, the CPU 210 may be operatively coupled to memory modules 221, 222, and 223.

Referring to FIG. 3, the serial hub 120 may receive information on a memory range from the CPU 110 or the CPU 210. The information on the memory range may be information indicating a memory area to be allocated to an application running on the CPU. The serial hub 120 may determine an area of a memory to be provided to the CPU 110 and the CPU 210, respectively, based on information on the memory range.

The serial hub 120 may determine a first memory to be provided to the CPU 110 and a second memory to be provided to the CPU 210 based on the usage amount of the CPU 110 and the usage amount of the CPU 210. [ For example, when the ratio of the usage amount of the CPU 110 to the usage amount of the CPU 210 is 7: 3, the serial hub 120 can store more memory in operation of the CPU 110 than the operation in the CPU 210 You can decide to allocate. The serial hub 120 may provide the CPU 110 with a memory corresponding to seven tenths of the memory to be allocated to the entire operation. The serial hub 120 may provide the CPU 210 with a memory corresponding to three tenths of the memory to be allocated. That is, the serial hub 120 may be required to change the allocation target of the memory of some memory modules.

The serial hub 120 may change the provision target of memory modules for memory sharing. In some embodiments, the CPU 110 and the CPU 210 may share the same memory module according to the setting of the serial hub 120. [ For example, the CPU 110 and the CPU 210 may share the memory module 223. The serial hub 120 may provide a portion of the memory of the memory module 223 for processing in the CPU 210. That is, the serial hub 120 may change the setting so as to allocate the part to the application of the CPU 210. The serial hub 120 may maintain allocation for the rest of the memory. The CPU 110 and the CPU 210 may share the memory module 223 at the same time.

In some other embodiments, the CPU 110 and the CPU 210 may share a memory module 226. The serial hub 120 may provide all of the memory of the memory module 226 for processing by the CPU 110. [ That is, the serial hub 120 may change the setting so that the memory is allocated to the application of the CPU 210 at another point in time so that the memory is allocated to the application of the CPU 110 at any one point in time. The CPU 110 and the CPU 210 may share the memory module 226 at another point in time. In other words, the CPU 110 and the CPU 210 can use the memory module 226 for different time intervals.

The serial hub 120 may determine the memory module to provide to the CPU based on the characteristics of each of the memory modules. The characteristics may include the type, capacity, and operating speed of the memory modules. The memory module may include an SDR (signal date rate) SDRAM, a double data rate (DDR) SDRAM, a DDR2 SDRAM, a DDR3 SDRAM, a DDR4 SDRAM, and a DDR5 SDRAM. The capacity of the memory module means a capacity of data that can be stored in one memory module. For example, the capacity of the memory module 221 may be 2 gigabytes (gigabytes). The capacity of the memory module 223 may be 6 GB. The operating speed of the memory module may be referred to as an operating clock. The operating speed may be a rate at which the memory module outputs data. For example, the operation speed of the memory module 222 may be 12800 MB / s (megabyte / second).

In the embodiment described with reference to FIG. 3, the allocation of memory modules or memory for CPUs 110 and 210 has been described as being performed by the serial hub 120. However, in other embodiments, the determination of the memory module or memory allocation, i. E., The amount of memory allocated to the operation of the CPUs 110 and 210, and the index of the allocated memory module, And routing according to the allocation result can be performed by the serial hub 120. [ In other words, at least one of the CPUs 110 and 210 may be involved in the memory module or memory allocation process.

Figure 4 illustrates an example of memory / ethernet switching of an electronic device according to various embodiments of the present disclosure. The electronic device may be the electronic device 100 of FIG. The serial hub 120 of the electronic device 100 may perform the memory / Ethernet switching.

Referring to FIG. 4, the serial hub 120 may be connected to the Ethernet modules 421 and 422. The serial hub 120 and the Ethernet module 421 may be connected through a serial line. The Ethernet module 421 may be an Ethernet module for ethernet communication. The Ethernet module may be an interface for connection between electronic devices. The Ethernet module 421 may be used in a local area network (LAN).

The electronic device 100 may be connected to another electronic device through the Ethernet module 421. The electronic device 100 can receive data from the other electronic device through the Ethernet module 421. [ Alternatively, the electronic device 100 may transmit data to the other electronic device through the Ethernet module 421. [

In order to communicate with the other electronic device, the electronic device 100 may be required to have an Ethernet interface. The Ethernet interface may be an interface supporting a serial protocol. As described above with reference to FIG. 1, the serial hub 120 may provide a memory interface supporting a serial protocol. Accordingly, the electronic device 100 can provide the Ethernet interface in addition to the memory interface for the memory module through the serial hub 120. [ The electronic device 100 may adaptively switch data communication through the Ethernet module in the data communication through the memory module through the serial hub 120.

For example, the CPU 110 can handle the operation of transmitting data to another device on the application being driven. The memory of the memory module 223 may be allocated to the application. In order for the CPU 110 to transfer data, the CPU 110 may be required to have an Ethernet interface. The CPU 110 can transmit data to the electronic device via the Ethernet module 421 connected to the serial hub 120 and the serial hub via the serial line without setting a separate path for a separate interface.

The serial hub 120 may set a protocol for the Ethernet module 421. The protocol for the Ethernet module 421 may be the same as the protocol for the first layer (layer 1) indicating a physical layer or the layer 2 indicating a link layer. The protocol for the Ethernet module 421 may be a protocol for the memory module 223. That is, the protocol may be a protocol applied to both the memory module 223 and the Ethernet module 421 in the first layer and the second layer. Thus, the protocol may be referred to as a hybrid serial protocol. Through the setting of the hybrid serial protocol, the serial hub 120 can provide a switch structure capable of connecting the memory module 223 and the Ethernet module 421 without discrimination.

The serial hub 120 may perform a direct memory access (DMA) function. The DMA function is a function that accesses the memory without direct intervention of the CPU. In order to perform the DMA function, the CPU 110 may transmit a control signal to the serial hub 120. The control signal is a signal for setting the serial hub 120 to perform a DMA function, and may designate a memory module for reading data and a memory module for writing data. Accordingly, the serial hub 120 can directly store the data in an arbitrary memory module upon receiving specific data based on the setting.

For example, referring to the flow 450, when the electronic device 100 receives data from the Ethernet module 421, it can directly store the data in the memory module 223 without direct intervention of the CPU 110. Specifically, the serial hub 120 of the electronic device 100 can receive data from another device via the Ethernet module 421. [ The serial hub 120 may store the data in a buffer. The serial hub 120 may not transmit the data to the CPU 110. The serial hub 120 may store the data in the memory module 224. That is, the data may not be transmitted to the CPU 110 but may be stored in the memory module 224. The serial hub 120 may transmit only a part of the data without transmitting the data. For example, the serial hub 120 may transmit information about an address storing the data to the CPU 110. [ Alternatively, the serial hub 120 may transmit to the CPU 110 information indicating that the movement of the data is completed. The electronic device 100 can reduce the operation of the CPU through the serial hub 120, thereby widening the utilization range of the CPU when using the Ethernet module.

5 illustrates an example of signal exchange between a serial hub and a memory module in accordance with various embodiments of the present disclosure. The serial hub may be the serial hub 120 of FIG. The memory module may be the memory module 225 of FIG.

Referring to FIG. 5, the serial hub 120 may include an ingress port 510 and an egress port 520. The entry port 510 and the exit port 520 may be operatively connected to a data path and a control path.

The ingress port 510 may be an ingress port for processing a packet. For example, the ingress port may be an ingress port for processing a memory address of the packet. The entry port 510 can check whether a packet is input in a memory range specified in a mapping unit (not shown) of the serial hub 120. The memory range may indicate a range for the memory address of the packet. The entry port 510 may add a tag to the packet so that the memory range is connected to the port. The entry port 510 may check the format of the packet. The entry port 510 may check whether the data is erroneous. The entry port 510 may forward the input packet to the mapping unit.

The exit port 520 may be an exit port for processing the memory address. The egress port 520 may receive packets from the mapping unit. The exit port 520 can determine whether to transmit a packet according to the status of the input / output port 540 after confirming the tag of the packet. The tag may be an identifier used for retransmission in the inside. The tag may be determined by the mapping unit.

The serial hub 120 may include an inter-integrated circuit (I ² C) 530. The serial hub 120 can manage the control path using I ² C 530. The control path may be a line for controlling data in the data path. The I ² C 530 may include two serial lines. The two serial lines may be SDA (serial data) lines and SCL (serial clock) lines. The SDA line may be a line representing bit information of data transmitted in the data path. The SDA line may be a bidirectional line whose direction is different depending on whether it is a data reading operation or a writing operation. The SCL line may be a line for transmitting a clock for transmitting the data. The SCL line may be a unidirectional line transmitted from the serial hub 120 to the memory module 225.

In some embodiments, the serial hub 120 may control a module coupled to the serial hub 120 via the I ² C 530. The serial hub 120 may obtain configuration information of the connected module through the I ² C 530. The serial hub 120 may configure the mapping unit based on the information. The connected module may be a memory module 225.

The serial hub 120 may include an input / output port 540. The input / output port 540 may be hardware for transferring data of the data path. The input / output port 540 may include a plurality of pins. The plurality of pins may be coupled to physical lines for transferring the data. The input / output port 540 may be connected to the serial lines through the plurality of pins. The input / output port 540 may be connected to the input / output port 550 of the memory module 225 through serial lines. The input / output port 540 can transmit / receive data to / from the input / output port 550 of the memory module 225 through the serial lines. The input / output port 540 may transmit or receive the data based on a rule determined by the mapping unit.

5 illustrates the connection relationship between the serial hub 120 and the memory module, but the present invention is not limited thereto. For example, the serial hub 120 may be connected to a module other than the memory module. As another example, the control path may be configured in a manner other than I ² C 530. When the serial hub 120 is connected to an Ethernet module, the serial hub 120 can manage a control path through a media independent interface (MII).

Figure 6 illustrates an example of the functional configuration of a serial hub in accordance with various embodiments of the present disclosure. The serial hub may be the serial hub 120 of FIG.

6, the serial hub 120 may include ports 540-1 through 540-6, a mapping unit 610, a buffer 620, and a controller 630. [ The mapping unit 610, the buffer 620, and the controller 630 may be operatively coupled to the ports 540-1 through 540-6, respectively. Hereinafter, a case where the serial hub 120 and the memory module 225 of FIG. 5 are connected by serial lines will be described.

The ports 540-1 through 540-6 may be components that physically couple the serial hub 120 to other modules (e.g., a memory module, an Ethernet module, etc.) and a CPU. Each of the ports 540-1 to 540-6 is composed of at least one pin, and may be an entry port or an exit port depending on the data input / output state. The ports 540-1 through 540-6 support a serial interface, and may support SERDES (serialize-deserialize), for example.

The mapping unit 610 may connect the CPU and the modules using a mapping rule between the ports 540-1 to 540-6. That is, the mapping unit 610 sets the paths between 540-1 and 540-6 according to the mapping rule. The mapping rule determines whether data input to one of the ports 540-1 through 5406- should be output to which of the ports 540-1 through 540-6, in other words, 540-6 indicate what the corresponding outlet port is when each is an entry port. The mapping unit 610 may be referred to as various terms. For example, the mapping unit 610 may be referred to as an MMU (memory management unit). As another example, the mapping unit 610 may be referred to as a mapper.

Also, the mapping unit 610 may convert a virtual address of data into a physical address. The virtual address may be an address for identifying a virtual memory of the data. The virtual address may be referred to as a logical address. The physical address may be an address for identifying a physical memory in which the data is actually stored. The physical memory means a memory provided by the memory module 225. [ The physical address may be referred to as a real address. The mapping unit 610 can perform a logical connection between the CPU and the module through an address conversion operation.

The buffer 620 may temporarily store packets received through at least one of the ports 540-1 through 540-6. The temporarily stored packet may be output to the egress port 520 under the control of the controller 630. The temporarily stored data may be output to the egress port 520 according to a rule set by the mapping unit 610. The buffer 620 may include a translation lookaside buffer (TLB). The conversion reference buffer may be a space for storing a page table that is mapped recently. The mapping unit 610 may convert the virtual address into the physical address using the conversion reference buffer.

In some embodiments, the buffer 620 may store data received from the memory module 225. For example, the data received from the memory module 225 may be data for the CPU 110 to process. As another example, data received from the memory module 225 may be data for the electronic device 100 to store in another memory module. In some other embodiments, the buffer 620 may store data received from the Ethernet module 421. The data received from the Ethernet module 421 may be data received from another electronic device.

The controller 630 may be configured to control the serial hub 120. The controller 630 may control the mapping unit 610 or the buffer 620 of the serial hub 120. The controller 630 may control the internal settings of the serial hub 120. In some embodiments, the controller 630 may receive a setup signal from the CPU 110. [ The controller 630 may control the setting of the serial hub 120 based on the setting signal. The setting signal may be a signal for internal setting of the serial hub 120.

In order to access the control unit 630, the CPU 110 may transmit a control signal to the serial hub 120. [ In some embodiments, the CPU 110 may transmit the control signal through the ports 540-1 through 540-6. In this case, the control signal may have the form of a specific packet that is interpreted as control information at the ingress port. In some other embodiments, the CPU 100 may transmit the control signal through a separate control path. For example, the CPU 110 may transmit the control signal through I ² C. As another example, the CPU 110 may transmit the control signal through the MII.

The controller 630 may determine at least one memory module to be provided to the CPU 110 among the plurality of memory modules. Also, the controller 630 may determine distribution of memory resources. The controller 630 may determine a first memory and a second memory to be allocated based on a first signal according to the operation of the CPU 110 and a second signal according to the operation of the CPU 210, respectively. The first memory is a memory allocated for the operation of the CPU 110. The second memory is a memory allocated for the operation of the CPU 210. In some embodiments, the controller 630 may determine the first memory and the second memory based on the nature, type, and processing size of each of the operations of the CPU 110 and the operation of the CPU 210.

The controller 630 may perform memory sharing. In some embodiments, the controller 630 may provide a first memory region of the same memory module to the CPU 110 and a second memory region to the CPU 210. In some other embodiments, the controller 630 may provide the memory of the same memory module to the CPU 110, and then provide the memory to the CPU 210. Accordingly, the electronic device 100 can efficiently utilize a plurality of memory modules in terms of space.

The controller 630 can simultaneously perform an operation of reading data stored in the memory module and an operation of storing data in the memory module. That is, the controller 630 can perform a reading operation and a writing operation through the serial lines. The electronic device 100 can simultaneously use the memory resources and the CPU by performing the read operation and the write operation at the same time.

The controller 630 may control the switching between the Ethernet module and the memory module. The Ethernet module may be an Ethernet module 421. The memory module may be the memory module 225. The controller 630 can communicate with the memory module 225 or the Ethernet module 421 through a serial line at the request of the CPU. The controller 630 may operate on an interface having both a memory interface for memory allocation and an Ethernet interface for Ethernet communication. The interface may be a serial interface. The interface may support SERDES (serialize-deserialize). The controller 630 may be connected to each of the Ethernet module 421 and the memory module 225 by a serial line. The controller 630 can perform serial communication with the Ethernet module 421 or the memory module 225 through the serial line and the serial interface.

The controller 630 may operate according to a protocol compatible with both the memory interface and the Ethernet interface. For example, the protocol may be a serial line internet protocol (SLIP). The protocol may be referred to as a hybrid serial protocol. The hybrid serial protocol may be a protocol applied to the first layer or the second layer. For example, the protocol applied to the first layer may be a 10GBASE-KR Ethernet protocol. The controller 630 may set the hybrid serial protocol according to a control signal received from the CPU 110. [

The controller 630 may perform a DMA function. The controller 630 can store the data received from the Ethernet module 421 in the memory module without transmitting the data to the CPU 110 or the CPU 210. [ The electronic device 100 can reduce the operation of the CPU through the DMA function. The electronic device 100 can increase the utilization of the CPU by reducing the CPU operation.

6, the serial hub 120 includes the mapping unit 610, but the present invention is not limited thereto. In some embodiments, the serial hub 120 may not include the mapping unit 610. For example, the function of the mapping unit 610 may be performed by the CPU 110. The serial hub 120 receives information on the converted address, and the controller 630 of the serial hub 120 can use the received information to determine a memory module to store data. In another example, the mapping unit 610 may be configured as separate hardware.

FIG. 7 illustrates an example of a read operation or a write operation of an electronic device according to various embodiments of the present disclosure. The electronic device may be the electronic device 100 of FIG. The electronic device 100 may include a CPU 110, a serial hub 120, a memory module 221, and a memory module 222.

The CPU 110 may configure the serial hub 120. The CPU 110 may configure the serial hub 120 during a period 710. For example, the CPU 110 may set the mapping unit 610 of FIG. 6 during the interval 710. For example, the CPU 110 may set the protocol of the controller 630 of FIG. 6 during the interval 710. For example, the CPU 110 may set the input / output port 540 of FIG. 5 during the interval 710.

The CPU 110 can perform a write operation. The CPU 110 may perform the write operation during the interval 720. The writing operation may be an operation in which the CPU 110 stores the first data in the memory module 221.

Specifically, in operation 721, the CPU 110 may transmit the first data to the serial hub 120. The CPU 110 may additionally transmit a control signal for the write operation to the serial hub 120. [ In some embodiments, the CPU 110 may transmit only a control signal for the DMA function to the serial hub 120. [

In operation 722, the serial hub 120 may store the first data in a buffer. The buffer may be the buffer 620 of FIG. In some embodiments, when the serial hub 120 receives a control signal for a DMA function, the serial hub 120 may receive the first data from another module. For example, the serial hub 120 may receive the first data from the memory module 223 of FIG. In another example, the serial hub 120 may receive the first data from the Ethernet module 421 of FIG. The first data may be data received from the other electronic device.

In operation 723, the serial hub 120 may transmit the first data to the memory module 221. The serial hub 120 may determine the address of the memory module in which the first data is to be stored, as set by the CPU 110. The address may be a physical address. The serial hub 120 may transmit the first data to the memory module 221 based on the determined physical address.

The serial hub 120 may serialize the first data. The serial hub 120 may transmit the first data to the memory module 221 through a serial line. The serial hub 120 can transmit the data to the memory module 221 through a transmission serial line in the serial line. The serial hub 120 can transmit the first data to the memory module 221 through the serial line regardless of whether the memory module 222 is operated or not.

In operation 724, the memory module 221 may receive the first data. The memory module 221 may deserialize the received first data. The memory module 221 may store the desalinated first data in the memory of the memory module 221. If the first data is stored in the memory of the memory module 221, the writing operation of the CPU 110 may be terminated. In some embodiments, the memory module 221 may send an ACK (acknowledge) signal to the CPU 110 indicating that the write operation has been successfully terminated.

The CPU 110 may perform a read operation. The CPU 110 may perform the read operation during the interval 730. The read operation may be an operation in which the CPU 110 receives the second data from the memory module 222.

Specifically, in operation 731, the CPU 110 may send a request signal to the serial hub 120. [ The request signal may be a control signal for the read operation. The control signal may be referred to as a data transmission request.

In operation 732, the serial hub 120 may store the control signal in a buffer. The buffer may be the buffer 620 of FIG.

In operation 733, the serial hub 120 may send the control signal to the memory module 222. The control signal may include information indicating a virtual address for the second data. The serial hub 120 may generate information indicating a physical address of the second data based on information indicating a virtual address of the second data. The serial hub 120 may determine a memory module for the physical address. The memory module may be the memory module 222. That is, the serial hub 120 may transmit the control signal to the memory module 222 based on the determined physical address.

In operation 734, the memory module 222 may receive the control signal. The memory module 222 may determine the second data based on the received control signal. The memory module 222 may search for the second data among a plurality of memory cells included in the memory module 222. When the memory module 222 retrieves the second data, the memory module 222 may serialize the second data.

In operation 735, the memory module 222 may transmit the serialized second data to the serial hub 120. [

In operation 736, the serial hub 120 may store the second data in the buffer 620.

In operation 737, the serial hub 120 may transmit the second data to the CPU 110. When the CPU 110 receives the second data, the read operation can be terminated.

The CPU 110 may simultaneously perform a write operation and a read operation during the interval 740. The CPU 110 can independently perform data communication with each of the memory modules through the serial hub 120. The serial hub 120 is connected to each of the memory modules through serial lines instead of the parallel bus, thereby enabling independent data communication. That is, the electronic device 100 can use the memory resources of the memory module 221 and the memory module 222 at the same time. The electronic device 100 can utilize the memory resources efficiently through the serial hub 120. [

Figure 8 shows an example of a hierarchical structure for memory / Ethernet switching.

Referring to FIG. 8, the first layer indicates a physical layer. The second layer represents the link layer. The third layer represents an application layer. The electronic device can use an application that uses both a memory module and an Ethernet module. For example, the electronic device may use an application 850 for storing data received from another electronic device in a memory module.

The hierarchy 810 represents a hierarchical structure of a conventional Ethernet interface. The hierarchy 820 represents a hierarchical structure of a conventional memory interface. When the electronic device uses the application 850, the electronic device can request data from the other electronic device. The electronic device can receive data via the Ethernet interface and store the received data in a memory. At this time, the electronic device may be required to access a separate interface for storing the data in the memory. For example, the electronic device can access the memory using a memory interface which is an interface other than the Ethernet interface. In other words, the CPU included in the electronic device can access the memory interface through another path. The CPU can access the memory module via the memory interface and then store the data.

The hierarchy 830 represents a hierarchical structure of interfaces of the serial hub 120, according to various embodiments. The interface of the serial hub 120 may be a memory / internet interface. Here, the memory / Ethernet interface may be referred to as a hybrid serial interface. According to the hierarchy 830, the application layer 850 of the memory module and the Ethernet module are separated, but the protocols of the link layer and the physical layer are common. That is, the memory module and the Ethernet module use the same link layer and physical layer protocol. For example, the hybrid serial protocol can be implemented as a serial line interface (e.g., 10GKR-BASE) in the physical layer. Since the protocol of the physical layer is common, the memory module and the Ethernet module can be connected to the serial hub 120 according to various embodiments without any distinction. Further, since the protocol of the physical layer is common, a switch and a relay configuration between the memory module and the Ethernet module are possible. The link layer protocol is designed to accommodate memory modules and Ethernet modules. These link layer protocols can be configured only with driver modifications below the kernel.

According to various embodiments, the electronic device 100 may use an application that uses both a memory module and an Ethernet module. The memory module may be used for data storage. The Ethernet module may be used for data communication with other devices. The application may be the application 850.

The electronic device 100 may use an Ethernet interface to perform communications with other electronic devices. The electronic device 100 can receive data through the Ethernet module. The Ethernet module may be the Ethernet module 421 of FIG. To store the data in the memory module 223, the serial hub 120 may require a memory interface. The serial hub 120 may store the data in the memory module 223 through the memory interface.

The serial hub 120 may set a protocol for memory allocation and a protocol for Ethernet communication. The protocol may be referred to as the hybrid serial protocol of FIG. The hybrid serial protocol may be a protocol for the first layer and the second layer.

The electronic device 100 can store data without using a separate path for the heterogeneous interface. The electronic device 100 may receive the data from another device on the interface of the serial hub 120 and store the data in memory. The electronic device 100 may configure one interface through the serial hub 120. The serial hub 120 may be connected to both the Ethernet module 421 and the memory module 223 through a serial line. The serial hub 120 may configure a serial interface to be connected to the serial line.

9 shows a flow of an electronic device according to various embodiments of the present disclosure. The electronic device may be the electronic device 100 of FIG. The electronic device 100 may include the CPU 110, the serial hub 120, the memory module 130, and the memory module 140 of FIG. The serial hub 120 may be connected to the CPU 110, the memory module 130, and the memory module 140 through a serial line, respectively.

9, in operation 910, the serial hub 120 may receive a signal from the CPU 110. In operation, The serial hub 120 can receive the signal in a serial communication manner. In some embodiments, the signal may be a signal requesting storage of data. In some other embodiments, the signal may be a signal requesting data stored in a memory module. In some other embodiments, the signal may be a signal for configuring the serial hub 120. The serial hub 120 may set a specific protocol based on the signal. For example, the serial hub 120 may establish a protocol for a memory interface based on the signal. As another example, the serial hub 120 may set a protocol for the Ethernet interface based on the signal. As another example, the serial hub 120 may be configured to perform a DMA function based on the signal. The serial hub 120 may be configured to store the specific data in the memory module 140 without transmitting the specific data to the CPU 110 upon receipt of the specific data.

In operation 920, the serial hub 120 may determine a memory module for the CPU 110 among a plurality of memory modules based on the signal.

In some embodiments, the serial hub 120 may determine a memory module for a write operation based on the signal. The signal may be a signal requesting storage of data. The serial hub 120 may determine a memory module for the write operation among a plurality of memory modules. The plurality of memory modules may include the memory module 130 and the memory module 140. The serial hub 120 may store the data in the memory module 130. The serial hub 120 may store the data in the memory module 130 through a serial communication method. The serial hub 120 may store the data in the memory module 130 via a transmission serial line.

In some other embodiments, the serial hub 120 may determine the memory module for a read operation based on the signal. The signal may be a signal requesting a call of data. The serial hub 120 may search the memory module 140 in which the data is stored among the plurality of memory modules. The serial hub 120 can transmit a signal requesting the data to the memory module 140 through a serial communication method. The serial hub 120 may receive the data from the memory module 140 based on a signal requesting the data. The serial hub 120 can receive the data from the memory module 140 through a serial communication method. The serial hub 120 may receive the data from the memory module 130 via a receive serial line.

10 illustrates a flow of memory sharing of an electronic device in accordance with various embodiments of the present disclosure. The electronic device may be the electronic device 100 of FIG. The electronic device 100 may include the CPU 110, the CPU 210, the serial hub 120, and the memory modules 221, 222, 223, 224, 225, and 226 shown in FIG. The serial hub 120 may be connected to the CPU 110, the CPU 210, and the plurality of memory modules (the memory modules 221, 222, 223, 224, 225, and 226, respectively) by a serial line. The serial hub 120 can independently perform data communication with each of the plurality of memory modules via the serial line.

Referring to FIG. 10, in step 1010, the serial hub 120 may receive a first signal from a first CPU. The first CPU may be the CPU 110. In some embodiments, the first signal may be a signal requesting storage of data. In some other embodiments, the first signal may be a signal requesting a call of stored data.

In step 1020, the serial hub 120 may receive a second signal from the second CPU. The second CPU may be the CPU 210. In some embodiments, the second signal may be a signal requesting storage of data. In some other embodiments, the second signal may be a signal requesting a call of stored data.

In step 1030, the serial hub 120 determines a first memory module for the CPU 110 and a second memory module for the CPU 210 among the plurality of memory modules based on the first signal and the second signal . The first memory module may be a memory module 221. The second memory module may be a memory module 222.

In some embodiments, the serial hub 120 may determine the memory module 221 and the memory module 222, respectively, based on the magnitude of the first data for the first signal and the magnitude of the second data for the second signal have. For example, if the size of the first data is larger than the size of the second data, the serial hub 120 may allocate the capacity of the memory allocated to the processing of the first data to the memory allocated to the processing of the second data The memory module 221 and the memory module 22 can be respectively determined.

In some other embodiments, the serial hub 120 may determine the memory module 221 and the memory module 222 based on the type of the first data and the type of the second data. The serial hub 120 may determine the memory module 221 and the memory module 222 based on at least one of memory capacity, operation speed, and type of each of the plurality of memory modules. For example, when the first data is data related to a service requiring faster processing than the second data, the memory of the memory module 221, which has a higher operation speed than the memory module 222, Can be assigned to the processing operation.

11 illustrates the flow of Ethernet communication of an electronic device according to various embodiments of the present disclosure. The electronic device may be the electronic device 100 of FIG. The electronic device 100 includes the CPU 110 of FIG. 4, the CPU 210 of FIG. 4, the serial hub 120 of FIG. 4, the Ethernet modules 421 and 422 of FIG. 4, and the memory modules 223, 224, 225 and 226 can do. The serial hub 120 may be connected to the CPU 110, the CPU 210 and the plurality of modules (the Ethernet modules 421 and 422 and the memory modules 223, 224, 225 and 226, respectively) by a serial line. The serial hub 120 can independently transmit and receive data to and from the plurality of memory modules and the Ethernet modules through the serial line.

In step 1110, the serial hub 120 may receive an Ethernet signal from the CPU 110. The Ethernet signal may be a signal to be coupled to another electronic device. In some embodiments, the Ethernet signal may be a signal for transmitting data to the other electronic device. In some other embodiments, the Ethernet signal may be a signal for requesting data from the other electronic device.

In step 1120, the serial hub 120 may transmit data to or receive data from another electronic device through the Ethernet module 421 based on the Ethernet signal. That is, the serial hub 120 can communicate with other electronic devices through the Ethernet module 421. The serial hub 120 may include an Ethernet interface.

The serial hub 120 may be connected to the Ethernet modules 421 and 422 through at least one line for serial communication. have. The serial hub 120 may be connected to the memory modules 223, 224, 225, and 226 in at least one line for serial communication. That is, the serial hub 120 may also include a memory interface. The serial hub 120 may be connected to each of the Ethernet modules 421 and 422 independently of the memory modules 223, 224, 225, and 226 through the at least one line. The serial hub 120 may include one interface for an Ethernet module and a memory module.

12 shows an example of a connection between a serial relay and a target device. The serial relay may be a serial relay 1210. The serial relay 1210 may have a structure capable of providing various interfaces according to an applied setting signal. The serial relay 1210 may be referred to as a configurable serial relay.

Referring to FIG. 12, the serial relay 1210 may be connected to the target device 1220. The target device 1220 may be a device implemented as a board or a card. For example, the target device may be a card including a memory module. As another example, the target device may be a board including an Ethernet module. As another example, the target device may be a board including a CPU. As another example, the target device may be a card including a graphics processor unit (GPU). As another example, the target device may be a board including both a memory module and an Ethernet module.

The serial relay 1210 may be connected to the target device 1220 through an input / output port. The serial relay 1210 may include at least one input / output port. The at least one input / output port may be an input / output port connected to at least one serial line. The serial relay 1210 may be connected to the target device 1220 through the at least one input / output port and the at least one serial line. In some embodiments, the at least one input / output port may include at least one channel. For example, the at least one channel may be four channels. As another example, the at least one channel may be eight channels. As another example, the at least one channel may be 32 channels. The number of channels may represent a bandwidth for data transmission. The serial relay 1210 can adaptively distribute channels for each module as needed. The channel may be referred to as a lane. Or the channel may be referred to as a pin.

The serial relay 1210 can perform serial communication. The serial relay 1210 may be connected to the target device 1220 via the at least one serial line. The serial relay 1210 can perform serial communication with the target device 1220 through the serial line. The serial relay 1210 can transmit data through the serial communication. In this case, the serial relay 1210 may function as a buffer for temporarily storing the data for transmission of the data.

The serial relay 1210 is connected to the target device 1220 in a serial manner, so that the serial relay 1210 can operate independently of other connections. That is, the serial relay 1210 can determine whether to operate with the target device 1220 regardless of whether the other memory module or another Ethernet module is operating.

In some embodiments, the serial relay 1210 may be a relay for connection between boards / cards and expansion of the module. The serial relay 1210 may support an additional connection of the module. For example, the serial relay 1210 may connect a board including a CPU and a board including a first memory module. The serial relay 1210 may additionally connect a second memory module. The serial relay 1210 may be connected to the board including the CPU, the first memory module, and the second memory module by a serial line.

The serial relay 1210 may serve as a repeater. The serial relay 1210 may perform the function of the repeater to support communication between the modules extended by the serial connection. The serial relay 1210 can amplify a data transmission signal for communication with a module connected at a relatively long distance.

In some other embodiments, the serial relay 1210 may be a relay for expansion of the Ethernet interface at the memory interface. The serial relay 1210 may provide both an interface for memory allocation and an interface for Ethernet connection. For example, the serial relay 1210 can connect a board including a CPU and a board including an Ethernet module.

13 shows an example of the connection of a serial relay and a plurality of target devices. The serial relay may be the serial relay 1210 of FIG. The plurality of target devices may include the target device 1220 and the target device 1320 of FIG.

Referring to FIG. 13, a block diagram 1300 illustrates the connection between the relay 1210 and the target device 1220 and the target device 1320. The relay 1210 may include an input / output port 1215. The input / output port 1215 may have two channels. The two channels may be channels for performing serial communication. The target device 1220 may include an input / output port 1225. The input / output port 1225 may have four channels. The input / output port 1225 may include an input / output port 1225a corresponding to two channels and an input / output port 1225b corresponding to two channels. The target device 1320 may include an input / output port 1325. The input / output port 1325 may have four channels.

The relay 1210 may perform serial communication with the target device 1220. The relay 1210 can perform serial communication with the target device 1220 through the input / output port 1215. The relay 1210 can perform serial communication with the target device 1220 through two channels. The target device 1220 can perform serial communication with the relay 1210 through the input / output port 1225a.

The target device 1220 may perform serial communication with the target device 1320. The target device 1220 can perform serial communication with the target device 1320 through the input / output port 1225b. The input / output port 1225b may be an input / output port for a relay function. The target device 1220 can perform serial communication with two input channels. The target device 1320 may perform serial communication with the target device 1220 through the input / output port 1325.

For example, the relay 1210 may send a signal to the target device 1220. The target device 1220 may send a signal received from the relay 1210 to the target device 1320. The target device 1220 may transmit the signal to the target device 1320 via two channels. The target device 1330 may receive the signal from the target device 1220.

In some embodiments, the target device 1320 may use all four channels of the input / output port 1325. The target device 1220 uses two channels, but the target device 1320 can perform serial communication using four channels. The serial communication may be a synchronous serial communication.

In some other embodiments, the target device 1320 may use only two of the four channels of the input / output port 1325. The target device 1220 and the target device 1320 can perform serial communication using only two channels. The serial communication may be an asynchronous serial communication.

In addition, the target device 1320 may use two of the four channels of the input / output port 1325 for signal reception and the other two channels for transmission of the signal. Although not shown in FIG. 13, the target device 1330 may transmit signals to other target devices through input / output ports corresponding to the other two channels of the input / output port 1325. In this manner, the relay 1210 may be capable of continuous addition of a plurality of target devices. The connection of the plurality of target devices may be referred to as a cascade connection. The relay 1210 may amplify the signal to deliver a signal to a target device at a relatively long distance due to the cascade connection. That is, the relay 1210 may serve as a repeater.

Block diagram 1350 illustrates the logical connection between the relay 1210 and the target device 1220 and the target device 1320. The relay 1210 may be operatively coupled to the target device 1220 and the target device 1320. The electronic device 100 may extend the target devices through the relay 1210 in a serial communication manner as needed.

14 illustrates embodiments of a serial relay in accordance with various embodiments of the present disclosure. The serial relay may be the serial relay 1210 of FIG. 14A, 14B, 14C, and 14D show embodiments according to the configuration of the serial relay 1210, respectively.

14A illustrates one embodiment of a serial relay 1210 that supports one interface.

Referring to FIG. 14A, the serial relay 1210 may be connected to a board 1410 including a CPU by a serial line. For example, when the serial relay 1210 is connected to the CPU, the serial relay 1210 may be connected to the serial line through an edge portion of each board. As another example, the serial relay 1210 may be connected to an external serial line of the CPU and the board. The CPU may include a memory controller. The serial relay 1210 may be connected to a board 1420 including a memory module by a serial line. The serial relay 1210 may support a memory interface configured with a serial interface.

The serial relay 1210 may be connected to a board 1410 including a CPU by a serial line. The CPU may be a CPU having an Ethernet controller incorporated therein. The serial relay 1210 may be connected to the board 1425 including the Ethernet module by a serial line. The Ethernet module may be referred to as an ethernet phy. The serial relay 1210 may support an Ethernet interface configured with a serial interface.

The serial relay 1210 may support a serial interface. For example, in the physical layer, the serial interface may be 10G-KR or 40G-KR. The serial relay 1210 is configurable in accordance with a module for supporting the serial interface. In some embodiments, when the serial relay 1210 is coupled to the board 1420, the relay 1210 may be configured as a memory interface. In some other embodiments, when the serial relay 1210 is connected to the board 1425, the relay 1210 may be set to an Ethernet interface. The relay 1210 may be set to a specific impression based on a control signal received from the CPU.

14B illustrates an embodiment of a serial relay 1210 that supports multiple interfaces.

The serial relay 1210 may be connected to a board 1430 including a CPU by a serial line. The CPU may be a CPU including both a memory controller and an Ethernet controller. The serial relay 1210 may be connected to the board 1440 through a serial line. The board 1440 may be a board including both a memory module 1443 and an Ethernet module 1445.

The serial relay 1210 may be configured to implement a protocol that supports both a memory interface and an Ethernet interface. The protocol may be a protocol for at least one of a physical layer and a data link layer. In some embodiments, the serial relay 1210 may be configured to implement a protocol for a memory interface. In some other embodiments, the serial relay 1210 may be configured to implement a protocol for an Ethernet interface. In some other embodiments, the serial relay 1210 may be configured to implement a protocol that supports both a memory interface and an Ethernet interface. The serial relay 1210 can simultaneously perform data communication with the memory module 1443 and the Ethernet module 1445. The serial relay 1210 can implement a protocol adaptively according to the setting.

The CPU can transmit a control signal for setting the relay.

14C shows an example of a cascade connection of the serial relay 1210. Fig.

The serial relay 1210 may be connected to a board 1450 including a CPU by a serial line. The CPU may be a CPU including a memory controller. The serial relay 1210 may be connected to the board 1460 through a serial line. The board 1460 may be a board including a memory module 1461, a memory module 1463, and a memory module 1465.

The memory module 1461, the memory module 1463, and the memory module 1465 may be connected to the serial relay 1210 in a dependent manner. Specifically, the relay module 1210 may be connected to the memory module 1461 by a serial line. The memory module 1461 may be connected to the memory module 1463 by a serial line. The memory module 1463 may be connected to the memory module 1465 through a serial line.

The relay 1210 may be transmitted to the memory 1465 via the memory module 1461 and the memory module 1463 when a signal is transmitted to the memory module 1465. In some embodiments, the relay 1210 may amplify the output of the signal to transmit a signal to the memory module 1465 that is relatively far away.

The relay 1210 may receive a signal for data from the CPU. The signal for the data may be a signal for requesting data. The relay 1210 can sequentially transmit signals for the data to the memory module 1461, the memory module 1463, and the memory module 1465.

In some embodiments, the relay 1210 may determine an amount of memory resource allocation for the data. For example, the signal for the data may be a signal for storing 3 data in the memory module 1461, 5 data in the memory module 1463, and 2 data in the memory module 1465. The memory module 1461 may store the 3 pieces of data when the signal is received. Then, the memory module 1461 can transmit the signal to the memory module 1463 as it is. The memory module 1463 may store the data of 5 and then transmit the signal to the memory module 1465 as it is. The memory module 1465 may store the data of the two.

In some other embodiments, the relay 1210 may receive an indication signal from the CPU indicating an amount of allocation of data for each of the memory modules. The subsequent operation may be the same as the operation in the case of receiving the signal for the data.

14D shows an example of a cascade connection of a serial relay 1210 supporting multiple interfaces.

The serial relay 1210 may be connected to a board 1470 including a CPU by a serial line. The CPU may be a CPU including a memory controller and an Ethernet controller. The serial relay 1210 may be connected to the board 1480 through a serial line. The board 1460 may be a board including a memory module 1481, an Ethernet module 1483, and a memory module 1485.

The memory module 1481, the Ethernet module 1483, and the memory module 1485 may be connected to the serial relay 1210 in a dependent manner. Specifically, the relay module 1210 may be connected to the memory module 1481 via a serial line. The memory module 1481 may be connected to the memory module 1483 by a serial line. The memory module 1483 may be connected to the memory module 1485 by a serial line.

The relay 1210 may be transmitted to the memory 1485 via the memory module 1481 and the Ethernet module 1483 when a signal is transmitted to the memory module 1485. In some embodiments, the relay 1210 may amplify the output of the signal to transmit a signal to the memory module 1485 that is relatively far away.

The relay 1210 may receive an Ethernet signal for data from the CPU. The Ethernet signal may be a signal for requesting the data to another electronic device. The relay 1210 can sequentially transmit a signal for the data to the memory module 1481, the Ethernet module 1483, and the memory module 1485. When receiving the Ethernet signal, the memory module 1481 can transmit the signal to the Ethernet module 1483 as it is. The Ethernet module 1483 may be coupled to the other electronic device based on the signal. The Ethernet module 1483 can transmit the Ethernet signal to the memory module 1485 independently of being connected to other electronic devices. In this case, the serial relay 1210 may be configured to implement a protocol supporting both a memory interface and an Ethernet interface.

Although the board has been described with reference to Fig. 14, the present invention is not limited thereto. That is, the operation of the relay 1210 may be applied to the card instead of the board.

While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. Therefore, the scope of the present disclosure should not be limited to the embodiments described, but should be determined by the scope of the appended claims, as well as the appended claims.

It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. Accordingly, the scope of the present invention should be construed as being included in the scope of the present invention, all changes or modifications derived from the technical idea of the present invention.

Claims (20)

In an electronic device,
A central processing unit (CPU)
A plurality of memory modules,
And a serial hub connected to each of the CPU, the plurality of memory modules, and at least one line for performing serial communication,
The CPU is configured to transmit a signal to the serial hub,
Wherein the serial hub is configured to determine, based on the signal, a first memory module for the CPU among the plurality of memory modules,
The method according to claim 1,
Further comprising another CPU connected to the serial hub as at least one line for performing serial communication,
The other CPU is configured to transmit another signal to the serial hub,
Wherein the serial hub is further configured to determine a first memory module and a second memory module for the other CPU among the plurality of memory modules based on the signal and the other signal.
The method according to claim 1,
Further comprising another CPU connected to the serial hub as at least one line for performing serial communication,
The other CPU is configured to transmit another signal to the serial hub,
Wherein the serial hub is further configured to determine, based on the signal and the other signal, a first memory area to be provided to the CPU and a second memory area to be provided to the other CPU from among the memory areas of the first memory module Lt; / RTI >
The method according to claim 1,
Further comprising another CPU connected to the serial hub as at least one line for performing serial communication,
The CPU is further configured to transmit a control signal to the serial hub,
Wherein the serial hub is further configured to provide a memory of the first memory module to the other CPU based on the control signal.
The method according to claim 1,
Further comprising an ethernet module connected to the serial hub as at least one line for performing serial communication,
Wherein the CPU is further configured to transmit an Ethernet signal to the serial hub for communicating with another electronic device,
Wherein the serial hub is further configured to send data to or receive data from the other electronic device via the Ethernet module based on the Ethernet signal.
The method of claim 5,
The serial hub includes:
And to transmit the received data to a third one of the plurality of memory modules without transmitting the received data to the CPU.
The method according to claim 1,
The serial hub includes:
And store, via the at least one line, the data indicated by the signal in the determined first memory module.
The method according to claim 1,
The serial hub includes:
And to receive data from the determined first memory module via the at least one line and to transmit the received data to the CPU.
The method according to claim 1,
Wherein the at least one line for performing the serial communication comprises:
A transmit serial line through which signals are transmitted from the serial hub to each of the plurality of memory modules,
A receive serial line through which signals are transmitted from the plurality of memory modules to the serial hub,
And a ground serial line for matching the voltage levels of the serial hub and the plurality of memory modules, respectively.
The method according to claim 1,
Wherein the serial hub comprises a memory management unit (MMU) configured to convert a virtual address for the signal to a physical address.
A method of operating an electronic device,
Wherein the serial hub of the electronic device receives a signal from a central processing unit (CPU) of the electronic device,
Wherein the serial hub comprises: determining, based on the signal, a first memory module for the CPU among a plurality of memory modules of the electronic device,
Wherein the serial hub is connected to at least one line for performing serial communication with the CPU and each of the plurality of memory modules.
The method of claim 11,
Receiving another signal from another CPU of the electronic device;
Further comprising determining, based on the signal and the other signal, a first memory module and a second memory module for the other CPU among the plurality of memory modules,
And the other CPU is connected to the serial hub by at least one line for performing serial communication.
The method of claim 11,
Receiving another signal from another CPU of the electronic device;
Further comprising determining, based on the signal and the other signal, a first memory area to be provided to the CPU and a second memory area to be provided to the other CPU, among the memories of the first memory module,
And the other CPU is connected to the serial hub by at least one line for performing serial communication.
The method of claim 11,
Receiving a control signal from another CPU of the electronic device,
Further comprising providing the memory of the first memory module to the other CPU based on the control signal,
And the other CPU is connected to the serial hub by at least one line for performing serial communication.
The method of claim 11,
Receiving an ethernet signal from the CPU to communicate with another electronic device;
Further comprising transmitting, based on the Ethernet signal, data to or from the other electronic device via an Ethernet module of the electronic device,
Wherein the Ethernet module is connected to the serial hub by at least one line for performing serial communication.
16. The method of claim 15,
Further comprising transmitting the received data to a third one of the plurality of memory modules without transferring the received data to the CPU.
The method of claim 11,
Further comprising converting a virtual address for the signal to a physical address.
In an electronic device,
A first board including a central processing unit (CPU)
And a second board including a first memory module, a second memory module, and a serial relay,
The CPU being configured to send a signal to the serial relay,
Wherein the serial relay is configured to amplify the signal and to transmit the amplified signal to the first memory module,
Wherein the first memory module is configured to transmit the amplified signal to the second memory module,
Wherein the serial relay is connected to the CPU and the first memory module as at least one line for performing serial communication,
Wherein the second memory module is connected to the first memory module with at least one line for performing serial communication.
19. The method of claim 18,
Wherein the serial relay is further configured to determine first data to be stored in the first memory module and second data to be stored in the second memory module,
Wherein the signal is a signal requesting storage of the first data and the second data.
19. The method of claim 18,
The second board further comprises an Ethernet module for performing communication with another electronic device,
The CPU is configured to transmit an Ethernet signal to the serial relay,
Wherein the serial relay is configured to amplify the Ethernet signal and to transmit the amplified Ethernet signal to the first memory module,
Wherein the first memory module is configured to transmit the amplified Ethernet signal to the Ethernet module,
Wherein the Ethernet module is configured to communicate with the other electronic device based on the amplified Ethernet signal,
Wherein the Ethernet module is connected to the first memory module via at least one line for performing serial communication.

Images