CN112947857B - Data moving method, device, equipment and computer readable storage medium - Google Patents
Data moving method, device, equipment and computer readable storage medium Download PDFInfo
- Publication number
- CN112947857B CN112947857B CN202110211367.8A CN202110211367A CN112947857B CN 112947857 B CN112947857 B CN 112947857B CN 202110211367 A CN202110211367 A CN 202110211367A CN 112947857 B CN112947857 B CN 112947857B
- Authority
- CN
- China
- Prior art keywords
- data
- flow control
- data transfer
- moving
- task
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0647—Migration mechanisms
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0626—Reducing size or complexity of storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Bus Control (AREA)
Abstract
The invention discloses a data moving method, which comprises the following steps: receiving configuration information corresponding to the target data transfer task; analyzing the configuration information to obtain a source address, a destination address and a flow control type; judging whether the flow control type is an external flow control type; if so, when a data transfer request sent by the target peripheral equipment corresponding to the source address is received, transferring the data corresponding to the source address in the unified memory to the destination address. By applying the data moving method provided by the invention, FIFO memories do not need to be arranged in all the peripheral equipment respectively, the system complexity is reduced, the data transmission waiting is avoided, and the data transmission efficiency is greatly improved. The invention also discloses a data moving device, equipment and a storage medium, and has corresponding technical effects.
Description
Technical Field
The present invention relates to the field of storage technologies, and in particular, to a data moving method, apparatus, device, and computer readable storage medium.
Background
With the increasingly widespread application of heterogeneous acceleration, field Programmable Gate Arrays (FPGA) based accelerator cards are also rapidly developed. The accelerator card FPGA is connected with a server host through a Peripheral Component Interconnect Express (PCIE) interface, the server host sends data needing to be accelerated to the accelerator card FPGA through the PCIE interface, and relevant data are returned through the PCIE interface after the accelerator card FPGA completes processing. In the data transmission process, a Direct Access Memory (DMA) is a common data transfer device.
The existing direct access memory receives the instruction of host, applies bus control right, moves data from address A to address B, and sends interrupt or other signals to inform host after moving. However, a general direct access memory can only perform data transfer between memories (memories) but cannot directly perform data transfer between streaming peripherals, such as Universal Asynchronous Receiver/Transmitter (UART) and network interface.
In the prior art, when devices such as UART and network interface require DMA to move data, a common method is to add a FIFO (First Input First Output) memory between the DMA and the UART, which is equivalent to changing a UART peripheral (peripheral) into a memory type peripheral. However, in a system with many peripherals, the FIFO memory needs to be added in each peripheral, which increases the complexity of the system and is not favorable for product development. Because the data of the peripheral is unstable, the data transmission waiting time is long, and the data transmission efficiency is low.
In summary, how to effectively solve the problems of complex system and low data transmission efficiency of the existing data moving method is a problem that needs to be solved urgently by those skilled in the art at present.
Disclosure of Invention
The invention aims to provide a data moving method, which reduces the complexity of a system and improves the data transmission efficiency; another object of the present invention is to provide a data moving device, an apparatus and a computer readable storage medium.
In order to solve the technical problems, the invention provides the following technical scheme:
a data migration method includes:
receiving configuration information corresponding to a target data transfer task;
analyzing the configuration information to obtain a source address, a destination address and a flow control type;
judging whether the flow control type is peripheral flow control or not;
if so, when a data moving request sent by the target peripheral equipment corresponding to the source address is received, moving the data corresponding to the source address in the unified memory to the destination address.
In a specific embodiment of the present invention, moving data corresponding to the source address to the destination address in the unified memory includes:
judging whether a DMA flow control data transfer task to be executed exists at present;
if yes, executing the DMA flow control data transfer task;
judging whether the DMA flow control data moving task is executed and completed;
and if so, executing the step of moving the data corresponding to the source address in the unified memory to the destination address.
In a specific embodiment of the present invention, determining whether there is a DMA flow control data transfer task to be processed currently includes:
judging whether the DMA flow control signal is in an enabling state or not;
executing the DMA flow control data transfer task, comprising:
and determining that the DMA flow control data transfer task exists, and executing the DMA flow control data transfer task.
In a specific embodiment of the present invention, after receiving a data transfer request sent by a target peripheral device corresponding to the source address, the method further includes:
judging whether the data moving request is the last data moving request corresponding to the target data moving task;
and if so, determining to finish the execution of the target data transfer task after executing the step of transferring the data corresponding to the source address in the unified memory to the destination address.
In a specific embodiment of the present invention, moving data corresponding to the source address in the unified memory to the destination address includes:
and moving the data corresponding to the source address in the unified memory to the destination address through an Avalon bus.
A data mover, comprising:
the information receiving module is used for receiving configuration information corresponding to the target data moving task;
the information analysis module is used for analyzing the configuration information to obtain a source address, a destination address and a flow control type;
the first judgment module is used for judging whether the flow control type is the peripheral flow control;
and the data moving module is used for moving the data corresponding to the source address in the unified memory to the destination address when receiving a data moving request sent by a target peripheral corresponding to the source address when determining that the flow control type is peripheral flow control.
In a specific embodiment of the present invention, the data moving module includes:
the first judgment sub-module is used for judging whether a DMA flow control data transfer task to be executed currently exists or not;
the task execution sub-module is used for executing the DMA flow control data transfer task when the DMA flow control data transfer task to be executed currently exists;
the second judgment submodule is used for judging whether the DMA flow control data moving task is executed and completed;
and the data moving submodule is used for moving the data corresponding to the source address in the unified memory to the destination address when the DMA flow control data moving task is determined to be completed.
In one embodiment of the present invention, the method further comprises:
the second judging module is used for judging whether the data moving request is the last data moving request corresponding to the target data moving task after receiving the data moving request sent by the target peripheral corresponding to the source address;
and the task execution state determining module is used for determining to finish the execution of the target data transfer task after the data corresponding to the source address in the unified memory is transferred to the destination address when the data transfer request is determined to be the last data transfer request corresponding to the target data transfer task.
A data moving apparatus comprising:
a memory for storing a computer program;
and a processor for implementing the steps of the data transfer method when executing the computer program.
A computer-readable storage medium, having stored thereon a computer program which, when executed by a processor, implements the steps of a data migration method as previously described.
The data moving method provided by the invention receives the configuration information corresponding to the target data moving task; analyzing the configuration information to obtain a source address, a destination address and a flow control type; judging whether the flow control type is an external flow control type; if so, when a data transfer request sent by a target peripheral corresponding to the source address is received, transferring the data corresponding to the source address in the unified memory to the destination address. The unified memory is preset, the flow control type of the data moving task corresponding to the peripheral is configured in advance, and when the flow control type of the target data moving task is determined to be the peripheral flow control type, the execution of the data moving task is triggered in a mode that the target peripheral actively initiates a data moving request. Therefore, FIFO memories are not needed to be arranged in the peripheral devices, the complexity of the system is reduced, waiting of data transmission is avoided, and the data transmission efficiency is greatly improved.
Correspondingly, the invention also provides a data moving device, equipment and a computer readable storage medium corresponding to the data moving method, which have the technical effects and are not described herein again.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flowchart illustrating an implementation of a data moving method according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating another embodiment of a data moving method according to the present invention;
FIG. 3 is a block diagram of a data migration system according to an embodiment of the present invention;
FIG. 4 is a flow chart of data movement according to an embodiment of the present invention;
FIG. 5 is a block diagram of a data moving device according to an embodiment of the present invention;
fig. 6 is a block diagram of a data moving device according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
The first embodiment is as follows:
referring to fig. 1, fig. 1 is a flowchart of an implementation of a data moving method according to an embodiment of the present invention, where the method may include the following steps:
s101: and receiving configuration information corresponding to the target data transfer task.
The method comprises the steps that configuration information of data transfer tasks corresponding to peripheral devices is set in a host in advance, when target data transfer tasks to be processed exist, the host sends the configuration information corresponding to the target data transfer tasks to the multi-stream empty DMA, and the multi-stream empty DMA receives the configuration information corresponding to the target data transfer tasks.
The configuration information may include a source address, a destination address, a flow control type, a data size, whether the source address and the destination address of the data to be moved belong to an incremental type or an invariant type, and the like.
The flow control types comprise DMA flow control and peripheral flow control. DMA flow control is to control DMA as data flow, and peripheral flow control is to control peripheral as data flow.
S102: and analyzing the configuration information to obtain a source address, a destination address and a flow control type.
And after receiving the configuration information corresponding to the target data transfer task, analyzing the configuration information to obtain a source address, a destination address and a flow control type.
S103: and judging whether the flow control type is the peripheral flow control type, if not, executing a step S104, and if so, executing a step S105.
And after the flow control type is obtained through analysis, judging whether the flow control type is an external flow control type, if not, indicating that the flow control type is a DMA flow control type, executing step S104, and if so, executing step S105.
S104: and when the DMA flow control signal is in an enabling state, moving the data corresponding to the source address in the unified memory to the destination address.
When the flow control type is determined not to be the peripheral flow control, the flow control type is determined to be the DMA flow control, whether the DMA flow control signal is in the enabling state is detected, for example, a ready signal can be preset as an indication identifier of the DMA flow control signal, the low level of the ready signal is set to correspond to the enabling state of the DMA flow control signal, and when the DMA flow control signal is determined to be the enabling state, data corresponding to the source address in the unified memory is moved to the destination address. When the DMA is used as the flow control, the DMA can directly obtain the total data volume to be transferred, so when the DMA flow control signal is determined to be in the enabled state, the DMA flow control signal can directly initiate data transmission until the execution of the target data transfer task is finished.
S105: and when a data moving request sent by the target peripheral equipment corresponding to the source address is received, moving the data corresponding to the source address in the unified memory to the destination address.
When the flow control type is determined to be the peripheral flow control type, the DMA cannot acquire the total data volume needing to be moved, so that the DMA needs to wait for the request of the peripheral and then move the data. And when a data moving request sent by the target peripheral equipment corresponding to the source address is received, moving the data corresponding to the source address in the unified memory to the destination address. The unified memory is preset, the flow control type of the data moving task corresponding to the peripheral is configured in advance, and when the flow control type of the target data moving task is determined to be the peripheral flow control type, the execution of the data moving task is triggered in a mode that the target peripheral actively initiates a data moving request. Therefore, FIFO memories do not need to be arranged in the peripheral devices, the system complexity is reduced, convenience is brought to product development, data transmission waiting is avoided, and the data transmission efficiency is greatly improved.
The data moving method provided by the invention receives the configuration information corresponding to the target data moving task; analyzing the configuration information to obtain a source address, a destination address and a flow control type; judging whether the flow control type is an external flow control type; if so, when a data transfer request sent by the target peripheral equipment corresponding to the source address is received, transferring the data corresponding to the source address in the unified memory to the destination address. By presetting the unified memory and configuring the flow control type of the data moving task corresponding to the peripheral equipment in advance, when the flow control type of the target data moving task is determined to be the peripheral flow control type, the execution of the data moving task is triggered in a mode that the target peripheral equipment actively initiates a data moving request. Therefore, FIFO memories do not need to be arranged in the peripheral devices, the complexity of the system is reduced, data transmission waiting is avoided, and the data transmission efficiency is greatly improved.
It should be noted that, based on the first embodiment, the embodiment of the present invention further provides a corresponding improvement scheme. In the following embodiments, the same steps or corresponding steps as those in the first embodiment may be referred to each other, and the corresponding beneficial effects may also be referred to each other, which are not described in detail in the following modified embodiments.
The second embodiment:
referring to fig. 2, fig. 2 is a flowchart of another implementation of the data moving method in the embodiment of the present invention, where the method may include the following steps:
s201: and receiving configuration information corresponding to the target data transfer task.
S202: and analyzing the configuration information to obtain a source address, a destination address and a flow control type.
S203: and judging whether the flow control type is peripheral flow control or not, if not, executing a step S204, and if so, executing a step S205.
S204: and when the DMA flow control signal is in an enabling state, moving the data corresponding to the source address in the unified memory to the destination address through the Avalon bus.
After the flow control type is determined not to be the peripheral flow control type, when the DMA flow control signal is in an enabling state, data corresponding to the source address in the unified memory is moved to the destination address through the Avalon bus, and therefore data moving among the peripheral devices is achieved.
S205: and receiving a data transfer request sent by the target peripheral equipment corresponding to the source address.
When the flow control type is determined to be the peripheral flow control type, when the peripheral needs to perform data transmission, the data transfer request is actively sent to the multi-flow control DMA, and the multi-flow control DMA receives the data transfer request sent by the target peripheral corresponding to the source address.
S206: and judging whether a DMA flow control data transfer task to be executed exists at present, if so, executing step S207, and if not, executing step S209.
Because the data transmission speed of the DMA flow control is higher than that of the peripheral flow control, the priority of the DMA flow control is preset to be higher than that of the peripheral flow control. After receiving a data transfer request sent by a target peripheral corresponding to a source address, judging whether a to-be-executed DMA flow control data transfer task exists currently, if so, indicating that the DMA flow control data transfer task needs to be executed first, executing step S207, otherwise, executing step S209.
S207: and executing the DMA flow control data transfer task.
And when the DMA flow control data transfer task to be executed currently exists, executing the DMA flow control data transfer task.
In one embodiment of the present invention, step S206 may include the following steps:
judging whether the DMA flow control signal is in an enabling state;
accordingly, step S207 may include the steps of:
and determining that the DMA flow control data transfer task exists, and executing the DMA flow control data transfer task.
And taking the state of the DMA flow control signal as a judgment basis for judging whether the DMA flow control data transfer task exists or not, judging whether the DMA flow control signal is in an enabled state or not after receiving a data transfer request sent by a target peripheral corresponding to the source address, if so, determining that the DMA flow control data transfer task exists, and executing the DMA flow control data transfer task.
S208: and judging whether the DMA flow control data moving task is executed completely, if so, executing the step S209, and if not, not processing.
After determining that the DMA flow control data transfer task exists and executing the DMA flow control data transfer task, determining whether the DMA flow control data transfer task is executed completely, if yes, indicating that the peripheral flow control data transfer task can be executed next, executing step S209, and if not, indicating that the DMA flow control data transfer task is not executed completely.
S209: and moving the data corresponding to the source address in the unified memory to the destination address through the Avalon bus.
When the DMA flow control data transfer task is determined to be completed, the peripheral flow control data transfer task can be executed next, and data corresponding to the source address in the unified memory is transferred to the destination address through the Avalon bus.
S210: and judging whether the data transfer request is the last data transfer request corresponding to the target data transfer task, if so, executing step S211, otherwise, repeatedly executing step S205.
When the peripheral is used as a flow control device, the DMA cannot acquire the total data volume required to be moved, the DMA needs to wait for the request of the peripheral and then move the data, and the DMA cannot automatically acquire whether the data movement is finished. Therefore, when the data of the peripheral device is about to end, the DMA is notified that the data is the last data transfer by initiating the last data transfer request, and after the DMA executes the data transfer of the time, the data transfer task is ended. After receiving the data transfer request sent by the target peripheral corresponding to the source address, determining whether the data transfer request is the last data transfer request corresponding to the target data transfer task, if so, indicating that the data transfer is the last data transfer corresponding to the target data transfer task, executing step S211, otherwise, indicating that the data transfer is not the last data transfer corresponding to the target data transfer task, and repeatedly executing step S205.
S211: and determining to finish executing the target data transfer task.
When the data moving request is determined to be the last data moving request corresponding to the target data moving task, the data moving request is described to be the last data moving corresponding to the target data moving task, and the target data moving task is determined to be completed.
Referring to fig. 3, fig. 3 is a block diagram of a data moving system according to an embodiment of the present invention. The system comprises peripheral equipment such as SRAM, DDR, SPI, UART, ethernet (Ethernet) and the like, multi-flow control DMA and a host. The peripheral equipment is connected with the multi-flow control DMA and the host through Avalon-MM interfaces. The multi-flow control DMA is set as a multi-flow control DMA based on the FPGA, all logics are realized in the FPGA and mainly divided into 8 modules: the system comprises a configuration module, a state module, a DMA flow control module, an external flow control module, a Burst transmission module, a Last transmission module, a request module and an interrupt module.
The configuration module mainly receives configuration information from host, including source address, destination address, data volume, flow control type, whether the source address and the destination address belong to increment type or invariant type, etc. of data to be moved by the multi-flow control DMA.
The status module mainly has the function of recording status information of the DMA flow control module and the peripheral flow control module, such as internal FIFO empty and full, whether the current flow control channel is moving, waiting, or ending, the remaining data volume, and the like.
The DMA flow control module mainly functions to perform data transfer between a memory (memory) or a peripheral (peripheral) by using a multi-flow control DMA as a data flow control, and the flow control types include four types, namely, memory to memory (m 2 m), memory to peripheral (m 2 p), peripheral to memory (p 2 m), and peripheral to peripheral (p 2 p).
The peripheral flow control module has the main functions of controlling data flow by taking a peripheral as a data flow and executing data transfer between a memory or a peripheral, and the flow control types are three, namely memory to peripheral (m 2 p), peripheral to memory (p 2 m) and peripheral to peripheral (p 2 p).
Setting the priority of the DMA flow control to be higher than that of the peripheral flow control.
The main function of the interrupt module is that after the data transfer task of the multi-stream control DMA is completed, the interrupt module sends corresponding interrupt or other information to inform the host, and the host can also be configured to shield the interrupts, and then obtains the corresponding information through the read status module.
The Burst transmission module changes various flow control request types of the multi-flow control DMA into Burst transmission meeting an Avalon bus protocol, continuously reads data from a source address, and writes a destination address, and the data needs to pass through the module no matter the DMA is used as flow control or peripheral equipment is used as flow control.
The Last transmission module is only used for data transfer when the peripheral serves as the flow control, the multi-flow control DMA cannot acquire the total data volume needing to be transferred, only the request of the peripheral is waited, data transfer is performed, and the multi-flow control DMA cannot acquire when the data transfer is finished. When the peripheral data is about to finish, the Last transmission is requested to inform the multi-flow control DMA that the Last data is moved, and after the multi-flow control DMA finishes the Last transmission, the data moving task is finished. When the multi-flow control DMA is used as the flow control, the multi-flow control DMA can acquire the total data volume to be moved, so that normal Burst transmission can be initiated until the task is finished.
The main function of the request module is to receive a data transfer request from the peripheral module, because the peripheral data is unstable, sometimes much data comes, sometimes little data comes, and sometimes no data comes, in which case if the multi-flow control DMA is used as the flow control, a long wait may be needed, resulting in low efficiency. At the moment, the peripheral equipment is used as flow control, when data comes, a request is actively initiated to the multi-flow control DMA, the multi-flow control DMA initiates a Burst request under the normal condition, if the data is the Last data, a Last request is initiated, and the peripheral equipment flow control module initiates corresponding Burst/Last data transmission according to the request type.
The multi-flow control DMA can be encapsulated into IP for independent use and can be suitable for data movement among various types of peripheral equipment. The flexibility, the portability and the expandability are enhanced, and the system can be directly called in project development, thereby providing convenience for product development and shortening the development period.
Referring to fig. 4, fig. 4 is a flowchart of data movement according to an embodiment of the present invention. The work flow of the multi-flow control DMA is illustrated by data movement among SRAM, DDR and UART. The first set of configuration cases of host is that the source address is SRAM address a, the destination address is DDR address B, the total amount of data is 256M, the flow control type is D _ M2M, and both the source address and the destination address are incremented. The second group of configuration conditions are that the source address is UART address C, the destination address is DDR address D, the flow control type is P _ P2m, the source address is fixed and unchanged, and the destination address is increased progressively.
Firstly, the multi-flow control DMA starts to execute a task of D _ m2m, burst transmission is initiated through a Burst transmission module, data are read from the SRAM and written into the multi-flow control DDR, and the read-write address of each Burst is increased progressively. If the data is moved to 64M, the data of the SRAM is insufficient and needs to wait, and then D _ M2M waits at the moment, and meanwhile, the transmission of P _ P2M is started. If the UART has sufficient data, the UART can initiate a req request to inform the multi-flow control DMA that the data of the UART can be read, and the multi-flow control DMA reads the data of the UART and writes the data into a multi-flow control DDR address D by initiating Burst transmission. If the data of the SRAM is sufficient again, the ready signal is pulled low, and D _ m2m is started again after the P _ P2m finishes the current burst transmission, but the time is needed. When the transmission of D _ m2m is finished, the multi-flow control DMA initiates corresponding interruption to the host to inform the host that the D _ m2m moving task is finished, and simultaneously, the P _ P2m is continuously executed, because the data rate of the UART is slower, the next moving can be executed for a longer time, the multi-flow control DMA waits for the req request of the UART, then Burst transmission moving data is executed, when the multi-flow control DMA receives the Last req request, the multi-flow control DMA initiates Last transmission, and after the Last transmission is finished, corresponding interruption is initiated to the host to inform the host that the P _ P2m task is finished at the moment.
In the period, the state module records the state information of D _ m2m and P _ P2m, and the host can shield interruption and acquire the information by accessing the state module.
Example three:
corresponding to the above method embodiment, the present invention further provides a data moving device, and the data moving device described below and the data moving method described above may be referred to in correspondence.
Referring to fig. 5, fig. 5 is a block diagram of a data moving device according to an embodiment of the present invention, where the device may include:
an information receiving module 51, configured to receive configuration information corresponding to the target data moving task;
the information analysis module 52 is configured to analyze the configuration information to obtain a source address, a destination address, and a flow control type;
the first judging module 53 is configured to judge whether the flow control type is an external flow control;
and the data moving module 54 is configured to, when it is determined that the flow control type is the peripheral flow control, move data corresponding to the source address in the unified memory to the destination address when receiving a data moving request sent by a target peripheral corresponding to the source address.
In one embodiment of the present invention, the data moving module 54 includes:
the first judgment submodule is used for judging whether a DMA flow control data transfer task to be executed exists at present;
the task execution submodule is used for executing the DMA flow control data transfer task when the DMA flow control data transfer task to be executed currently exists;
the second judgment submodule is used for judging whether the DMA flow control data moving task is executed and completed;
and the data moving submodule is used for moving the data corresponding to the source address in the unified memory to the destination address when the DMA flow control data moving task is determined to be completed.
In a specific embodiment of the present invention, the second determining sub-module is specifically a module that determines whether the DMA flow control signal is in an enabled state;
the task execution sub-module is specifically a module which determines that a DMA flow control data transfer task exists and executes the DMA flow control data transfer task when determining that the DMA flow control signal is in an enabled state.
In one embodiment of the present invention, the apparatus may further include:
the second judgment module is used for judging whether the data moving request is the last data moving request corresponding to the target data moving task after receiving the data moving request sent by the target peripheral corresponding to the source address;
and the task execution state determining module is used for determining to finish the execution of the target data transfer task after the data corresponding to the source address in the unified memory is transferred to the destination address when the data transfer request is determined to be the last data transfer request corresponding to the target data transfer task.
In an embodiment of the present invention, the data moving module 54 is a module that moves data corresponding to a source address in the unified memory to a destination address through the Avalon bus.
Corresponding to the above method embodiment, referring to fig. 6, fig. 6 is a schematic diagram of a data moving device provided by the present invention, where the device may include:
a memory 61 for storing a computer program;
the processor 62, when executing the computer program stored in the memory 61, may implement the following steps:
receiving configuration information corresponding to the target data transfer task; analyzing the configuration information to obtain a source address, a destination address and a flow control type; judging whether the flow control type is an external flow control type; if so, when a data transfer request sent by the target peripheral equipment corresponding to the source address is received, transferring the data corresponding to the source address in the unified memory to the destination address.
For the introduction of the device provided by the present invention, please refer to the above method embodiment, which is not described herein again.
Example four:
corresponding to the above method embodiment, the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, can implement the following steps:
receiving configuration information corresponding to the target data transfer task; analyzing the configuration information to obtain a source address, a destination address and a flow control type; judging whether the flow control type is an external flow control type; if so, when a data transfer request sent by the target peripheral equipment corresponding to the source address is received, transferring the data corresponding to the source address in the unified memory to the destination address.
The computer-readable storage medium may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
For the introduction of the computer-readable storage medium provided by the present invention, please refer to the above method embodiments, which are not described herein again.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device, the apparatus and the computer-readable storage medium disclosed in the embodiments correspond to the method disclosed in the embodiments, so that the description is simple, and the relevant points can be referred to the description of the method.
The principle and the implementation of the present invention are explained in the present application by using specific examples, and the above description of the embodiments is only used to help understanding the technical solution and the core idea of the present invention. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, it is possible to make various improvements and modifications to the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Claims (10)
1. A data migration method, comprising:
receiving configuration information corresponding to the target data transfer task;
analyzing the configuration information to obtain a source address, a destination address and a flow control type;
judging whether the flow control type is an external flow control type;
if so, when a data transfer request sent by a target peripheral device corresponding to the source address is received, transferring the data corresponding to the source address in a unified memory to the destination address, wherein the unified memory is an FIFO memory which is uniformly used by each peripheral device.
2. The data transfer method according to claim 1, wherein transferring data corresponding to the source address to the destination address in a unified memory includes:
judging whether a DMA flow control data transfer task to be executed exists at present;
if yes, executing the DMA flow control data transfer task;
judging whether the DMA flow control data moving task is executed and completed;
and if so, executing the step of moving the data corresponding to the source address in the unified memory to the destination address.
3. The data transfer method according to claim 2, wherein the step of judging whether the DMA flow control data transfer task to be processed currently exists comprises the following steps:
judging whether the DMA flow control signal is in an enabling state or not;
executing the DMA flow control data transfer task, comprising:
and determining that the DMA flow control data transfer task exists, and executing the DMA flow control data transfer task.
4. The data transfer method according to any one of claims 1 to 3, further comprising, after receiving a data transfer request sent by a target peripheral device corresponding to the source address:
judging whether the data moving request is the last data moving request corresponding to the target data moving task;
and if so, determining to finish the execution of the target data transfer task after executing the step of transferring the data corresponding to the source address in the unified memory to the destination address.
5. The method of claim 4, wherein moving the data corresponding to the source address to the destination address in the unified memory comprises:
and moving the data corresponding to the source address in the unified memory to the destination address through an Avalon bus.
6. A data moving device, comprising:
the information receiving module is used for receiving the configuration information corresponding to the target data moving task;
the information analysis module is used for analyzing the configuration information to obtain a source address, a destination address and a flow control type;
the first judgment module is used for judging whether the flow control type is the peripheral flow control;
and the data moving module is used for moving the data corresponding to the source address in a unified memory to the destination address when receiving a data moving request sent by a target peripheral corresponding to the source address when the flow control type is determined to be the peripheral flow control type, wherein the unified memory is an FIFO memory which is used by all peripheral devices in a unified manner.
7. The data mover of claim 6, wherein the data mover module comprises:
the first judgment submodule is used for judging whether a DMA flow control data transfer task to be executed exists at present;
the task execution submodule is used for executing the DMA flow control data transfer task when the DMA flow control data transfer task to be executed currently exists;
the second judging submodule is used for judging whether the DMA flow control data moving task is executed and completed;
and the data moving submodule is used for moving the data corresponding to the source address in the unified memory to the destination address when the DMA flow control data moving task is determined to be completed.
8. The data mover according to claim 6 or 7, further comprising:
the second judging module is used for judging whether the data moving request is the last data moving request corresponding to the target data moving task after receiving the data moving request sent by the target peripheral corresponding to the source address;
and the task execution state determining module is used for determining to finish the execution of the target data transfer task after the data corresponding to the source address in the unified memory is transferred to the destination address when the data transfer request is determined to be the last data transfer request corresponding to the target data transfer task.
9. A data moving device, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the data movement method according to any one of claims 1 to 5 when executing the computer program.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of a data moving method according to any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110211367.8A CN112947857B (en) | 2021-02-25 | 2021-02-25 | Data moving method, device, equipment and computer readable storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110211367.8A CN112947857B (en) | 2021-02-25 | 2021-02-25 | Data moving method, device, equipment and computer readable storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112947857A CN112947857A (en) | 2021-06-11 |
| CN112947857B true CN112947857B (en) | 2023-02-28 |
Family
ID=76246183
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110211367.8A Active CN112947857B (en) | 2021-02-25 | 2021-02-25 | Data moving method, device, equipment and computer readable storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112947857B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113868039B (en) * | 2021-08-30 | 2024-02-09 | 浪潮电子信息产业股份有限公司 | Test method, device and related equipment |
| CN114490465B (en) * | 2021-12-28 | 2024-04-26 | 北京奕斯伟计算技术股份有限公司 | Data transmission method and device for direct memory access |
| CN115660941B (en) * | 2022-12-27 | 2023-03-14 | 北京象帝先计算技术有限公司 | Image moving method and device, electronic equipment and computer readable storage medium |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100342359C (en) * | 2004-12-24 | 2007-10-10 | 华为技术有限公司 | Method of data interchange by using mode of direct memory access |
| CN100354842C (en) * | 2005-02-23 | 2007-12-12 | 华为技术有限公司 | Access device for direct memory access and method for implementing single channel bidirectional data interaction |
| CN102541780B (en) * | 2011-12-15 | 2014-10-22 | 苏州国芯科技有限公司 | Multi-data stream channel DMA (Direct Memory Access) system |
| US20130204962A1 (en) * | 2012-02-02 | 2013-08-08 | Texas Instruments Incorporated | Network and peripheral interface circuits, systems and processes |
| CN109558348B (en) * | 2018-12-19 | 2024-10-01 | 深圳开立生物医疗科技股份有限公司 | Data moving method, device and system |
| CN111352869B (en) * | 2018-12-24 | 2024-05-07 | 深圳市中兴微电子技术有限公司 | Data transmission method and device and storage medium |
| CN109766296A (en) * | 2019-01-08 | 2019-05-17 | 郑州云海信息技术有限公司 | A kind of data processing method, device, system and dma controller |
-
2021
- 2021-02-25 CN CN202110211367.8A patent/CN112947857B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN112947857A (en) | 2021-06-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112947857B (en) | Data moving method, device, equipment and computer readable storage medium | |
| CN112765059A (en) | DMA (direct memory access) equipment based on FPGA (field programmable Gate array) and DMA data transfer method | |
| CN108595353B (en) | PCIe bus-based data transmission control method and device | |
| US9009373B2 (en) | Method for implementing audio transmission and mobile terminal | |
| CN109558344B (en) | DMA transmission method and DMA controller suitable for network transmission | |
| CN111190842B (en) | Direct memory access, processor, electronic device, and data transfer method | |
| US20190369919A1 (en) | Task management method and host for electronic storage device | |
| WO2022032990A1 (en) | Command information transmission method, system, and apparatus, and readable storage medium | |
| EP3296836A1 (en) | Computer device and data read-write method for computer device | |
| CN112100090A (en) | Data access request processing method, device, medium and memory mapping controller | |
| CN107066413B (en) | Method for processing data of multiple bus devices and bus system thereof | |
| CN112631969A (en) | Virtual multichannel data transmission method and system based on PCIE interface | |
| US20060236001A1 (en) | Direct memory access controller | |
| CN112749113A (en) | Data interaction method, system, device and medium | |
| CN103106164A (en) | Highly efficient direct memory access (DMA) controller | |
| CN112817899B (en) | PCIE-based data transmission method and device, storage medium and electronic equipment | |
| CN116594951B (en) | FPGA-based data transmission system and method | |
| CN109992539B (en) | Double-host cooperative working device | |
| CN114579319B (en) | Video memory management method, video memory management module, SOC and electronic equipment | |
| CN111143068A (en) | File operation method and device and embedded controller | |
| CN112732176B (en) | SSD (solid State disk) access method and device based on FPGA (field programmable Gate array), storage system and storage medium | |
| CN113961497A (en) | Communication circuit system, method, chip and storage medium | |
| CN107729140B (en) | Device and method for realizing command queuing functions of multiple eMMC host interfaces in parallel | |
| CN107992328A (en) | The method, apparatus and system-on-chip of a kind of data processing | |
| CN115098428B (en) | SPI data transmission method and device, electronic equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |