CN103488600A - Universal auxiliary machine synchronous serial interface circuit - Google Patents
Universal auxiliary machine synchronous serial interface circuit Download PDFInfo
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- CN103488600A CN103488600A CN201310465134.6A CN201310465134A CN103488600A CN 103488600 A CN103488600 A CN 103488600A CN 201310465134 A CN201310465134 A CN 201310465134A CN 103488600 A CN103488600 A CN 103488600A
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Abstract
The invention discloses a universal auxiliary computer synchronous serial interface circuit comprising a starting and ending detection module, a control module, a parallel-serial/serial-parallel conversion module and an address pointer register. The starting and ending detection module is used for detecting and outputting a significance bit of an SPI bus protocol, and a starting condition and an ending condition of an IIC bus protocol. The control module is used for determining a bus data transmission mode of the serial interface circuit according to an output signal of the starting and ending detection module, and controlling the parallel-serial/serial-parallel conversion module. The parallel-serial/serial-parallel conversion module is controlled by the control module, and is used for outputting data of multiple register data inside an auxiliary computer in a serial mode, and converting external serial data into the data of the registers inside the auxiliary computer. The address pointer register is used for carrying out addressing on the resisters inside the auxiliary computer. The universal auxiliary computer synchronous serial interface circuit achieves compatibility of the bus data transmission of the IIC protocol and the SPI protocol, and can meet the application requirements of different occasions.
Description
Technical field
The present invention relates to a kind of serial communication technology, be specifically related to a kind of general slave synchronous serial interface circuit.
Background technology
SPI (Serial Peripheral Interface) and IIC (Inter-Integrated Circuit) bus interface circuit have been widely used in the every field such as microprocessor, sensor, EEPROM, Flash storer at present.SPI agreement and IIC agreement are the synchronous serial bus agreements, can and receive serial data by parallel data serial output and be converted to parallel data.Main frame in system and slave utilize spi bus or iic bus to carry out data transmission, and the performance of bus interface circuit directly affects the data transmission quality of bus.
Aspect data rate, spi bus can reach 5Mbit/s, and the highest 3.4Mbit/s that can only reach of iic bus; Aspect the data transmission accuracy rate, iic bus is because byte data of every transmission all needs to reply, and accuracy rate will be higher than spi bus; Aspect system applies, iic bus can form the system of many main frames, many slaves, and spi bus can only form the system of a main frame, many slaves.
The slave synchronous serial interface circuit of development scarcely has the function of compatible iic bus of while and spi bus data transmission at present.The existing iic bus interface circuit of some slave, have again the spi bus interface circuit, but two kinds of interface circuits have been wasted the internal logic resource and taken more interface.
Therefore the general slave synchronous serial interface circuit design of a kind of compatible IIC and spi bus agreement extremely is necessary.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of general slave synchronous serial interface circuit of supporting compatible IIC agreement and SPI protocol bus data transmission is provided.The technical solution used in the present invention is:
A kind of general slave synchronous serial interface circuit comprises:
Initial with stop detection module, for detection of spi bus agreement significance bit, iic bus agreement initial conditions and end condition output;
Control module, for determine the bus data transmission mode of described serial interface circuit according to the initial output signal with the termination detection module, to also string and string modular converter are controlled; Described bus data transmission mode comprises spi bus data transmission and iic bus data transmission;
And string and string modular converter, be controlled by control module, be converted into slave internal register data for a plurality of register data serial output by slave inside and external series data;
Address pointer register, for a plurality of registers of addressing slave inside;
When described serial interface circuit, for the spi bus data transmission time, slave carries out data transmission according to spi bus agreement and main frame;
When described serial interface circuit, for the iic bus data transmission time, slave carries out data transmission according to iic bus agreement and main frame.
Further, described serial interface circuit also comprises chip selection signal port CS_n, serial clock port SCK, serial data port SOI, slave addresses selection port;
When the chip selection signal of described chip selection signal port CS_n is effective, initial and termination detection module sends spi bus agreement significance bit to control module, and described serial interface circuit is for the transmission of SPI total data line;
When the chip selection signal of described chip selection signal port CS_n is invalid, the initial data with stopping detection module detection serial clock port SCK and serial data port SOI, if iic bus agreement initial conditions detected, described serial interface circuit is for the iic bus data transmission; And then, when iic bus agreement end condition being detected, the iic bus data transmission stops;
Described slave addresses selects port for when the iic bus data transmission, determines unique slave addresses of each slave on iic bus.
Further, it is three that described slave addresses is selected port, is respectively that slave addresses is selected port A2, A1 and A0.
Further, described chip selection signal is Low level effective, and high level is invalid.
Further, described iic bus agreement initial conditions are: when the SCK signal is high level, the SOI signal switches to low level from high level; Described iic bus agreement end condition is: when the SCK signal is high level, the SOI signal switches to high level from low level.
Further, when described serial interface circuit for the spi bus data transmission time, according to the register address information comprised in the read write command received and in conjunction with address pointer register, a plurality of registers in slave are carried out to addressing, be specially: control module deposits the register address information comprised in the read write command received in address pointer register, and the register address information that then deposits according to this address pointer register in is carried out addressing to a plurality of registers in slave.
Further, when described serial interface circuit for the iic bus data transmission time, according to the address pointer received and in conjunction with address pointer register, a plurality of registers in slave are carried out to addressing, be specially: control module deposits the address pointer received in address pointer register, and the address pointer that then deposits according to this address pointer register in carries out addressing to a plurality of registers in slave.
The present invention has designed the general slave synchronous serial interface circuit of a kind of compatible IIC and spi bus agreement, and the internal logic resource of having saved interface circuit can also reduce the number of ports of slave interface circuit, can promote the optimal design of whole system.
The accompanying drawing explanation
Fig. 1 is general slave synchronous serial interface circuit diagram.
Fig. 2 is general slave synchronous serial interface circuit structure block diagram.
The state machine that Fig. 3 is general slave synchronous serial interface circuit control module.
Fig. 4 is the sequential of this interface circuit for the spi bus data transmission.
Fig. 5 is the read sequential of this interface circuit for the iic bus data transmission.
Fig. 6 is the write sequential of this interface circuit for the iic bus data transmission.
Embodiment
Below in conjunction with concrete drawings and Examples, the invention will be further described.
A kind of general slave synchronous serial interface circuit comprises: initial and termination detection module 114, for detection of spi bus agreement significance bit, iic bus agreement initial conditions 106 and end condition 110 output; Control module 115, for determine the bus data transmission mode of described serial interface circuit according to the initial output signal with termination detection module 114, to and the string and the string and modular converter 116 controlled, described bus data transmission mode comprises spi bus data transmission and iic bus data transmission; And string and string modular converter 116, be controlled by control module 115, be converted into slave internal register data for a plurality of register data serial output by slave inside and external series data; Address pointer register 117, for a plurality of registers of addressing slave inside.
When described serial interface circuit, for the spi bus data transmission time, slave carries out data transmission according to spi bus agreement and main frame;
When described serial interface circuit, for the iic bus data transmission time, slave carries out data transmission according to iic bus agreement and main frame.
Particularly, slave interface circuit proposed by the invention as shown in Figure 1, comprises with lower interface: chip selection signal port CS_n, serial clock port SCK, serial data port SOI, slave addresses are selected port A2, A1, A0.Wherein, it is defeated that the chip selection signal of chip selection signal end CS_n determines whether to carry out spi bus biography data, Low level effective; Slave addresses selects port A2, A1, A0 for when the iic bus data transmission, determines unique slave addresses of each slave on iic bus.The serial clock terminal that serial clock port SCK, serial data port SOI are iic bus or spi bus and serial data end.
As shown in Figure 2, initial sum stops detection module 114 and send spi bus agreement significance bit to control module 115 when chip selection signal port CS_n is low level circuit structure block diagram of the present invention, and described serial interface circuit is for the transmission of SPI total data line; Otherwise the data of utilizing serial clock port SCK, serial data port SOI when chip selection signal port CS_n is high level whether meet Fig. 5 and Fig. 6 in initial conditions 106 and the stop condition 110 of iic bus agreement judge that whether the iic bus data transmission effective, that is to say the initial data with stopping detection module 114 detection serial clock port SCK and serial data port SOI, if iic bus agreement initial conditions 106 detected, described serial interface circuit is for the iic bus data transmission; And then, when iic bus agreement end condition 110 being detected, the iic bus data transmission stops.Control module 115 stops iic bus agreement initial conditions 106 and the end condition 110 of detection module 114 transmissions according to initial sum or spi bus agreement significance bit is controlled and gone here and there and goes here and there and modular converter 116.When the iic bus data transmission, control module 115 also will receive and send response bits 109 in addition.117 pairs of slave internal registers of host computer using address pointer register carry out addressing, and a plurality of registers in slave inside are carried out to read-write operation.In the present embodiment, in slave, register 1, register 2, register 4, register 5 are read-only register, and the low byte of register 3 is that read-only, high byte is read-write.In this example, slave internal register data are 16 bits.
Above-mentioned iic bus agreement initial conditions 106 are: when the SCK signal is high level, the SOI signal switches to low level from high level; Above-mentioned iic bus agreement end condition 110 is: when the SCK signal is high level, the SOI signal switches to high level from low level.
Wherein, iic bus requires every transmission 8 Bit datas, receives data side and need to send response bits 109 to sending data side.Spi bus does not need to receive or send response bits 109, receives at every turn and send the data of 16 bits.Therefore, in order to meet the needs of iic bus agreement and spi bus agreement, when according to the iic bus agreement, carrying out data transmission, and string and string modular converter 116 utilize is that the register of 8 bits is (to 16 bit register operation the time, can first carry out the operation of high eight-bit, hang down again the operation of eight), and when according to the spi bus agreement, carrying out data transmission, and string and string modular converter 116 utilizations is the register of 16 bits.
Shown in Fig. 3 is the state machine of control module 115.This state machine is initially Idle state 119, when slave receives the spi bus significance bit, be chip selection signal port CS_n while being logical zero, slave enters read data state 124, and next slave enters the read write command state 125 that receives, if read instruction, enter again read data state 124; If write command, enter and write data mode 126.
And when state machine is initially located in Idle state 119, if from machine testing, (initial and termination detection module 114 is being detected, lower same) to iic bus agreement initial conditions 106 and chip selection signal CS_n, be logical one, control module 115 enters into slave addresses and the read-write position receives response status 120, if then slave detects iic bus agreement end condition 110, enter Idle state 119, read sign for iic bus else if, system enters data and sends state 121, if and then slave detects iic bus agreement end condition 110, enter initial Idle state 119; IIC writes sign if, and slave enters address and receives response status 122, and if then slave iic bus agreement end condition 110 detected, slave returns to Idle state 119; Otherwise slave enters data receiver response status 123, and then slave receives iic bus agreement end condition 110, turns back to Idle state 119.
Sequential when general slave synchronous serial interface circuit is used for the spi bus data transmission as shown in Figure 4.When chip selection signal CS_n is effective, at first the read data that slave sends 16 bits to main frame (is the corresponding acquiescence register data of address pointer register 117, initial default data that power on namely), and then the 16 bit read write commands that Receiving Host sends, according to the difference of reading and writing instruction, next 16 clock period slaves send 16 bit read datas or Receiving Host 16 than feature data to main frame.When general slave synchronous serial interface circuit is used for the spi bus data transmission, the corresponding relation of read write command and register is as shown in table 1.Read if instruction, 6,5,4 that read in this example in instruction have represented register address information, 16 6,5,4 of reading instruction that control module 115 will receive deposit address pointer register 117 in, and then slave corresponding register read of register address information from read instruction is fetched data and sent to main frame; Write command if, the middle eight bit data of 16 write commands that control module 115 will receive deposits in the high eight-bit of register 3.Only have register 3 in this example for writing, thus during write operation without according to the addressing of register address information, in the situation that other is possible, when a plurality of registers being arranged for can write the time, the register addressing mode of write operation can be with reference to the addressing mode of read operation.
Table 1
| Register | Read instruction | Write command |
| Register 1 | 1000_0000_0000_0000 | ? |
| Register 2 | 1000_0000_0000_1000 | ? |
| Register 3 | 1000_0000_0001_0000 | 0000_xxxx_xxxx_0000 |
| Register 4 | 1000_0000_0001_1000 | ? |
| Register 5 | 1000_0000_0010_0000 | ? |
General slave synchronous serial interface circuit is read sequential as shown in Figure 5 when the iic bus data transmission.In the situation that chip selection signal CS_n is invalid, at first main frame sends iic bus agreement initial conditions 106 to slave, next main frame sends 7 slave addresses 107 and 1 to slave and reads zone bit 108, if slave addresses 107 slave addresses corresponding with this slave addresses selecting side A2-A0 is consistent, slave sends response bits 109 to main frame, next main frame and slave carry out data transmission 130 and reply 131, when slave detects the iic bus agreement end condition 110 of main frame transmission, the iic bus transmission stops.When read operation first, do not need to address pointer register 117 writing address pointers, directly the corresponding acquiescence register data of reading address pointer register 117, namely the initial default data that power on.
General slave synchronous serial interface circuit is write sequential as shown in Figure 6 when the iic bus data transmission.In the situation that chip selection signal CS_n is invalid, at first main frame sends iic bus agreement initial conditions 106 to slave, next main frame sends 7 slave addresses 107 and 1 to slave and writes zone bit 132, if slave addresses 107 slave addresses corresponding with this slave addresses selecting side A2-A0 is consistent, slave sends response bits 109 to main frame, next main frame carries out data transmission 130 and replys 131 with slave again after address pointer register 117 writing address pointer datas 133, in this process, specifically control module 115 deposits the address pointer received in address pointer register 117, control module 115 utilizes address pointer to distinguish the inner different register of slave, with aft engine, slave is carried out to data writing operation, data are written in the corresponding register of address pointer (only has register 3 to write in this example, in other possible situation, other register also can be configured to read-write register).When slave detects the stop condition 110 of main frame transmission, the iic bus transmission stops.The corresponding relation of the register of address pointer and slave inside is as shown in table 2.In the present embodiment, control module 115 deposits in address pointer register 117 low three of the address pointer data 133 that receive, can carry out addressing to five registers.
Table 2
| Register | Address pointer |
| Register 1 | 8’b0000_0000 |
| Register 2 | 8’b0000_0001 |
| Register 3 | 8’b0000_0010 |
| Register 4 | 8’b0000_0011 |
| Register 5 | 8’b0000_0100 |
Claims (7)
1. a general slave synchronous serial interface circuit, is characterized in that, comprising:
Initial with stop detection module (114), for detection of spi bus agreement significance bit, iic bus agreement initial conditions (106) and end condition (110) and export;
Control module (115), for determining the bus data transmission mode of described serial interface circuit, to also string and string modular converter (116) are controlled according to the initial output signal with termination detection module (114); Described bus data transmission mode comprises spi bus data transmission and iic bus data transmission;
And string and string modular converter (116), be controlled by control module (115), be converted into slave internal register data for a plurality of register data serial output by slave inside and external series data;
Address pointer register (117), for a plurality of registers of addressing slave inside;
When described serial interface circuit, for the spi bus data transmission time, slave carries out data transmission according to spi bus agreement and main frame;
When described serial interface circuit, for the iic bus data transmission time, slave carries out data transmission according to iic bus agreement and main frame.
2. general slave synchronous serial interface circuit as claimed in claim 1 is characterized in that: described serial interface circuit also comprises that chip selection signal port CS_n, serial clock port SCK, serial data port SOI, slave addresses select port;
When the chip selection signal of described chip selection signal port CS_n is effective, initial and termination detection module (114) sends spi bus agreement significance bit to control module (115), and described serial interface circuit is for the transmission of SPI total data line;
When the chip selection signal of described chip selection signal port CS_n is invalid, the initial data with stopping detection module (114) detection serial clock port SCK and serial data port SOI, if iic bus agreement initial conditions (106) detected, described serial interface circuit is for the iic bus data transmission; And then, when iic bus agreement end condition (110) being detected, the iic bus data transmission stops;
Described slave addresses selects port for when the iic bus data transmission, determines unique slave addresses of each slave on iic bus.
3. general slave synchronous serial interface circuit as claimed in claim 2 is characterized in that: it is three that described slave addresses is selected port, is respectively that slave addresses is selected port A2, A1 and A0.
4. general slave synchronous serial interface circuit as claimed in claim 2, it is characterized in that: described chip selection signal is Low level effective, and high level is invalid.
5. general slave synchronous serial interface circuit as claimed in claim 2, it is characterized in that: described iic bus agreement initial conditions (106) are: when the SCK signal is high level, the SOI signal switches to low level from high level; Described iic bus agreement end condition (110) is: when the SCK signal is high level, the SOI signal switches to high level from low level.
6. general slave synchronous serial interface circuit as claimed in claim 1 or 2 is characterized in that:
When described serial interface circuit for the spi bus data transmission time, according to the register address information comprised in the read write command received and in conjunction with address pointer register (117), a plurality of registers in slave are carried out to addressing, be specially: control module (115) deposits the register address information comprised in the read write command received in address pointer register (117), and the register address information that then deposits according to this address pointer register (117) in is carried out addressing to a plurality of registers in slave.
7. general slave synchronous serial interface circuit as claimed in claim 1 or 2 is characterized in that:
When described serial interface circuit for the iic bus data transmission time, according to the address pointer received and in conjunction with address pointer register (117), a plurality of registers in slave are carried out to addressing, be specially: control module (115) deposits the address pointer received in address pointer register (117), and the address pointer that then deposits according to this address pointer register (117) in carries out addressing to a plurality of registers in slave.
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| CN105224497A (en) * | 2015-09-10 | 2016-01-06 | 上海斐讯数据通信技术有限公司 | The extendible treating apparatus of serial line interface and method |
| CN111124987A (en) * | 2019-12-30 | 2020-05-08 | 京信通信系统（中国）有限公司 | PCIE-based data transmission control system and method |
| CN112470137A (en) * | 2019-01-24 | 2021-03-09 | 株式会社矽因赛德 | Master and slave device having cascade structure |
| CN114168508A (en) * | 2020-09-10 | 2022-03-11 | 鸿富锦精密电子(天津)有限公司 | Single-wire bidirectional communication circuit and single-wire bidirectional communication method |
| CN114356419A (en) * | 2022-03-14 | 2022-04-15 | 苏州浪潮智能科技有限公司 | Universal interface register system and rapid generation method |
| CN115033516A (en) * | 2022-05-30 | 2022-09-09 | 浙江大学 | Method for realizing multi-wire SPI (Serial peripheral interface) transmission based on multiple single-wire SPI interfaces |
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| CN114356419A (en) * | 2022-03-14 | 2022-04-15 | 苏州浪潮智能科技有限公司 | Universal interface register system and rapid generation method |
| CN114356419B (en) * | 2022-03-14 | 2022-06-07 | 苏州浪潮智能科技有限公司 | Universal interface register system and rapid generation method |
| CN115033516A (en) * | 2022-05-30 | 2022-09-09 | 浙江大学 | Method for realizing multi-wire SPI (Serial peripheral interface) transmission based on multiple single-wire SPI interfaces |
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