CN102012885A - System and method for realizing communication by adopting dynamic I2C bus - Google Patents
System and method for realizing communication by adopting dynamic I2C bus Download PDFInfo
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Abstract
The invention relates to a system and a method for realizing communication by adopting a dynamic I2C bus. The system comprises a host computer and a plurality of slave computers, wherein the host computer is connected with each slave computer through the I2C bus; each slave computer is provided with more than one address bus and an address assignment completion signal output; the slave computers are cascaded by adopting a method that the address assignment completion signal output of the preceding stage slave computer is connected with the address bus of the post-stage slave computer, and one address bus of the first slave computer and the address assignment completion signal output of the last slave computer are connected with the host computer respectively; different I2C addresses are dynamically assigned to each slave computer by the host computer; after an effective address is assigned to the preceding stage slave computer, the post-stage slave computer is activated; and after effective addresses are assigned to all the slave computers, the system performs communication according to a standard I2C bus protocol. In the system and the method, the addresses can be arbitrarily assigned to the slave computers on the basis of maintaining the I2C topology structure and exerting speed of I2C, the control of the host computer over the slave computers is strengthened, the number of chip pins is reduced, and the system is compatible with control commands of the traditional I2C.
Description
Technical field
The present invention is specifically related to a kind of employing dynamic I
2The C bus realizes the system and method for communication.
Background technology
I
2C bus (I2C Bus) is two-way, two lines, serial and many master controls interface standard, has bus arbitration mechanism, is adapted at carrying out closely between the device, non-recurrent data communication.As Fig. 1 is a standard 4bits I
2The C bus, wherein SCK is Master clock, SDA is a bidirectional data line,, A0～A3 is an address bus.This standard 4bits I
2The C bus can be connected with 16 slaves (device) at most, as IC1, IC2 ... IC16.
Because I
2The C bus is used the simple hardware interface of two lines, so it is used more and more widely.But, existing I
2Also there is following deficiency in the C bus, that is: the limited amount of attachable slave; Communication time-delay (referring to the disclosed technology of the patent of invention of patent No. ZL200410077281.7); Slave need have a clock pulse pin position (SCL), a data pin position (SDA), a grounding leg position (GND), an application circuit and the used power supply (VCC) of application circuit, and number of pin is too much, produces, uses all comparatively inconvenience.
Summary of the invention
The objective of the invention is to propose a kind of employing dynamic I
2The C bus realizes the system and method for communication, it can make the slave that is connected with the I2C bus not limit, and each slave reaches the state of synchronous working in communication process, can make the number of pin of each slave significantly reduce simultaneously, thereby overcome deficiency of the prior art.
For achieving the above object, the present invention has adopted following technical scheme:
A kind of employing dynamic I
2The C bus realizes the system of communication, comprises a main frame and a plurality of slave, and main frame is by an I
2The C bus is connected with each slave respectively, it is characterized in that:
An address bus and an address assignment that one or more is set respectively on each slave are finished signal;
An address bus of first slave is connected with main frame, its address assignment finish signal with thereafter the level slave an address bus be connected, follow-up each slave is finished signal according to the address assignment of prime slave and is connected with the address bus ways of connecting of back level slave, and the address assignment of last slave is finished signal and is connected with main frame;
Main frame is to each slave dynamic-configuration different I
2Back level slave after the prime slave is assigned to effective address, is then activated in the C address;
After all slaves all were assigned to effective address, system was according to standard I
2The C bus protocol carries out communication.
Say that further after the prime slave was assigned to effective address, the concrete mistake that activates back level slave was called:
When the address enable of being imported by the address bus of prime slave was noble potential, this prime slave was in state of activation, begins to respond I
2The C bus line command, before obtaining dynamic address, address assignment is finished signal and is output as electronegative potential, and is obtaining dynamic address, finish with main frame shake hands (handshake) afterwards, address assignment is finished signal and is output as noble potential, and order back level slave activates;
Otherwise, if the address enable of being imported by the address bus of prime slave is an electronegative potential, then this prime slave standby, and do not respond I
2The C bus line command, address assignment is finished signal and is output as electronegative potential, back level slave standby.
One address is set in the described main frame deposits a module and a data pointer, at main frame through I
2After the SCL bus of C bus and SDA bus were finished the transmission of an address date, then data pointer pointed to the address automatically and deposits next address data in the module.
Described I
2The form of C order is: Start+ command word+packet+reply+stop, described command word are first kind of address pattern or second kind of address pattern;
When the initial address of a slave enables to be input as low level:
If command word is first kind of address pattern, this slave reads I
2The C bus, calculate the number that SCK rises and prolongs, each SCK rising extension address is deposited module count+1, when the address enable of this slave is input as high level, the address is deposited the module count value and is the effective address that this slave is assigned to, the address is deposited module count and is stopped to add 1, and with address significance bit sign set, this slave addresses has assigned signal and has been output as high level simultaneously;
If command word is second kind of address pattern, this slave does not read I
2The C bus, when the address enable of this slave was input as high level, this slave activated, and reads I
28 bit data of C bus are as effective address, and with address significance bit sign set, this slave addresses has assigned signal and has been output as high level simultaneously;
Described Start and Stop condition are the highest order of priority level, receive I under any condition
2The slave of C order all will respond.
A kind of employing dynamic I
2The C bus realizes the method for communication, it is characterized in that this method is:
One main frame is passed through an I
2The C bus is connected with each slave respectively, an address bus and an address assignment that one or more is set respectively on the described slave are finished signal, each slave adopts the address assignment of prime slave to finish signal and is connected in series successively with the method that an address bus of back level slave is connected, simultaneously, the address assignment of first slave address bus and last slave is finished signal and is connected with main frame respectively;
After the main frame initialization, to each slave dynamic-configuration different I
2The C address;
When the address enable of being imported by the address bus of a slave was noble potential, this slave was in state of activation, begins to respond I
2The C bus line command, before obtaining effective address, address assignment is finished signal and is output as electronegative potential, and obtaining effective address, finish with the handshake (shaking hands) of main frame afterwards, address assignment is finished signal and is output as noble potential, makes the back level slave of this slave activate;
After all slaves all were assigned to effective address, system was according to standard I
2The C bus protocol carries out communication.
Particularly, described I
2The form of C order is: Start+ command word+packet+reply+stop, described command word are two kinds of address patterns;
If the initial address of a slave enables to be input as low level, then:
If command word is first kind of address pattern, this slave reads I
2The C bus, calculate the number that SCK rises and prolongs, each SCK rising extension address is deposited module count+1, when the address enable of this slave is input as high level, the address is deposited the module count value and is the effective address that this slave is assigned to, the address is deposited module count and is stopped to add 1, and with address significance bit sign set, this slave addresses has assigned signal and has been output as high level simultaneously;
If command word is second kind of address pattern, this slave does not read I
2The C bus, when the address enable of this slave was input as high level, this slave activated, and reads I
28 bit data of C bus are as effective address, and with address significance bit sign set, this slave addresses has assigned signal and has been output as high level simultaneously.
Described Start and Stop condition are the highest order of priority level, receive I under any condition
2The slave of C order all will respond.
One address is set in the described main frame deposits a module and a data pointer, at main frame through I
2After the SCL bus of C bus and SDA bus were finished the transmission of an address date, then data pointer pointed to the address automatically and deposits next address data in the module.
Compared with prior art, beneficial effect of the present invention is:
(1) can keep I
2The topological structure of C, the speed of performance I2C;
(2) can as required the ADDR_COUNT length of slave be set,, can reduce pin of chip quantity especially for integrated circuit;
(3) can distribute the address to slave arbitrarily, be convenient to the control of main frame slave;
(4) control command of system and traditional I
2C control command compatibility, and only need expand its instruction set.
Description of drawings
Fig. 1 is existing a kind of standard I
2The structural representation of C bus;
Fig. 2 is a kind of employing dynamic I in the specific embodiment of the invention
2The C bus realizes the system architecture synoptic diagram of communication;
Fig. 3 is an employing dynamic I shown in Figure 2
2The C bus realizes that the system of communication adopts the workflow diagram of first kind of dynamic address allocation pattern;
Fig. 4 is an employing dynamic I shown in Figure 2
2The C bus realizes that the system of communication adopts the workflow diagram of second kind of dynamic address allocation pattern;
Fig. 5 is the structural representation of the present invention's one application example;
Fig. 6 is the workflow diagram that the present invention's one application example shown in Figure 5 adopts first kind of dynamic address allocation pattern;
Fig. 7 is the workflow diagram that the present invention's one application example shown in Figure 5 adopts second kind of dynamic address allocation pattern.
Embodiment
As shown in Figure 2, the present invention adopts dynamic I
2The C bus realizes that the system of communication comprises a main frame and a plurality of slave, and the main frame (not shown) is by an I
2C bus (comprising clock line SCK, bidirectional data line SDA) by host computer control respectively with each slave IC1, IC2 ... ICn connects, and finishes signal READY output port but an address bus and the address assignment that a transport address enables A0 is set respectively on each slave;
The address bus of first slave IC1 is connected with main frame, its address assignment is finished signal output and is connected with the address bus of slave IC2, follow-up each slave is finished signal output according to the address assignment of prime slave and is connected (promptly with the address bus ways of connecting of back level slave, the connected mode of daisy chain), the address assignment of slave ICn is finished signal output and is connected (not shown) with main frame.
This adopts dynamic I
2The C bus realizes in the system of communication, and main frame is by the communication between address mode control and the slave, and by the main frame (I that gives an order
2The C bus line command) data transmission between startup and the slave.
Postscript, dynamic I among the present invention
2C communications protocol and standard I
2The C unanimity, but in the control of address, adopt the dynamic assignment structure, that is, give slave by the host assignment dynamic address.
Among the present invention, for arbitrary slave, if the address enable A0 of input is an electronegative potential, then this slave is in " wait " state, does not respond I
2The C bus line command, and its address assignment is finished signal REDAY and is output as low level; And if the address enable A0 of input is a noble potential, then this slave is in state of activation, begins to respond I
2The C bus line command, and its address assignment is finished signal and is output as high level, before obtaining dynamic (effectively) address, its address assignment is finished signal REDAY and is output as electronegative potential, until obtaining dynamically (effectively) address, and finish with main frame handshake after, address assignment is finished signal REDAY and is output as noble potential.
Otherwise, if the address enable of being imported by the address bus of prime slave is an electronegative potential, then this prime slave standby, and do not respond I
2The C bus line command, address assignment is finished signal and is output as electronegative potential, back level slave standby;
After all slaves all were assigned to effective address, system was according to standard I
2The C bus protocol carries out communication.
One address is set in the described main frame deposits a module and a data pointer, at main frame through I
2After the SCL bus of C bus and SDA bus were finished the transmission of an address date, then data pointer pointed to the address automatically and deposits next address data in the module.
Described I
2The form of C order is: Start+ command word+packet+reply+stop, described command word are first kind of address pattern (address pattern " 0 " as shown in Figure 3) or second kind of address pattern (address pattern " 1 " as shown in Figure 4);
When the initial address of a slave enables to be input as low level: (A0=" 0 ")
If command word is first kind of address pattern, this slave reads I
2The C bus, calculate the number that SCK rises and prolongs, each SCK rises and prolongs ADDR_COUNT (module is deposited in the address)+1, when the address enable of this slave is input as high level (A0=" 1 "), ADDR_COUNT is the effective address that this slave is assigned to, ADDR_COUNT stops to add 1, and with ADDR_FLAG (effective address zone bit) set, this slave addresses has assigned signal and has been output as high level simultaneously;
If command word is second kind of address pattern, this slave does not read I
2The C bus, when the address enable of this slave was input as high level, this slave activated, and reads I
28 bit data of C bus are as effective address, and simultaneously with the ADDR_FLAG set, this slave addresses has assigned signal and has been output as high level;
Described Start and Stop condition are the highest order of priority level, receive I under any condition
2The slave of C order all will respond.
Above-mentioned ADDR_COUNT, ADDR_FLAG etc. are I
2C bus internal register.
Be an application example of the present invention as shown in Figure 5, it relates to a LED display drive system, comprise a MCU and some chip for driving Q0, Q1, Q2 ... Qn, system is controlled by MCU, and this MCU by its pin P30, P31 by setting up two-way data communication between SCL, SDA bus and the chip for driving Q0～Qn, simultaneously, MCU also finishes signal output by the address bus of pin P33, P32 and chip for driving Q0 with the address assignment of chip for driving Qn respectively and is connected.
During this system works, MCU gives earlier chip Q0～Qn configuration address, just can realize two-way data communication after finishing address configuration, and the information that will show is dealt into chip Q0～Qn, and the while also can read the internal information of chip Q0～Qn.
MCU can adopt two kinds of patterns for chip Q0～Qn configuration address, first kind of pattern is dynamic address pattern " 0 " (as shown in Figure 6), after the MCU initialization, produce the Start condition, send dynamic address pattern " 0 " command word, chip address enables to import A0＜=" 1 " (promptly, high level), SCL produces count pulse, the address assignment of MCU supervision chip Qn is finished signal READY output, when receiving READY=" 1 " (high level) signal, then chip Q1～Qn all is assigned to effective address, finishes the configuration of dynamic address pattern " 0 ".First kind of pattern is dynamic address pattern " 1 " (as shown in Figure 7), after the MCU initialization, produce the Start condition, send dynamic address pattern " 1 " command word, chip address enables to import A0＜=" 1 " (promptly, high level), system will will the addresses distributed data storing deposit in the module in an address according to needs, one data pointer DP is set simultaneously, SCL, SDA sends " data byte " (address date), whenever finish a byte and send, DP adds 1, points to the next address data, the address assignment of MCU supervision chip Qn is finished signal READY output, when receiving READY=" 1 " (high level) signal, then chip Q1～Qn all is assigned to effective address, finishes the configuration of dynamic address pattern " 1 ".
Claims (8)
1. one kind is adopted dynamic I
2The C bus realizes the system of communication, comprises a main frame and a plurality of slave, and main frame is by an I
2The C bus is connected with each slave respectively, it is characterized in that:
An address bus and an address assignment that one or more is set respectively on each slave are finished signal;
An address bus of first slave is connected with main frame, its address assignment finish signal with thereafter the level slave an address bus be connected, follow-up each slave is finished signal according to the address assignment of prime slave and is connected with the address bus ways of connecting of back level slave, and the address assignment of last slave is finished signal and is connected with main frame;
Main frame is to each slave dynamic-configuration different I
2Back level slave after the prime slave is assigned to effective address, is then activated in the C address;
After all slaves all were assigned to effective address, system was according to standard I
2The C bus protocol carries out communication.
2. employing dynamic I as claimed in claim 1
2The C bus realizes the system of communication, it is characterized in that, after the prime slave was assigned to effective address, the concrete mistake that activates back level slave was called:
When the address enable of being imported by the address bus of prime slave was noble potential, this prime slave was in state of activation, begins to respond I
2The C bus line command, before obtaining dynamic address, address assignment is finished signal and is output as electronegative potential, and is obtaining dynamic address, finish with the shaking hands of main frame after, address assignment is finished signal and is output as noble potential, and order back level slave activates;
Otherwise, if the address enable of being imported by the address bus of prime slave is an electronegative potential, then this prime slave standby, and do not respond I
2The C bus line command, address assignment is finished signal and is output as electronegative potential, back level slave standby.
3. employing dynamic I as claimed in claim 1 or 2
2The C bus realizes the system of communication, it is characterized in that, an address is set in the described main frame deposits a module and a data pointer, at main frame through I
2After the SCL bus of C bus and SDA bus were finished the transmission of an address date, then data pointer pointed to the address automatically and deposits next address data in the module.
4. employing dynamic I as claimed in claim 2
2The C bus realizes the system of communication, it is characterized in that,
Described I
2The form of C order is: Start+ command word+packet+reply+Stop, described command word are first kind of address pattern or second kind of address pattern;
When the initial address of a slave enables to be input as low level:
If command word is first kind of address pattern, this slave reads I
2The C bus, calculate the number that SCK rises and prolongs, each SCK rising extension address is deposited module count+1, when the address enable of this slave is input as high level, the count value that module is deposited in the address is the effective address that this slave is assigned to, the address is deposited module count and is stopped to add 1, and with address significance bit sign set, this slave addresses has assigned signal and has been output as high level simultaneously;
If command word is second kind of address pattern, this slave does not read I
2The C bus, when the address enable of this slave was input as high level, this slave activated, and reads I
28 bit data of C bus are as effective address, and with address significance bit sign set, this slave addresses has assigned signal and has been output as high level simultaneously;
Described Start and Stop condition are the highest order of priority level, receive I under any condition
2The slave of C order all will respond.
5. one kind is adopted dynamic I
2The C bus realizes the method for communication, it is characterized in that this method is:
One main frame is passed through an I
2The C bus is connected with each slave respectively, an address bus and an address assignment that one or more is set respectively on the described slave are finished signal, each slave adopts the address assignment of prime slave to finish signal and is connected in series successively with the method that an address bus of back level slave is connected, simultaneously, the address assignment of first slave address bus and last slave is finished signal and is connected with main frame respectively;
After the main frame initialization, to each slave dynamic-configuration different I
2The C address;
When the address enable of being imported by the address bus of a slave was noble potential, this slave was in state of activation, begins to respond I
2The C bus line command, before obtaining effective address, address assignment is finished signal and is output as electronegative potential, and is obtaining effective address, finish with the shaking hands of main frame after, address assignment is finished signal and is output as noble potential, makes the back level slave of this slave activate;
After all slaves all were assigned to effective address, system was according to standard I
2The C bus protocol carries out communication.
6. employing dynamic I as claimed in claim 5
2The C bus realizes the method for communication, it is characterized in that,
Described I
2The form of C order is: Start+ command word+packet+reply+Stop, described command word are two kinds of address patterns;
If the initial address of a slave enables to be input as low level, then:
If command word is first kind of address pattern, this slave reads I
2The C bus, calculate the number that SCK rises and prolongs, each SCK rising extension address is deposited module count+1, when the address enable of this slave is input as high level, the address is deposited the module count value and is the effective address that this slave is assigned to, the address is deposited module count and is stopped to add 1, and with address significance bit sign set, this slave addresses has assigned signal and has been output as high level simultaneously;
If command word is second kind of address pattern, this slave does not read I
2The C bus, when the address enable of this slave was input as high level, this slave activated, and reads I
28 bit data of C bus are as effective address, and with address significance bit sign set, this slave addresses has assigned signal and has been output as high level simultaneously.
7. employing dynamic I as claimed in claim 6
2The C bus realizes the method for communication, it is characterized in that described Start and Stop condition are the highest order of priority level, receive I under any condition
2The slave of C order all will respond.
8. employing dynamic I as claimed in claim 5
2The C bus realizes the method for communication, it is characterized in that, an address is set in the described main frame deposits a module and a data pointer, at main frame through I
2After the SCL bus of C bus and SDA bus were finished the transmission of an address date, then data pointer pointed to the address automatically and deposits next address data in the module.
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| CN201010281354XA CN102012885A (en) | 2010-09-15 | 2010-09-15 | System and method for realizing communication by adopting dynamic I2C bus |
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| CN103336486A (en) * | 2012-12-19 | 2013-10-02 | 惠州市亿能电子有限公司 | Method for battery module address assignment of battery energy storage system |
| CN104125047A (en) * | 2013-04-24 | 2014-10-29 | 精工爱普生株式会社 | Communication circuit, physical quantity measurement device, electronic apparatus, and communication method |
| CN104125047B (en) * | 2013-04-24 | 2019-05-03 | 精工爱普生株式会社 | Telecommunication circuit, physical amount measuring device, electronic equipment, communication means |
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| CN108616610A (en) * | 2018-05-21 | 2018-10-02 | 深圳前海有电物联科技有限公司 | Address distribution method, host, slave and bus system |
| CN110083570A (en) * | 2019-04-16 | 2019-08-02 | 深圳市致宸信息科技有限公司 | A kind of multi-chip series connection automatic address coded system and method |
| CN110290227A (en) * | 2019-05-28 | 2019-09-27 | 广州大学 | Dynamic allocation method, system and the storage medium of IC bus address |
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| CN114967570A (en) * | 2022-07-27 | 2022-08-30 | 深圳市汤诚科技有限公司 | I2C slave address programmable control circuit structure and control method |
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Application publication date: 20110413 |