CN101609442B - Interface self-adapting method, device and system thereof - Google Patents

Interface self-adapting method, device and system thereof Download PDF

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CN101609442B
CN101609442B CN2009102036863A CN200910203686A CN101609442B CN 101609442 B CN101609442 B CN 101609442B CN 2009102036863 A CN2009102036863 A CN 2009102036863A CN 200910203686 A CN200910203686 A CN 200910203686A CN 101609442 B CN101609442 B CN 101609442B
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interface
pcie
module
information
pcie card
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CN101609442A (en
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周誉
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Chengdu Huawei Technology Co Ltd
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Huawei Symantec Technologies Co Ltd
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Abstract

The invention discloses an interface self-adapting method, a device and a system thereof, wherein the method comprises the following steps of: obtaining the type information of a PCIE card or module which is inserted in the PCIE interfaces that are quickly connected with each other of external components; and changing the configuration information of the PCIE interfaces in accordance with the type information of the PCIE card or module, wherein the type information comprises the interface quantity information and the channel quantity information of each interface which are required by the PCIE card or module. The embodiment of the invention leads the PCIE interfaces of single fixed physical bandwidth to self-adaptively support the PCIE card or module with at least two chips, thus not only avoiding transmission delay caused by using PCIE exchange chips, but also being capable of making full use of the bandwidth of the PCIE interfaces, ensuring the system performance, and leading the use to be convenient.

Description

A kind of method of interface adaptive and device thereof, system
Technical field
The present invention relates to field of data transmission, especially relate to a kind of method of interface adaptive and device thereof, system.
Background technology
Peripheral component interconnection (PCIE, Peripheral Component Interconnect Express) adopted popular in the industry method point-to-point connected in series at present, the equipment on each PCIE interface that makes all has the special use of oneself to connect, and improves data transmission efficiency greatly; Therefore the PCIE interface has replaced early stage pci interface, particularly is widely used on the system interface of computer display card.
The PCIE interface has the X1 passage, the X2 passage, and the X4 passage, the X8 passage, the X12 passage, various bandwidth specifications such as X16 passage, and be the access port of PCIE card.Usually, chip on the PCIE card and interface channel number specification adapt.
In order to improve the integrated level of every PCIE card, can use 2 chips on the part PCIE card, promptly this PCIE calorie requirement carries out data transmission by 2 interfaces that the interface channel number is corresponding with chip with master control borad.The common way of prior art is to connect a PCIE exchange chip on the PCIE card again, for example 2 X4 interfaces on the PCIE card are passed through the PCIE exchange chip, be exchanged into an X4 interface, the PCIE cartoon is crossed on the PCIE interface that the PCIE exchange chip is inserted into the X4 of system passage, satisfies and uses needs.
In research and practice process to prior art, the present inventor finds to exist following problem:
When on individual PCIE card, having 2 chips, need to use exchange chip could guarantee that this blocks and being connected of system; And behind the use exchange chip, 2 X4 interface chips on the PCIE card can only be shared the bandwidth of an X4 interface or X8 interface, and data must be transmitted the transmission delay of increase data through exchange chip.
Summary of the invention
The embodiment of the invention provides a kind of method of the interface adaptive that does not use exchange chip and device thereof, system, reduces time-delay, makes full use of the bandwidth of PCIE interface, guarantees system performance.
For solving the problems of the technologies described above, embodiment provided by the present invention is achieved through the following technical solutions:
A kind of method of interface adaptive comprises:
Obtain the PCIE card or the type of module information that are inserted on the peripheral component high speed interconnect PCIE interface, type information comprises the interface information of number of PCIE card or module needs and the number of active lanes information of each interface;
At the overall channel number of PCIE card or module during smaller or equal to the physical channel number of PCIE interface, the configuration information of change PCIE interface; The overall channel number is the interface information of number of PCIE card or module needs and the amassing of number of active lanes of each interface.
A kind of device of interface adaptive comprises:
Acquiring unit is used to obtain the PCIE card or the type of module information that are inserted on the PCIE interface, and described type information comprises the interface information of number of PCIE card or module needs and the number of active lanes information of each interface;
The configuration change unit is used at the overall channel number of PCIE card or module during smaller or equal to the physical channel number of PCIE interface the configuration information of change PCIE interface; The overall channel number is the interface information of number of PCIE card or module needs and the amassing of number of active lanes of each interface.
A kind of system of interface adaptive comprises:
PCIE card or module are used for providing type information to logical circuit, and type information comprises the interface information of number of PCIE card or module needs and the number of active lanes information of each interface;
Master control borad is used to obtain the PCIE card or the type of module information that are inserted on the PCIE interface, and during smaller or equal to the physical channel number of PCIE interface, changes the configuration information of described PCIE interface at the overall channel number of PCIE card or module; The overall channel number is the interface information of number of PCIE card or module needs and the amassing of number of active lanes of each interface.
By technique scheme as can be seen, the embodiment of the invention is inserted into the interface number that PCIE card on the PCIE interface or module need and the number of active lanes of each interface by detection, the PCIE interface configuration signal configures of master control borad chipset is become PCIE card or the interface information of number of module needs and the number of active lanes information of each interface, the PCIE interface of then single fixed physical bandwidth can support to have the PCIE card or the module of at least two chips adaptively, make the bandwidth of PCIE interface be fully utilized, and reduce the data transmission time-delay.
Description of drawings
In order to be illustrated more clearly in the technical scheme in the embodiment of the invention, the accompanying drawing of required use is done to introduce simply in will describing embodiment below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the method flow synoptic diagram of the embodiment of the invention one;
Fig. 2 is the method flow synoptic diagram of the embodiment of the invention two;
Fig. 3 is the method flow synoptic diagram of the embodiment of the invention three;
Fig. 4 is the structural representation of embodiment of the invention device;
Fig. 5 is the structural representation of embodiment of the invention system.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that is obtained under the creative work prerequisite.
It below is the specific embodiment of the invention.
Embodiment one, describe in detail referring to Fig. 1, Fig. 1 is the method flow synoptic diagram of present embodiment.
Step 101: obtain the PCIE card or the type of module information that are inserted on the PCIE interface, the type information comprises the interface information of number of PCIE card or module needs and the number of active lanes information of each interface.
The logical circuit of master control borad obtains PCIE card or type of module information, the signal that can detect by self-defined pin from PCIE card or module, or by out-of-band communication interface (I2C) the visit PCIE card of PCIE card or module or the Erasable Programmable Read Only Memory EPROM (EEPROM on the module, Electrically Erasable Programmable ROM) signal in obtains, or the System Management Bus (SMB by PCIE card or module, System Management Bus) signal among the EEPROM on interface accessing PCIE card or the module obtains, and does not influence the realization of the embodiment of the invention.Obviously, other obtain manners by other protocol interfaces obtain the realization that the PCIE card that is inserted on the PCIE interface or type of module information do not influence the embodiment of the invention yet.
Obtain the PCIE card or the type of module information that are inserted on the PCIE interface, can be to obtain a PCIE card or the type of module information on the PCIE interface, or PCIE card on a plurality of PCIE interfaces or type of module information, do not influence the realization of the embodiment of the invention.
Step 102: according to PCIE card or type of module information, the configuration information of change PCIE interface.
The configuration information of the logical circuit change PCIE interface of master control borad comprises: the logical circuit of master control borad sends PCIE card or type of module information to the master control borad chipset, the configuration information of change PCIE interface.
The master control borad chipset can be the south bridge or the north bridge chipset of master control borad.
After the configuration information of PCIE interface is modified to PCIE card or type of module information, the master control borad chipset then sends and PCIE card or the corresponding clock signal of type of module information to the PCIE interface, and the number of clock signal is identical with the interface number that PCIE card or module need.
Clock signal is used for each device of synchro system (central processing unit, storer, system bus etc.) work, and concrete form can be a pulse signal that sends every one equal period.
Also can at the overall channel number of PCIE card or module during, just change the configuration information of PCIE interface, then can make full use of the bandwidth of this PCIE interface, help improving data transmission efficiency smaller or equal to the physical channel number of PCIE interface.The overall channel number of PCIE card or module is the amassing of number of active lanes of interface number and each interface of PCIE calorie requirement.
The embodiment of the invention has been avoided needing to adopt the support of PCIE exchange chip to have the PCIE card or the module of at least two chips in the prior art, the method of a plurality of PCIE cards or the shared PCIE interface bandwidth of module, but obtain PCIE card or the interface number of module needs and the number of active lanes of each interface by master control borad, directly the PCIE interface adaptive ground of single fixed physical bandwidth is supported to have the PCIE card or the module of at least two chips, not only avoided the transmission delay that uses the PCIE exchange chip to bring, and can make full use of the bandwidth of PCIE interface, guarantee system performance, and easy to use.
Following examples two are the Application Example of embodiment one, and the PCIE card that has 2 X4 channel chip with the PCIE interface adaptive support with 1 X8 passage is that example is elaborated.The PCIE card that the following embodiment of the invention two and embodiment three mention also can be that other are inserted into the application module on the PCIE of the system interface, does not influence the realization of the embodiment of the invention.
Embodiment two, describe in detail referring to Fig. 2, Fig. 2 is the method flow synoptic diagram of present embodiment.
Step 201: system standby power supply electrifying, the PCIE card that has 2 chips is inserted on the PCIE interface of X8 passage, PCIE card transmission types information is given the master control borad logical circuit, and type information comprises the interface information of number of PCIE calorie requirement and the number of active lanes information of each interface.
Type information can be sent by the self-defined pin of PCIE card, also can be by the out-of-band communication interface of PCIE card or the type information signal among the EEPROM on the System Management Bus interface transmission PCIE card.
Self-defined pin can be the undefined pin of unknown neighbor on the PCIE card, as the Pin32 of SideA, Pin33.
The self-defining mode of pin can be the type information signal that pre-defines each signal representative.For example, the length of the signal on the self-defined pin is 3 bits, and promptly the type information of 000 expression PCIE card is the interface of 1 X8 passage, the interface of 2 X4 passages of 001 expression etc.Obviously, other pin definitions method does not influence the realization of the embodiment of the invention yet.
Step 202: the master control borad logical circuit obtains the type information of PCIE card, learns the interface of 2 X4 passages of this PCIE calorie requirement.
Step 203: the master control borad logical circuit is to master control borad chipset output type information.
When the length of the signal on self-defined pin was 3 bits, type information was signal such as 000,001.
The master control borad chipset can be the south bridge or the north bridge chipset of master control borad.
Step 204: system's primary power powers on.
Step 205: with the PCIE interface configuration information change on the master control borad chipset is the interface message of 2 X4 passages.
The same prior art of information change process repeats no more.
Step 206: the master control borad chipset sends corresponding signal and 2 tunnel definition clocks to the interface of 2 X4 passages.
Clock signal is used for each device of synchro system (central processing unit, storer, system bus etc.) work, and concrete form can be a pulse signal that sends every one equal period.
The PCIE interface then can support to have the PCIE card of 2 chips after receiving the signal and 2 tunnel definition clocks of interface correspondence of 2 X4 passages, realizes the proper communication of this PCIE card and master control borad.
Present embodiment two is an example with the PCIE card that the interface adaptive with 1 X8 passage becomes to support to have the chip of 2 X4 passages, obviously, the interface adaptive of 1 X8 passage is become to support to have the PCIE card of 4 X2 channel chip, or self-adaptation becomes to support to have the PCIE card of 8 X1 channel chip, or the interface adaptive of 1 X16 passage become to support to have the PCIE card of 2 X8 channel chip etc., do not influence the realization of the embodiment of the invention.
The embodiment of the invention is obtained the number of active lanes of interface number He each interface of PCIE calorie requirement by master control borad, directly with the PCIE interface adaptive of single fixed physical bandwidth be configured to support to have the PCIE card of at least two chips, avoided the transmission delay that uses the PCIE exchange chip to bring, and can make full use of the bandwidth of PCIE interface, guarantee system performance, easy to use.
Following examples three are the Application Example of embodiment one, with the PCIE interface of 2 X8 passages of system respectively the self-adaptation PCIE card that becomes to support to have the PCIE card of 1 X8 channel chip, 2 X4 channel chip be that example is elaborated.
Embodiment three, describe in detail referring to Fig. 3, Fig. 3 is the method flow synoptic diagram of present embodiment.
Step 301: system standby power supply electrifying, 2 PCIE cards are inserted on the PCIE interface A and PCIE interface B of X8 passage, PCIE card transmission types information is given the master control borad logical circuit, and type information comprises the interface information of number of PCIE calorie requirement and the number of active lanes information of each interface.
Step 302: the master control borad logical circuit obtains the type information of 2 PCIE cards, learns the PCIE interface of 1 the X8 passage of PCIE calorie requirement on the PCIE interface A, the PCIE interface of 2 the X4 passages of PCIE calorie requirement on the PCIE interface B.
Obviously, if the PCIE card on the PCIE interface A also needs the PCIE interface of 2 X4 passages, or during the PCIE interface of other numbers, do not influence the realization of the embodiment of the invention yet.
Step 303: the master control borad logical circuit is to master control borad chipset transmission types information.
Step 304: system's primary power powers on.
Step 305: it is the PCIE interface of 1 X8 passage that the PCIE interface configuration information change on the master control borad chipset is become PCIE interface A, and PCIE interface B is the information of the PCIE interface of 2 X4 passages.
Step 306: the master control borad chipset sends the signal and 1 tunnel definition clock of 1 corresponding X8 passage to PCIE interface A; Send the signal and 2 tunnel definition clocks of 2 corresponding X4 passages to PCIE interface B.
Clock signal is used for each device of synchro system (central processing unit, storer, system bus etc.) work, and concrete form can be a pulse signal that sends every one equal period.
The PCIE interface receives out the signal of PCIE interface A and PCIE interface B correspondence, and behind the definition clock of two interface correspondences, then can support 2 PCIE cards that have different number chips, realizes the proper communication of this PCIE card and master control borad.
Present embodiment three with the PCIE interface of 2 X8 passages of system respectively the self-adaptation PCIE card that becomes to support to have the PCIE card of 1 X8 channel chip, 2 X4 channel chip be example, obviously, the interface adaptive of the interface of the X8 passage more than 2 or 2 X16 passages is become to have the PCIE card of other number chips, do not influence the realization of the embodiment of the invention.
The embodiment of the invention is obtained the number of active lanes of interface number He each interface of PCIE calorie requirement by master control borad, directly the PCIE interface of two fixed physical bandwidth is configured to support to have adaptively the PCIE card of different core numbers respectively, avoided the transmission delay that uses the PCIE exchange chip to bring, and can make full use of the bandwidth of PCIE interface, guarantee system performance, easy to use.
The PCIE card that the above embodiment of the invention is mentioned also can be that other are inserted into the application module on the PCIE of the system interface, does not influence the realization of the embodiment of the invention.
Need to prove, for aforesaid each method embodiment, for simple description, so it all is expressed as a series of combination of actions, but those skilled in the art should know, the present invention is not subjected to the restriction of described sequence of movement, because according to the present invention, some step can adopt other orders or carry out simultaneously.Secondly, those skilled in the art also should know, the embodiment described in the instructions all belongs to preferred embodiment, and related action and module might not be that the present invention is necessary.
In the above-described embodiments, the description of each embodiment is all emphasized particularly on different fields, do not have the part that describes in detail among certain embodiment, can be referring to the associated description of other embodiment.
A kind of method of interface adaptive more than is provided, and the embodiment of the invention also provides a kind of device of interface adaptive.
A kind of device of interface adaptive, referring to Fig. 4, Fig. 4 is the structural representation of embodiment of the invention device, comprising:
Acquiring unit 41 is used to obtain the PCIE card or the type of module information that are inserted on the PCIE interface, and type information comprises the number of active lanes of interface number He each interface of PCIE card or module needs; The signal that can detect by self-defined pin from PCIE card or module, perhaps, obtain the PCIE card or the type of module information that are inserted on the PCIE interface by the out-of-band communication interface of PCIE card or module or the signal in the Erasable Programmable Read Only Memory EPROM on System Management Bus interface accessing PCIE card or the module.
Configuration change unit 42 is used for PCIE card or the type of module information obtained according to acquiring unit 41, changes the configuration information of described PCIE interface; Can also be during smaller or equal to the physical channel number of PCIE interface, to change the configuration information of described PCIE interface at the overall channel number of PCIE card or module; The overall channel number is the interface information of number of PCIE card or module needs and the amassing of number of active lanes of each interface.
Behind the PCIE card or type of module information that configuration change unit 42 obtains, can send PCIE card or type of module information, change to and the corresponding configuration information of type information by the configuration information of master control borad chipset again the PCIE interface to the master control borad chipset.
Each module of embodiment of the invention equipment can be integrated in one, and also can separate deployment.Above-mentioned module can be merged into a module, also can further split into a plurality of submodules.
A kind of system of interface adaptive, referring to Fig. 5, Fig. 5 is the structural representation of embodiment of the invention system, comprising:
PCIE card or module 51 are used for providing type information to master control borad 52, and type information comprises the interface information of number of PCIE card or module needs and the number of active lanes information of each interface.
Master control borad 52 is used to obtain the PCIE card that is inserted on the PCIE interface or the type information of module 51, and according to PCIE card or type of module information, changes the configuration information of described PCIE interface.
Master control borad 52 is also to PCIE card or module 51 tranmitting data register signals, and the number of clock signal is identical with the interface number that PCIE card or module 51 need.
The signal that can detect by self-defined pin from PCIE card or module, perhaps, obtain the PCIE card or the type of module information that are inserted on the PCIE interface by the out-of-band communication interface of PCIE card or module or the signal in the Erasable Programmable Read Only Memory EPROM on the System Management Bus interface accessing PCIE card.
Master control borad 52 can be divided into logical circuit and chipset, logical circuit obtains the PCIE card that is inserted on the PCIE interface or the type information of module 51, and, change to and the corresponding configuration information of type information by the configuration information of chipset with the PCIE interface to the type information of chipset output PCIE card or module 51.Chipset can be the south bridge or the north bridge chipset of master control borad, does not influence the realization of the embodiment of the invention.
Embodiment of the invention device and system obtain PCIE card or the interface number of module needs and the number of active lanes of each interface by master control borad, can be directly the PCIE interface of the fixed physical bandwidth of system be configured to support to have the PCIE card or the module of at least two chips respectively adaptively, avoided the transmission delay that uses the PCIE exchange chip to bring, and can make full use of the bandwidth of PCIE interface, guarantee system performance, easy to use.
One of ordinary skill in the art will appreciate that, realize all or part of flow process in the foregoing description method, be to instruct relevant hardware to finish by computer program, program can be stored in the computer read/write memory medium, this program can comprise the flow process as the embodiment of above-mentioned each side method when carrying out.Wherein, storage medium can be magnetic disc, CD, read-only storage memory body (Read-Only Memory, ROM) or at random store memory body (Random Access Memory, RAM) etc.
More than the method for a kind of interface adaptive that the embodiment of the invention provided and device thereof, system are described in detail, used specific case herein principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.

Claims (8)

1. the method for an interface adaptive is characterized in that, comprising:
Obtain the PCIE card or the type of module information that are inserted on the peripheral component high speed interconnect PCIE interface, described type information comprises the interface information of number of PCIE card or module needs and the number of active lanes information of each interface;
During smaller or equal to the physical channel number of PCIE interface, change the configuration information of described PCIE interface at the overall channel number of PCIE card or module; Described overall channel number is the interface information of number of PCIE card or module needs and the amassing of number of active lanes of each interface.
2. method according to claim 1 is characterized in that, obtains the PCIE card or the type of module information that are inserted on the PCIE interface and comprises:
By the signal that the self-defined pin from PCIE card or module detects, obtain the PCIE card or the type of module information that are inserted on the PCIE interface; Perhaps
By the out-of-band communication interface of PCIE card or module or the signal in the Erasable Programmable Read Only Memory EPROM on System Management Bus interface accessing PCIE card or the module, obtain the PCIE card or the type of module information that are inserted on the PCIE interface.
3. method according to claim 1 is characterized in that, described overall channel number in PCIE card or module is during smaller or equal to the physical channel number of PCIE interface, and the configuration information of changing described PCIE interface comprises:
Send PCIE card or type of module information to the master control borad chipset;
Change to and the corresponding configuration information of described type information by the configuration information of master control borad chipset described PCIE interface.
4. method according to claim 3 is characterized in that, described method also comprises:
The master control borad chipset sends and PCIE card or the corresponding clock signal of type of module information to the PCIE interface, and the number of clock signal is identical with the interface number that PCIE card or module need.
5. the device of an interface adaptive is characterized in that, comprising:
Acquiring unit is used to obtain the PCIE card or the type of module information that are inserted on the PCIE interface, and described type information comprises the interface information of number of PCIE card or module needs and the number of active lanes information of each interface;
The configuration change unit is used at the overall channel number of PCIE card or module changing the configuration information of described PCIE interface during smaller or equal to the physical channel number of PCIE interface; The overall channel number is the interface information of number of PCIE card or module needs and the amassing of number of active lanes of each interface.
6. device according to claim 5 is characterized in that:
Acquiring unit obtains the PCIE card or the type of module information that are inserted on the PCIE interface by the signal that the self-defined pin from PCIE card or module detects; Perhaps
Acquiring unit obtains the PCIE card or the type of module information that are inserted on the PCIE interface by the out-of-band communication interface of PCIE card or module or the signal in the Erasable Programmable Read Only Memory EPROM on System Management Bus interface accessing PCIE card or the module.
7. according to claim 5 or 6 described devices, it is characterized in that:
The configuration change unit is used for sending PCIE card or type of module information to the master control borad chipset; Change to and the corresponding configuration information of described type information by the configuration information of master control borad chipset described PCIE interface.
8. the system of an interface adaptive is characterized in that, comprising:
PCIE card or module are used for providing type information to logical circuit, and type information comprises the interface information of number of PCIE card or module needs and the number of active lanes information of each interface;
Master control borad is used to obtain the PCIE card or the type of module information that are inserted on the PCIE interface, and during smaller or equal to the physical channel number of PCIE interface, changes the configuration information of described PCIE interface at the overall channel number of PCIE card or module; The overall channel number is the interface information of number of PCIE card or module needs and the amassing of number of active lanes of each interface.
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WO2012119385A1 (en) 2011-08-11 2012-09-13 华为技术有限公司 Method, device and system for performing time synchronization on pcie device
WO2014036725A1 (en) * 2012-09-07 2014-03-13 华为技术有限公司 Method, device and equipment for pcie port configuration
CN103098039B (en) * 2012-10-17 2016-05-25 华为技术有限公司 High-speed peripheral device interconnection bus port collocation method and equipment
CN103972735A (en) * 2013-01-30 2014-08-06 鸿富锦精密电子(天津)有限公司 Signal switching circuit and PCIE connector combination comprising signal switching circuit
KR102309907B1 (en) * 2013-08-29 2021-10-06 단 오프레아 Method and apparatus to manage the direct interconnect switch wiring and growth in computer networks
CN104714910B (en) * 2013-12-17 2018-11-30 研祥智能科技股份有限公司 The method and system of adaptive configuration PCIE bus interface
CN107257444B (en) * 2017-05-08 2018-10-09 广州美凯信息技术股份有限公司 A kind of host interface adaptive approach and device
CN109753460A (en) * 2017-11-06 2019-05-14 中兴通讯股份有限公司 A kind of storage equipment and storage system
CN110166301A (en) * 2019-05-28 2019-08-23 浪潮商用机器有限公司 A kind of method of automatic configuration, device, system and the controller of the port PCIE
CN111008162A (en) * 2019-11-22 2020-04-14 苏州浪潮智能科技有限公司 Method and system for realizing single PCIE slot supporting multiple PCIE ports
CN111723037A (en) * 2020-06-19 2020-09-29 浪潮电子信息产业股份有限公司 PCIE interface extension system and server
CN112685347A (en) * 2020-12-31 2021-04-20 西安易朴通讯技术有限公司 Compatible method and device for PCIE (peripheral component interface express) equipment with different bandwidths and server
CN115277407B (en) * 2022-07-25 2024-01-23 北京天融信网络安全技术有限公司 Internet access configuration processing method and device, electronic equipment and storage medium

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