Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that is obtained under the creative work prerequisite.
It below is the specific embodiment of the invention.
Embodiment one, describe in detail referring to Fig. 1, Fig. 1 is the method flow synoptic diagram of present embodiment.
Step 101: obtain the PCIE card or the type of module information that are inserted on the PCIE interface, the type information comprises the interface information of number of PCIE card or module needs and the number of active lanes information of each interface.
The logical circuit of master control borad obtains PCIE card or type of module information, the signal that can detect by self-defined pin from PCIE card or module, or by out-of-band communication interface (I2C) the visit PCIE card of PCIE card or module or the Erasable Programmable Read Only Memory EPROM (EEPROM on the module, Electrically Erasable Programmable ROM) signal in obtains, or the System Management Bus (SMB by PCIE card or module, System Management Bus) signal among the EEPROM on interface accessing PCIE card or the module obtains, and does not influence the realization of the embodiment of the invention.Obviously, other obtain manners by other protocol interfaces obtain the realization that the PCIE card that is inserted on the PCIE interface or type of module information do not influence the embodiment of the invention yet.
Obtain the PCIE card or the type of module information that are inserted on the PCIE interface, can be to obtain a PCIE card or the type of module information on the PCIE interface, or PCIE card on a plurality of PCIE interfaces or type of module information, do not influence the realization of the embodiment of the invention.
Step 102: according to PCIE card or type of module information, the configuration information of change PCIE interface.
The configuration information of the logical circuit change PCIE interface of master control borad comprises: the logical circuit of master control borad sends PCIE card or type of module information to the master control borad chipset, the configuration information of change PCIE interface.
The master control borad chipset can be the south bridge or the north bridge chipset of master control borad.
After the configuration information of PCIE interface is modified to PCIE card or type of module information, the master control borad chipset then sends and PCIE card or the corresponding clock signal of type of module information to the PCIE interface, and the number of clock signal is identical with the interface number that PCIE card or module need.
Clock signal is used for each device of synchro system (central processing unit, storer, system bus etc.) work, and concrete form can be a pulse signal that sends every one equal period.
Also can at the overall channel number of PCIE card or module during, just change the configuration information of PCIE interface, then can make full use of the bandwidth of this PCIE interface, help improving data transmission efficiency smaller or equal to the physical channel number of PCIE interface.The overall channel number of PCIE card or module is the amassing of number of active lanes of interface number and each interface of PCIE calorie requirement.
The embodiment of the invention has been avoided needing to adopt the support of PCIE exchange chip to have the PCIE card or the module of at least two chips in the prior art, the method of a plurality of PCIE cards or the shared PCIE interface bandwidth of module, but obtain PCIE card or the interface number of module needs and the number of active lanes of each interface by master control borad, directly the PCIE interface adaptive ground of single fixed physical bandwidth is supported to have the PCIE card or the module of at least two chips, not only avoided the transmission delay that uses the PCIE exchange chip to bring, and can make full use of the bandwidth of PCIE interface, guarantee system performance, and easy to use.
Following examples two are the Application Example of embodiment one, and the PCIE card that has 2 X4 channel chip with the PCIE interface adaptive support with 1 X8 passage is that example is elaborated.The PCIE card that the following embodiment of the invention two and embodiment three mention also can be that other are inserted into the application module on the PCIE of the system interface, does not influence the realization of the embodiment of the invention.
Embodiment two, describe in detail referring to Fig. 2, Fig. 2 is the method flow synoptic diagram of present embodiment.
Step 201: system standby power supply electrifying, the PCIE card that has 2 chips is inserted on the PCIE interface of X8 passage, PCIE card transmission types information is given the master control borad logical circuit, and type information comprises the interface information of number of PCIE calorie requirement and the number of active lanes information of each interface.
Type information can be sent by the self-defined pin of PCIE card, also can be by the out-of-band communication interface of PCIE card or the type information signal among the EEPROM on the System Management Bus interface transmission PCIE card.
Self-defined pin can be the undefined pin of unknown neighbor on the PCIE card, as the Pin32 of SideA, Pin33.
The self-defining mode of pin can be the type information signal that pre-defines each signal representative.For example, the length of the signal on the self-defined pin is 3 bits, and promptly the type information of 000 expression PCIE card is the interface of 1 X8 passage, the interface of 2 X4 passages of 001 expression etc.Obviously, other pin definitions method does not influence the realization of the embodiment of the invention yet.
Step 202: the master control borad logical circuit obtains the type information of PCIE card, learns the interface of 2 X4 passages of this PCIE calorie requirement.
Step 203: the master control borad logical circuit is to master control borad chipset output type information.
When the length of the signal on self-defined pin was 3 bits, type information was signal such as 000,001.
The master control borad chipset can be the south bridge or the north bridge chipset of master control borad.
Step 204: system's primary power powers on.
Step 205: with the PCIE interface configuration information change on the master control borad chipset is the interface message of 2 X4 passages.
The same prior art of information change process repeats no more.
Step 206: the master control borad chipset sends corresponding signal and 2 tunnel definition clocks to the interface of 2 X4 passages.
Clock signal is used for each device of synchro system (central processing unit, storer, system bus etc.) work, and concrete form can be a pulse signal that sends every one equal period.
The PCIE interface then can support to have the PCIE card of 2 chips after receiving the signal and 2 tunnel definition clocks of interface correspondence of 2 X4 passages, realizes the proper communication of this PCIE card and master control borad.
Present embodiment two is an example with the PCIE card that the interface adaptive with 1 X8 passage becomes to support to have the chip of 2 X4 passages, obviously, the interface adaptive of 1 X8 passage is become to support to have the PCIE card of 4 X2 channel chip, or self-adaptation becomes to support to have the PCIE card of 8 X1 channel chip, or the interface adaptive of 1 X16 passage become to support to have the PCIE card of 2 X8 channel chip etc., do not influence the realization of the embodiment of the invention.
The embodiment of the invention is obtained the number of active lanes of interface number He each interface of PCIE calorie requirement by master control borad, directly with the PCIE interface adaptive of single fixed physical bandwidth be configured to support to have the PCIE card of at least two chips, avoided the transmission delay that uses the PCIE exchange chip to bring, and can make full use of the bandwidth of PCIE interface, guarantee system performance, easy to use.
Following examples three are the Application Example of embodiment one, with the PCIE interface of 2 X8 passages of system respectively the self-adaptation PCIE card that becomes to support to have the PCIE card of 1 X8 channel chip, 2 X4 channel chip be that example is elaborated.
Embodiment three, describe in detail referring to Fig. 3, Fig. 3 is the method flow synoptic diagram of present embodiment.
Step 301: system standby power supply electrifying, 2 PCIE cards are inserted on the PCIE interface A and PCIE interface B of X8 passage, PCIE card transmission types information is given the master control borad logical circuit, and type information comprises the interface information of number of PCIE calorie requirement and the number of active lanes information of each interface.
Step 302: the master control borad logical circuit obtains the type information of 2 PCIE cards, learns the PCIE interface of 1 the X8 passage of PCIE calorie requirement on the PCIE interface A, the PCIE interface of 2 the X4 passages of PCIE calorie requirement on the PCIE interface B.
Obviously, if the PCIE card on the PCIE interface A also needs the PCIE interface of 2 X4 passages, or during the PCIE interface of other numbers, do not influence the realization of the embodiment of the invention yet.
Step 303: the master control borad logical circuit is to master control borad chipset transmission types information.
Step 304: system's primary power powers on.
Step 305: it is the PCIE interface of 1 X8 passage that the PCIE interface configuration information change on the master control borad chipset is become PCIE interface A, and PCIE interface B is the information of the PCIE interface of 2 X4 passages.
Step 306: the master control borad chipset sends the signal and 1 tunnel definition clock of 1 corresponding X8 passage to PCIE interface A; Send the signal and 2 tunnel definition clocks of 2 corresponding X4 passages to PCIE interface B.
Clock signal is used for each device of synchro system (central processing unit, storer, system bus etc.) work, and concrete form can be a pulse signal that sends every one equal period.
The PCIE interface receives out the signal of PCIE interface A and PCIE interface B correspondence, and behind the definition clock of two interface correspondences, then can support 2 PCIE cards that have different number chips, realizes the proper communication of this PCIE card and master control borad.
Present embodiment three with the PCIE interface of 2 X8 passages of system respectively the self-adaptation PCIE card that becomes to support to have the PCIE card of 1 X8 channel chip, 2 X4 channel chip be example, obviously, the interface adaptive of the interface of the X8 passage more than 2 or 2 X16 passages is become to have the PCIE card of other number chips, do not influence the realization of the embodiment of the invention.
The embodiment of the invention is obtained the number of active lanes of interface number He each interface of PCIE calorie requirement by master control borad, directly the PCIE interface of two fixed physical bandwidth is configured to support to have adaptively the PCIE card of different core numbers respectively, avoided the transmission delay that uses the PCIE exchange chip to bring, and can make full use of the bandwidth of PCIE interface, guarantee system performance, easy to use.
The PCIE card that the above embodiment of the invention is mentioned also can be that other are inserted into the application module on the PCIE of the system interface, does not influence the realization of the embodiment of the invention.
Need to prove, for aforesaid each method embodiment, for simple description, so it all is expressed as a series of combination of actions, but those skilled in the art should know, the present invention is not subjected to the restriction of described sequence of movement, because according to the present invention, some step can adopt other orders or carry out simultaneously.Secondly, those skilled in the art also should know, the embodiment described in the instructions all belongs to preferred embodiment, and related action and module might not be that the present invention is necessary.
In the above-described embodiments, the description of each embodiment is all emphasized particularly on different fields, do not have the part that describes in detail among certain embodiment, can be referring to the associated description of other embodiment.
A kind of method of interface adaptive more than is provided, and the embodiment of the invention also provides a kind of device of interface adaptive.
A kind of device of interface adaptive, referring to Fig. 4, Fig. 4 is the structural representation of embodiment of the invention device, comprising:
Acquiring unit 41 is used to obtain the PCIE card or the type of module information that are inserted on the PCIE interface, and type information comprises the number of active lanes of interface number He each interface of PCIE card or module needs; The signal that can detect by self-defined pin from PCIE card or module, perhaps, obtain the PCIE card or the type of module information that are inserted on the PCIE interface by the out-of-band communication interface of PCIE card or module or the signal in the Erasable Programmable Read Only Memory EPROM on System Management Bus interface accessing PCIE card or the module.
Configuration change unit 42 is used for PCIE card or the type of module information obtained according to acquiring unit 41, changes the configuration information of described PCIE interface; Can also be during smaller or equal to the physical channel number of PCIE interface, to change the configuration information of described PCIE interface at the overall channel number of PCIE card or module; The overall channel number is the interface information of number of PCIE card or module needs and the amassing of number of active lanes of each interface.
Behind the PCIE card or type of module information that configuration change unit 42 obtains, can send PCIE card or type of module information, change to and the corresponding configuration information of type information by the configuration information of master control borad chipset again the PCIE interface to the master control borad chipset.
Each module of embodiment of the invention equipment can be integrated in one, and also can separate deployment.Above-mentioned module can be merged into a module, also can further split into a plurality of submodules.
A kind of system of interface adaptive, referring to Fig. 5, Fig. 5 is the structural representation of embodiment of the invention system, comprising:
PCIE card or module 51 are used for providing type information to master control borad 52, and type information comprises the interface information of number of PCIE card or module needs and the number of active lanes information of each interface.
Master control borad 52 is used to obtain the PCIE card that is inserted on the PCIE interface or the type information of module 51, and according to PCIE card or type of module information, changes the configuration information of described PCIE interface.
Master control borad 52 is also to PCIE card or module 51 tranmitting data register signals, and the number of clock signal is identical with the interface number that PCIE card or module 51 need.
The signal that can detect by self-defined pin from PCIE card or module, perhaps, obtain the PCIE card or the type of module information that are inserted on the PCIE interface by the out-of-band communication interface of PCIE card or module or the signal in the Erasable Programmable Read Only Memory EPROM on the System Management Bus interface accessing PCIE card.
Master control borad 52 can be divided into logical circuit and chipset, logical circuit obtains the PCIE card that is inserted on the PCIE interface or the type information of module 51, and, change to and the corresponding configuration information of type information by the configuration information of chipset with the PCIE interface to the type information of chipset output PCIE card or module 51.Chipset can be the south bridge or the north bridge chipset of master control borad, does not influence the realization of the embodiment of the invention.
Embodiment of the invention device and system obtain PCIE card or the interface number of module needs and the number of active lanes of each interface by master control borad, can be directly the PCIE interface of the fixed physical bandwidth of system be configured to support to have the PCIE card or the module of at least two chips respectively adaptively, avoided the transmission delay that uses the PCIE exchange chip to bring, and can make full use of the bandwidth of PCIE interface, guarantee system performance, easy to use.
One of ordinary skill in the art will appreciate that, realize all or part of flow process in the foregoing description method, be to instruct relevant hardware to finish by computer program, program can be stored in the computer read/write memory medium, this program can comprise the flow process as the embodiment of above-mentioned each side method when carrying out.Wherein, storage medium can be magnetic disc, CD, read-only storage memory body (Read-Only Memory, ROM) or at random store memory body (Random Access Memory, RAM) etc.
More than the method for a kind of interface adaptive that the embodiment of the invention provided and device thereof, system are described in detail, used specific case herein principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.