CN114116563A - High-speed synchronous serial port module based on PCIE bus - Google Patents
High-speed synchronous serial port module based on PCIE bus Download PDFInfo
- Publication number
- CN114116563A CN114116563A CN202111240916.0A CN202111240916A CN114116563A CN 114116563 A CN114116563 A CN 114116563A CN 202111240916 A CN202111240916 A CN 202111240916A CN 114116563 A CN114116563 A CN 114116563A
- Authority
- CN
- China
- Prior art keywords
- circuit
- pcie
- serial port
- synchronous serial
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Information Transfer Systems (AREA)
- Bus Control (AREA)
Abstract
The invention discloses a high-speed synchronous serial port module based on a PCIE bus, which is characterized by comprising a PCIE golden finger interface circuit, a power supply circuit, a PCIE bridge piece conversion circuit, a double-port RAM data storage circuit, an FPGA protocol processing control circuit, a signal isolation circuit, a high-speed synchronous serial port receiving and transmitting circuit and a synchronous serial port connector circuit. The invention has the advantages and beneficial effects that: the PCIE bus high-speed serial bus is introduced through the PCIE golden finger, a high-speed synchronous serial bus protocol is realized through protocol conversion, communication with external equipment is realized through a high-speed transceiver, the high-speed synchronous serial port converted through the PCIE bus is realized, and the device has the characteristics of high integration level, strong operability, convenience in carrying, stability, high efficiency and the like.
Description
Technical Field
The invention relates to the field of industrial control and the field of military communication, in particular to the field of industrial control and the field of military communication.
Background
PCI-express (peripheral component interconnect express) is a high-speed serial computer expansion bus standard, originally named "3 GIO", which was proposed by Intel in 2001, to replace the old PCI, PCI-X and AGP bus standards.
PCIE belongs to high-speed serial point-to-point double-channel high-bandwidth transmission, connected equipment distributes independent channel bandwidth and does not share bus bandwidth, and mainly supports functions of active power management, error reporting, end-to-end reliable transmission, hot plug, quality of service (QOS) and the like. PCIE has the main advantage of high data transmission rate and has considerable development potential. PCI Express also has a variety of specifications, from PCI Express x1 to PCI Express x32, that meet the demands of low-speed devices and high-speed devices that will emerge in the future for a certain time. The PCI-Express interface is a PCIE3.0 interface, has a bit rate of 8Gbps, which is about twice the bandwidth of the previous generation product, and includes a series of important new functions, such as transmitter and receiver equalization, PLL improvement, and clock data recovery, to improve data transmission and data protection performance.
Serial communication can be classified into two types, synchronous communication and asynchronous communication. Synchronous communication means that the frequency and phase of clock signals of a transmitting end and a receiving end are always kept consistent (synchronous) under an agreed communication rate, so that the two communication parties have a completely consistent timing relationship when transmitting and receiving data. Serial communication refers to the serial transfer of data between a host computer and peripheral devices, and between a host system and a host system. With serial communication, each character sent and received is actually transmitted one bit at a time, with each bit being either a 1 or a 0.
Synchronous serial communication combines a plurality of characters into a message group, or message frame, and the beginning of each frame is indicated by a synchronous character. Since the same clock is used for both transmission and reception, a clock signal is transmitted at the same time as the data is transmitted so that the receiver can determine each information bit using the clock signal.
Synchronous serial port communication requires that a continuous character bit stream is always maintained on a transmission line, and if a computer does not transmit data, the line is filled with special 'idle' characters or synchronous characters.
The number of bits of the information transmitted by the synchronous serial port communication is almost unlimited, and generally, the data transmitted by one-time communication has dozens of to thousands of bytes, so that the communication efficiency is high. But it requires maintaining an accurate synchronous clock in the communication, so its transmitter and receiver are more complex and costly, and are generally used in the occasions where the transmission rate requirement is higher.
At present, synchronous serial ports are applied to many occasions, such as military aircrafts, aviation guidance, missile and rocket transportation and the like, so that ground test equipment also needs the synchronous serial ports. At present, PCIE interfaces of a computer and an industrial personal computer become the most basic peripheral interfaces, and the PCIE interfaces realize the communication and the test of an expanded synchronous serial port and become a good method.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a high-speed synchronous serial port module based on a PCIE bus.
The technical scheme of the invention is as follows:
a high-speed synchronous serial port module based on a PCIE bus is characterized by comprising a PCIE golden finger interface circuit, a power supply circuit, a PCIE bridge piece conversion circuit, a double-port RAM data storage circuit, an FPGA protocol processing control circuit, a signal isolation circuit, a high-speed synchronous serial port transceiving circuit and a synchronous serial port connector circuit, wherein the FPGA protocol processing control circuit, the double-port RAM data storage circuit, the PCIE bridge piece conversion circuit and the PCIE golden finger interface circuit are sequentially connected; the FPGA protocol processing control circuit is connected with the signal isolation circuit, and the signal isolation circuit is connected with the synchronous serial port connector circuit through a high-speed synchronous serial port transceiving circuit; the PCIE golden finger interface circuit adopts a standard PCIE x1 golden finger board type, and introduces a 12V power supply, a 5V power supply, a reset signal RST, a same source difference differential PCIE reference clock and a PCIE bus of a system from a golden finger connection position; the function of the PCIE bridge chip conversion circuit is used for converting a PCIE serial BUS into a LOCAL BUS parallel BUS and finishing PCIE enumeration and mapping; the double-port RAM data storage circuit is used for storing communication data, and is mounted with two chips of 70V28 of IDT company, wherein one chip is used as a sending data cache, and the other chip is used as a receiving data cache; the PCIE bridge chip switching circuit writes required sending data into a sending data cache through a LOCAL BUS and reads received data from a receiving data cache; the FPGA protocol processing control circuit is just opposite to the FPGA protocol processing control circuit, and generates a LOCAL BUS through decoding to read and send a data cache and write an interface data cache, so that data exchange at two sides is realized.
The invention has the advantages and beneficial effects that: the PCIE bus high-speed serial bus is introduced through the PCIE golden finger, a high-speed synchronous serial bus protocol is realized through protocol conversion, communication with external equipment is realized through a high-speed transceiver, the high-speed synchronous serial port converted through the PCIE bus is realized, and the PCIE bus high-speed synchronous serial bus interface has the characteristics of high integration level, strong operability, convenience in carrying, stability, high efficiency and the like.
Drawings
Fig. 1 is a connection schematic block diagram of a PCIE bus-based high-speed synchronous serial port module provided in the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, and the two components can be communicated with each other. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art through specific situations.
As shown in fig. 1, a PCIE bus-based high-speed synchronous serial port module includes a PCIE gold finger interface circuit, a power supply circuit, a PCIE bridge piece conversion circuit, a dual-port RAM data storage circuit, an FPGA protocol processing control circuit, a signal isolation circuit, a high-speed synchronous serial port transceiver circuit, and a synchronous serial port connector circuit, where the FPGA protocol processing control circuit, the dual-port RAM data storage circuit, the PCIE bridge piece conversion circuit, and the PCIE gold finger interface circuit are connected in sequence; the FPGA protocol processing control circuit is connected with the signal isolation circuit, and the signal isolation circuit is connected with the synchronous serial port connector circuit through a high-speed synchronous serial port transceiving circuit; the PCIE golden finger interface circuit adopts a standard PCIE x1 golden finger board type, and introduces a 12V power supply, a 5V power supply, a reset signal RST, a same source difference differential PCIE reference clock and a PCIE bus of a system from a golden finger connection position; the function of the PCIE bridge chip conversion circuit is used for converting a PCIE serial BUS into a LOCAL BUS parallel BUS and finishing PCIE enumeration and mapping; the double-port RAM data storage circuit is used for storing communication data, and is mounted with two chips of 70V28 of IDT company, wherein one chip is used as a sending data cache, and the other chip is used as a receiving data cache; the PCIE bridge chip switching circuit writes required sending data into a sending data cache through a LOCAL BUS and reads received data from a receiving data cache; the FPGA protocol processing control circuit is just opposite to the FPGA protocol processing control circuit, and generates a LOCAL BUS through decoding to read and send a data cache and write an interface data cache, so that data exchange at two sides is realized.
The power supply circuit is a circuit for providing DC power conversion for the device, adopts an LTM4644 DC conversion module of ADI company to realize the conversion of a 12V main power supply, and provides 3.3V, 2.5V, 1.8V and 1.2V secondary power supplies for a rear-stage circuit.
The function of the PCIE bridge chip conversion circuit is used for converting a PCIE serial BUS into a LOCAL BUS parallel BUS and completing PCIE enumeration and mapping, a PEX8311 chip of PLX company is adopted, and when equipment is powered on, configuration information is read from an EEPROM through an SPI interface, so that an enumeration process is completed. And then, converting the PCIE BUS into a LOCAL BUS BUS, and reading and writing the rear-stage storage circuit.
The FPGA protocol processing control circuit is used for communication data exchange, protocol conversion and data and clock synchronization; the method comprises the steps of processing protocol data by using an EP3C5144I7 FPGA of ALTERA company, specifically, packaging data to be transmitted when the data are transmitted, generating a transmitting synchronous clock TXD _ CLK by using a PLL (phase locked loop), and sequentially transmitting the TXD according to a serial port protocol on the rising edge of the synchronous clock TXD _ CLK. When receiving data, under the excitation of an external input synchronous clock RXD _ CLK, the receiving RXD data is latched along the rising edge of the clock in sequence.
The signal isolation circuit is used for isolating the high-speed synchronous serial port transceiver circuit from each digital circuit at the front stage, converting a 5V power supply into a 5V isolation power supply through a Jinshengyang B0505 isolation power supply, supplying power to an isolation chip ISO7240 of the TI and a rear-stage high-speed synchronous serial port transceiver circuit, supplying power to the digital test by adopting 3.3V, and realizing the isolation of the transceiver circuit and the clock from external electricity through the device.
The high-speed synchronous serial port transceiving circuit is used for receiving and sending data and a clock, converting and transmitting a single-end signal and a differential signal, converting RXD and TXD into a standard RS422 differential signal for transmission by adopting a MAX490 chip of a Mei Xin company, and converting RXD _ CLK and TXD _ CLK into a standard RS422 differential signal for transmission by adopting a MAX490 chip of the Mei Xin company.
The synchronous serial port connector circuit is used for connecting the module with external equipment, four groups of differential signals of RXD, TXD, RXD _ CLK and TXD _ CLK and an isolation power supply GND are connected with the external equipment by adopting a standard DB9 interface, and data communication is realized.
The present invention has been described in detail with reference to the examples, but the description is only for the preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (7)
1. A high-speed synchronous serial port module based on a PCIE bus is characterized by comprising a PCIE golden finger interface circuit, a power supply circuit, a PCIE bridge piece conversion circuit, a double-port RAM data storage circuit, an FPGA protocol processing control circuit, a signal isolation circuit, a high-speed synchronous serial port receiving and transmitting circuit and a synchronous serial port connector circuit; the FPGA protocol processing control circuit, the double-port RAM data storage circuit, the PCIE bridge chip conversion circuit and the PCIE golden finger interface circuit are sequentially connected; the FPGA protocol processing control circuit is connected with the signal isolation circuit, and the signal isolation circuit is connected with the synchronous serial port connector circuit through a high-speed synchronous serial port transceiving circuit; the PCIE golden finger interface circuit adopts a standard PCIE x1 golden finger board type, and introduces a 12V power supply, a 5V power supply, a reset signal RST, a same source difference differential PCIE reference clock and a PCIE bus of a system from a golden finger connection position; the function of the PCIE bridge chip conversion circuit is used for converting a PCIE serial BUS into a LOCAL BUS parallel BUS and finishing PCIE enumeration and mapping; the double-port RAM data storage circuit is used for storing communication data, and is mounted with two chips of 70V28 of IDT company, wherein one chip is used as a sending data cache, and the other chip is used as a receiving data cache; the PCIE bridge chip switching circuit writes required sending data into a sending data cache through a LOCAL BUS and reads received data from a receiving data cache; the FPGA protocol processing control circuit is just opposite to the FPGA protocol processing control circuit, and generates a LOCAL BUS through decoding to read and send a data cache and write an interface data cache, so that data exchange at two sides is realized.
2. The PCIE bus-based high-speed synchronous serial port module of claim 1, wherein the power supply circuit is a circuit that provides DC power conversion of the present apparatus, and the DC conversion module is used to implement conversion of a 12V main power supply and provide secondary power supplies of 3.3V, 2.5V, 1.8V, and 1.2V to a subsequent circuit.
3. The PCIE BUS-based high-speed synchronous serial port module according to claim 1, wherein the PCIE bridge chip converting circuit is configured to convert a PCIE serial BUS into a LOCAL BUS parallel BUS and complete PCIE enumeration and mapping, and when the device is powered on, the device reads configuration information from an EEPROM through an SPI interface, completes an enumeration process, and then converts the PCIE BUS into a LOCAL BUS, and reads and writes a rear-stage storage circuit.
4. The PCIE bus-based high speed synchronous serial port module of claim 1, wherein the FPGA protocol processing control circuit is configured to exchange communication data, convert protocols, and synchronize data and clocks; the method comprises the steps of realizing protocol data processing by adopting an EP3C5144I7 FPGA, specifically, packing data to be transmitted when the data are transmitted, generating a transmitting synchronous clock TXD _ CLK by a PLL (phase locked loop), sequentially transmitting the TXD according to a serial port protocol by the data at the rising edge of the synchronous clock TXD _ CLK, and latching and receiving the RXD data along the rising edge of the clock in sequence under the excitation of an externally input synchronous clock RXD _ CLK when the data are received.
5. The PCIE bus-based high-speed synchronous serial port module according to claim 1, wherein the signal isolation circuit is configured to isolate the high-speed synchronous serial port transceiver circuit from each digital circuit at a preceding stage, convert a 5V power supply into a 5V isolation power supply through the isolation power supply, and supply power to the isolation chip ISO7240 and the high-speed synchronous serial port transceiver circuit at a subsequent stage, and the digital measurement uses 3.3V power supply, and the transceiver and clock thereof are electrically isolated from the outside through the apparatus.
6. The PCIE bus-based high-speed synchronous serial port module according to claim 1, wherein the high-speed synchronous serial port transceiver circuit is configured to receive and transmit data and a clock, convert a single-ended signal and a differential signal for transmission, convert RXD and TXD into a standard RS422 differential signal for transmission by using one MAX490 chip, and convert RXD _ CLK and TXD _ CLK into a standard RS422 differential signal for transmission by using one MAX490 chip.
7. The PCIE bus-based high-speed synchronous serial port module according to claim 1, wherein the synchronous serial port connector circuit is configured to connect the module with an external device, and a standard DB9 interface is adopted to connect four groups of differential signals RXD, TXD, RXD _ CLK, and TXD _ CLK and an isolation power GND with the external device, so as to implement data communication.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111240916.0A CN114116563B (en) | 2021-10-25 | 2021-10-25 | High-speed synchronous serial port module based on PCIE bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111240916.0A CN114116563B (en) | 2021-10-25 | 2021-10-25 | High-speed synchronous serial port module based on PCIE bus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114116563A true CN114116563A (en) | 2022-03-01 |
| CN114116563B CN114116563B (en) | 2023-08-29 |
Family
ID=80377323
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111240916.0A Active CN114116563B (en) | 2021-10-25 | 2021-10-25 | High-speed synchronous serial port module based on PCIE bus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114116563B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115442178A (en) * | 2022-08-31 | 2022-12-06 | 广东美的智能科技有限公司 | Multi-axis servo bus control circuit and multi-axis servo system |
| CN116841932A (en) * | 2022-11-04 | 2023-10-03 | 成都立思方信息技术有限公司 | Flexibly-connectable portable high-speed data access equipment and working method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN206209088U (en) * | 2016-12-02 | 2017-05-31 | 广东电网有限责任公司汕头供电局 | A kind of zinc oxide arrester tester calibrating installation |
| CN109522251A (en) * | 2018-09-28 | 2019-03-26 | 天津市英贝特航天科技有限公司 | A kind of high-speed synchronous serial port board and its working method based on PXIe bus |
| US20200004718A1 (en) * | 2018-07-02 | 2020-01-02 | Venturi, Inc. | Usb to synchronous serial interface with external clock signal |
| US20210117298A1 (en) * | 2013-02-21 | 2021-04-22 | Advantest Corporation | Use of host bus adapter to provide protocol flexibility in automated test equipment |
-
2021
- 2021-10-25 CN CN202111240916.0A patent/CN114116563B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20210117298A1 (en) * | 2013-02-21 | 2021-04-22 | Advantest Corporation | Use of host bus adapter to provide protocol flexibility in automated test equipment |
| CN206209088U (en) * | 2016-12-02 | 2017-05-31 | 广东电网有限责任公司汕头供电局 | A kind of zinc oxide arrester tester calibrating installation |
| US20200004718A1 (en) * | 2018-07-02 | 2020-01-02 | Venturi, Inc. | Usb to synchronous serial interface with external clock signal |
| CN109522251A (en) * | 2018-09-28 | 2019-03-26 | 天津市英贝特航天科技有限公司 | A kind of high-speed synchronous serial port board and its working method based on PXIe bus |
Non-Patent Citations (2)
| Title |
|---|
| 刘京威;: "煤矿井下多功能协议转换模块设计", 煤矿安全, no. 11 * |
| 陈卫涛;史忠科;: "航空总线接口通信系统的设计与实现", 计算机工程, no. 06 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115442178A (en) * | 2022-08-31 | 2022-12-06 | 广东美的智能科技有限公司 | Multi-axis servo bus control circuit and multi-axis servo system |
| CN115442178B (en) * | 2022-08-31 | 2023-12-15 | 广东美的智能科技有限公司 | Multi-axis servo bus control circuit and multi-axis servo system |
| CN116841932A (en) * | 2022-11-04 | 2023-10-03 | 成都立思方信息技术有限公司 | Flexibly-connectable portable high-speed data access equipment and working method thereof |
| CN116841932B (en) * | 2022-11-04 | 2024-03-26 | 成都立思方信息技术有限公司 | Flexibly-connectable portable high-speed data access equipment and working method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114116563B (en) | 2023-08-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114116563B (en) | High-speed synchronous serial port module based on PCIE bus | |
| US20110206381A1 (en) | Optical serializing/deserializing apparatus and method and method of manufacturing same | |
| CN104639410A (en) | Design method of field bus optical fiber communication interface | |
| CN103346977A (en) | Dynamic allocation method for data resources | |
| CN105281783A (en) | Signal decoding unit based on FPGA (Field Programmable Gate Array) and DSP (Digital Signal Processor) and realization method for signal decoding unit based on FPGA and DSP | |
| CN104991880B (en) | A kind of FC AE ASM Communication Cards based on PCI E interfaces | |
| CN111352887B (en) | PCI bus-to-configurable frame length serial bus adaptation and transmission method | |
| CN203643598U (en) | Radar data recording device | |
| CN201336661Y (en) | Optical module interface conversion device | |
| CN114442514B (en) | USB3.0/3.1 control system based on FPGA | |
| CN109491940A (en) | Conversion circuit and conversion method for TLK2711 transmission interface and USB3.0 transmission interface | |
| CN101561791B (en) | Synchronous serial interface device with expandable frame width | |
| CN219227609U (en) | JESD204B data transmission system based on optical fiber medium | |
| CN218772141U (en) | Dual-processor circuit and control mainboard of distributed control system | |
| CN209312015U (en) | Conversion circuit of TLK2711 transmission interface and USB3.0 transmission interface | |
| CN208314763U (en) | A kind of Retimer board for being transmitted outside PCIe signal chassis | |
| TWM639691U (en) | Interface conversion device | |
| CN202617157U (en) | PCI express (PCIE) switched circuit | |
| CN203761399U (en) | Optical communication equipment of single-fiber bi-directional symmetrical rate and system | |
| CN111258946A (en) | Communication method of GTX and TLK2711 series chips | |
| CN210804154U (en) | Dual-channel large-bandwidth waveform generation system | |
| KR100321981B1 (en) | Apparatus for recompensing delay of clock | |
| CN110912611A (en) | SFP transmission system based on distributed synchronous time service technology | |
| CN221056929U (en) | Communication system between double FPGAs | |
| CN110661687B (en) | Full-communication double-bus exchange platform |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |