CN221056929U - Communication system between double FPGAs - Google Patents

Abstract

The utility model relates to a communication system between double FPGAs, which comprises: the first FPGA module comprises a first phase-locked loop, a first data processing unit and a first communication interface unit which are sequentially connected; the second FPGA module comprises a second phase-locked loop, a second data processing unit and a second communication interface unit, wherein the second communication interface unit is connected with the first communication interface unit, the second phase-locked loop is connected with the second communication interface unit, and the second data processing unit is respectively connected with the second communication interface unit and the second phase-locked loop. The communication system between the double FPGAs can complete data transmission and reception by only directly connecting four groups of differential pins with two FPGAs at least without additional hardware, thereby realizing full duplex communication between the double FPGAs.

Description

Communication system between double FPGAs

Technical Field

The utility model relates to the field of communication, in particular to a communication system between double FPGAs.

Background

In power electronics field designs, data transfer involving multiple chips is often required. The data transmission method commonly used between two FPGA chips comprises the following two methods: serial communication is a common way to transfer data between two FPGA chips. It involves transmitting one bit of data at a time over a single data line. The serial communication mode has a slow communication rate, and the transmission rate is generally below 100 Mbps. Parallel communication designs transmit multiple bits of data simultaneously over multiple data lines, which can provide faster data transfer rates than serial communication, but require more IO interfaces and FPGA vendors typically do not provide the relevant communication protocol IP cores or require pay-for-use, with poor portability.

Disclosure of utility model

The utility model aims to solve the technical problems of low serial communication transmission rate and more IO interfaces occupied by parallel communication by providing a communication system between double FPGAs.

In order to solve the technical problems, the utility model provides a communication system between double FPGAs, comprising: the first FPGA module comprises a first phase-locked loop, a first data processing unit and a first communication interface unit which are sequentially connected; the second FPGA module comprises a second phase-locked loop, a second data processing unit and a second communication interface unit, wherein the second communication interface unit is connected with the first communication interface unit, the second phase-locked loop is connected with the second communication interface unit, and the second data processing unit is respectively connected with the second communication interface unit and the second phase-locked loop; the first communication interface unit and the second communication interface unit respectively comprise a TX-data differential interface, a TX-clock differential interface, an RX-data differential interface and an RX-clock differential interface, wherein the TX-data differential interface of the first communication interface unit is connected with the RX-data differential interface of the second communication interface unit, and the TX-clock differential interface of the first communication interface unit is connected with the RX-clock differential interface of the second communication interface unit.

Optionally, the first data processing unit and the second data processing unit each comprise ODDR units and IDDR units.

Optionally, the first phase-locked loop is configured to receive a first clock signal, and perform frequency conversion on the first clock signal to obtain a second clock signal, where the frequency of the second clock signal is N times that of the first clock signal, and N is a positive integer greater than 1; the first data processing unit is used for sending one bit data on each rising edge and each falling edge of the second clock signal through a ODDR unit of the first data processing unit.

Optionally, the first data processing unit is further configured to: the first clock signal is subjected to phase transformation to obtain a third clock signal, the third clock signal has the same frequency as the first clock signal but a 90-degree phase difference, and first bit data are sent on the rising edge of the third clock signal; and transmitting the third clock signal.

Optionally, the second phase-locked loop is configured to receive the third clock signal, and perform frequency conversion on the third clock signal to obtain a fourth clock signal, where the frequency of the fourth clock signal is N times that of the third clock signal, and N is a positive integer greater than 1; the second data processing unit is used for respectively acquiring one bit data on each rising edge and each falling edge of the fourth clock signal through the IDDR unit of the second data processing unit.

Optionally, the second data processing unit is further configured to obtain the first bit data on a rising edge of the third clock signal.

Optionally, the first FPGA module further includes a first buffer unit connected to the first data processing unit, and the second FPGA module further includes a second buffer unit connected to the second data processing unit.

Optionally, the system further comprises: and the clock module is connected with the first phase-locked loop and is used for providing the first clock signal for the first phase-locked loop.

Optionally, wherein N is equal to 4.

Optionally, the first data processing unit and the second data processing unit transmit data based on LVDS communication protocol.

The beneficial effects of the utility model are as follows:

According to the communication system between the double FPGAs, the first phase-locked loop, the first data processing unit, the second phase-locked loop and the second data processing unit are matched with each other, at least only four groups of differential pins are required to be directly connected with two FPGAs, and data transmission and reception can be completed without additional hardware, so that full duplex communication between the double FPGAs is realized; the communication system of the utility model maximally supports the transmission rate of 1Gbps by carrying out frequency conversion on clock signals through the first phase-locked loop and the second phase-locked loop and respectively updating one bit data on each rising edge and each falling edge of the converted clock signals through the first data processing unit and the second data processing unit; the communication system between the double FPGAs does not depend on a specific FPGA chip and IP verification, and has good portability.

Drawings

In order to make the above objects, features and advantages of the present utility model more comprehensible, embodiments accompanied with figures are described in detail below, wherein:

FIG. 1 is a system block diagram of a communication system between dual FPGAs in accordance with an embodiment of the present utility model;

Fig. 2 is a schematic diagram of a connection of a first communication interface unit with a second communication interface unit.

Fig. 3 is a schematic diagram of a first FPGA module transmit signal according to an embodiment of the present utility model.

Fig. 4 is a signal timing diagram of signals in the first FPGA module of fig. 3.

FIG. 5 is a diagram of a second FPGA module acquisition signal according to an embodiment of the present utility model.

Fig. 6 is a signal timing diagram of the signals in the second FPGA module of fig. 5.

Detailed Description

In order to make the above objects, features and advantages of the present utility model more comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present utility model, but the present utility model may be practiced in other ways than as described herein, and therefore the present utility model is not limited to the specific embodiments disclosed below.

FIG. 1 is a system block diagram of a communication system between dual FPGAs in accordance with an embodiment of the present utility model. As shown in fig. 1, the dual FPGA communication system 100 includes a first FPGA module 1 and a second FPGA module 2. The first FPGA module 11 includes a first phase-locked loop 11, a first data processing unit 12, and a first communication interface unit 13, which are sequentially connected. The second FPGA module 2 comprises a second phase-locked loop 21, a second data processing unit 22 and a second communication interface unit 23. The second communication interface unit 23 is connected to the first communication interface unit 13, the second phase locked loop 21 is connected to the second communication interface unit 23, and the second data processing unit 22 is connected to the second communication interface unit 23 and the second phase locked loop 21, respectively.

Fig. 2 is a schematic diagram of a connection of a first communication interface unit with a second communication interface unit. As shown in fig. 2. The first communication interface unit 13 and the second communication interface unit 23 include tx_data differential interfaces (tx_data_p and tx_data_n), tx_clock differential interfaces (tx_clk_x1_p and tx_clk_x1_n), rx_data differential interfaces (rx_data_p and rx_data_n), and rx_clock differential interfaces (rx_clk_x1_p and rx_clk_x1_n), respectively.

The tx_data differential interfaces (tx_data_p and tx_data_n) of the first communication interface unit 13 are connected to the rx_data differential interfaces (rx_data_p and rx_data_n) of the second communication interface unit 23, and the tx_clock differential interfaces (tx_clk_x1_p and tx_clk_x1_n) of the first communication interface unit 13 are connected to the rx_clock differential interfaces (rx_clk_x1_p and rx_clk_x1_n) of the second communication interface unit 23.

The tx_data differential interfaces (tx_data_p and tx_data_n) of the second communication interface unit 23 are connected to the rx_data differential interfaces (rx_data_p and rx_data_n) of the first communication interface unit 13, and the tx_clock differential interfaces (tx_clk_x1_p and tx_clk_x1_n) of the second communication interface unit 23 are connected to the rx_clock differential interfaces (rx_clk_x1_p and rx_clk_x1_n) of the first communication interface unit 13. It can be known that the first FPGA module 1 only needs to occupy 8 IO pins, and the second FPGA module 2 only needs to occupy 8 IO pins, so that full duplex communication between the first FPGA module 1 and the second FPGA module 2 can be achieved.

Optionally, as shown in fig. 1, the first data processing unit 12 includes ODDR units 121 and IDDR units 122. The second data processing unit 22 includes ODDR units 221 and IDDR unit 222.ODDR (Output Double Data Rate, double data rate output register) units can convert single-edge data signals to double-edge (rising, falling edge of clock) data signals, commonly used in serial-parallel data designs. IDDR (Input Double Date Rate, double data rate input register) units can convert a two-edge (rising edge, falling edge of clock) data signal to a single-edge data signal, commonly used in serial-parallel data designs.

Optionally, the first FPGA module 1 further comprises a first buffer unit connected to the first data processing unit 12, and the second FPGA module 2 further comprises a second buffer unit connected to the second data processing unit 22. The first buffer unit and the second buffer unit are used for storing the transmitted or received data.

Optionally, the system further comprises a clock module, which is connected to the first phase locked loop 11 and is configured to provide a first clock signal to the first phase locked loop 11.

Fig. 3 is a schematic diagram of a first FPGA module transmit signal according to an embodiment of the present utility model. As shown in fig. 3, the first phase-locked loop 11 is configured to receive a first clock signal CLK, and perform frequency conversion on the first clock signal CLK to obtain a second clock signal, where the frequency of the second clock signal is N times that of the first clock signal, and N is a positive integer greater than 1. In this embodiment, N is equal to 4, and the second clock signal is CLKx4. Optionally, the first phase-locked loop 11 is further configured to output the same frequency clock signal CLKx1, wherein there is no phase difference between CLK, CLKx1 and CLKx4. Where the first clock signal CLK may be from a clock unit external to the communication system, the first clock signal CLK may also be from a clock unit internal to the communication system when the communication system 100 further comprises a clock unit. The input data LVDS_IN [7:0] is the data which the first FPGA module needs to send to the second FPGA module. The input data LVDS_IN [7:0] can be from a storage unit outside the system, and when the first FPGA module 1 further comprises a buffer unit, the input data LVDS_IN [7:0] can also be from the buffer unit of the first FPGA module 1.

The first data processing unit 12 is configured to transmit one bit of data on each rising and falling edge of the second clock signal CLKx4 through its own ODDR unit 121, respectively.

Optionally, the first data processing unit 12 is further configured to perform phase transformation on the first clock signal CLK to obtain a third clock signal tx_clk_x1. The third clock signal tx_clk_x1 is the same frequency as the first clock signal CLK, but 90 ° out of phase.

Fig. 4 is a signal timing diagram of signals in the first FPGA module of fig. 3. As shown in fig. 4, the frequency of the second clock signal CLKx4 is four times that of the first clock signal CLK. The third clock signal tx_clk_x1 is the same frequency as the first clock signal CLK, but 90 ° out of phase. The first data processing unit 12 transmits the first bit data (bit 0) on the rising edge of the third clock signal tx_clk_x1, and then transmits one bit data on each of the rising and falling edges of the second clock signal CLKx4, respectively, to realize transmission of 8 bit data (bit 0 to bit 7) within 1 CLKx1 time.

As shown in fig. 3, the first DATA processing unit 12 outputs a DATA output signal tx_data and a third clock signal tx_clk_x1 to the first communication interface unit 13. Specifically, the DATA output signal tx_data is output to the tx_data differential interface of the first communication interface unit 13, and the third clock signal tx_clk_x1 is output to the tx_clock differential interface of the first communication interface unit 13.

FIG. 5 is a diagram of a second FPGA module acquisition signal according to an embodiment of the present utility model. As shown in fig. 5, the second phase locked loop 21 acquires a clock signal rx_clk_x1 from the rx_clock differential interface of the second communication interface unit 23, wherein the clock signal rx_clk_x1 and the third clock signal tx_clk_x1 are the same signal, except that the naming is different in the first FPGA module and the second FPGA module, and the clock signal rx_clk_x1 is hereinafter also referred to as the third clock signal. The second phase-locked loop 21 is configured to perform frequency conversion on the third clock signal rx_clk_x1 to obtain a fourth clock signal, where the frequency of the fourth clock signal is N times that of the third clock signal, and N is a positive integer greater than 1. In this embodiment, N is equal to 4, and the fourth clock signal is r_clkx4. Optionally, the second phase-locked loop 21 is further configured to output the same frequency clock signal r_clkx1, wherein there is no phase difference between rx_clkx1, r_clkx1 and r_clkx4. The second DATA processing unit 22 is configured to obtain a DATA input signal rx_data from the rx_data differential interface of the second communication interface unit 23, where the DATA input signal rx_data and the DATA output signal tx_data in fig. 3 are the same signal. The second data processing unit 22 acquires one bit data at each rising and falling edge of the fourth clock signal r_clkx4 through its own IDDR unit 222, respectively.

Fig. 6 is a signal timing diagram of the signals in the second FPGA module of fig. 5. As shown in fig. 6, the fourth clock signal r_clkx4 has a frequency four times that of the third clock signal r_clkx1. The second data processing unit 22 transmits the first bit data (bit 0) on the rising edge of the third clock signal rx_clk_x1, and then transmits one bit data on each of the rising and falling edges of the fourth clock signal r_clkx4, respectively, to realize transmission of 8 bit data (bit 0 to bit 7) within 1 rx_clkx1 time.

Optionally, the first data processing unit and the second data processing unit transmit data based on an LVDS (Low Voltage DIFFERENTIAL SIGNALING) communication protocol. The core of the LVDS technology is that data is transmitted in a high-speed differential mode by adopting an extremely low voltage swing, so that point-to-point or point-to-multipoint connection can be realized.

According to the communication system between the double FPGAs, the first phase-locked loop, the first data processing unit, the second phase-locked loop and the second data processing unit are matched with each other, at least only four groups of differential pins are required to be directly connected with two FPGAs, and data transmission and reception can be completed without additional hardware, so that full duplex communication between the double FPGAs is realized; the communication method of the utility model maximally supports the transmission rate of 1Gbps by carrying out frequency conversion on clock signals through the first phase-locked loop and the second phase-locked loop and respectively updating one bit data on each rising edge and each falling edge of the converted clock signals through the first data processing unit and the second data processing unit; the communication system between the double FPGAs does not depend on a specific FPGA chip and IP verification, and has good portability.

As used in the specification and in the claims, the terms "a," "an," "the," and/or "the" are not specific to a singular, but may include a plurality, unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that the steps and elements are explicitly identified, and they do not constitute an exclusive list, as other steps or elements may be included in a method or apparatus.

In addition, the terms "first", "second", etc. are used to define the components, and are only for convenience of distinguishing the corresponding components, and the terms have no special meaning unless otherwise stated, and therefore should not be construed as limiting the scope of the present application. Furthermore, although terms used in the present application are selected from publicly known and commonly used terms, some terms mentioned in the present specification may be selected by the applicant at his or her discretion, the detailed meanings of which are described in relevant parts of the description herein. Furthermore, it is required that the present application is understood, not simply by the actual terms used but by the meaning of each term lying within.

Hereinafter, embodiments of the present utility model will be described based on the drawings. However, the embodiments described below are examples of a light emitting element and a method for manufacturing the same, which embody the technical idea of the present utility model, and the light emitting device and the method for manufacturing the same of the present utility model are not particularly limited to the following. Further, in order to facilitate understanding of the scope of the claims, the numbers corresponding to the elements shown in the examples are given to the elements shown in the columns of "claims" and "summary of the utility model". The elements shown in the claims are not necessarily to be construed as elements of an embodiment. In particular, the dimensions, materials, shapes, relative arrangements, and the like of the constituent members described in the embodiments are not intended to limit the scope of the present utility model to those described herein unless specifically stated, but are merely illustrative examples.

However, the dimensions, positional relationships, and the like of the members shown in the drawings may be exaggerated for clarity. In the following description, the same names and symbols denote the same or similar members, and detailed description thereof is omitted. Further, each element constituting the present utility model may be a plurality of elements formed by the same member, and one member may also serve as a plurality of elements, or conversely, the functions of one member may be shared by a plurality of members. The contents described in some of the examples and embodiments may be applied to other examples and embodiments. In the present specification, "upper" is used not only in the case of being in contact with the upper surface but also in the case of being formed above in a spaced-apart manner, and also in the meaning of including a layer and a layer having an intervening layer therebetween.

While certain presently useful inventive embodiments have been discussed in the foregoing disclosure, by way of example, it is to be understood that such details are merely illustrative and that the appended claims are not limited to the disclosed embodiments, but, on the contrary, are intended to cover all modifications and equivalent arrangements included within the spirit and scope of the embodiments of the utility model. For example, while the system components described above may be implemented by hardware devices, they may also be implemented solely by software solutions, such as installing the described system on an existing server or mobile device.

Similarly, it should be noted that in order to simplify the description of the present disclosure and thereby aid in understanding one or more inventive embodiments, various features are sometimes grouped together in a single embodiment, figure, or description thereof. This method of disclosure does not imply that the subject utility model requires more features than are set forth in the claims. Indeed, less than all of the features of a single embodiment disclosed above.

While the utility model has been described with reference to the specific embodiments presently, it will be appreciated by those skilled in the art that the foregoing embodiments are merely illustrative of the utility model, and various equivalent changes and substitutions may be made without departing from the spirit of the utility model, and therefore, all changes and modifications to the embodiments are intended to be within the scope of the appended claims.

Claims (10)

1. A dual FPGA communication system, comprising:

The first FPGA module comprises a first phase-locked loop, a first data processing unit and a first communication interface unit which are sequentially connected;

The second FPGA module comprises a second phase-locked loop, a second data processing unit and a second communication interface unit, wherein the second communication interface unit is connected with the first communication interface unit, the second phase-locked loop is connected with the second communication interface unit, and the second data processing unit is respectively connected with the second communication interface unit and the second phase-locked loop;

The first communication interface unit and the second communication interface unit respectively comprise a TX-data differential interface, a TX-clock differential interface, an RX-data differential interface and an RX-clock differential interface, wherein the TX-data differential interface of the first communication interface unit is connected with the RX-data differential interface of the second communication interface unit, and the TX-clock differential interface of the first communication interface unit is connected with the RX-clock differential interface of the second communication interface unit.

2. The communication system of claim 1, wherein the first data processing unit and the second data processing unit each comprise ODDR units and IDDR units.

3. The communication system of claim 2, wherein the first phase-locked loop is configured to receive a first clock signal, and perform frequency conversion on the first clock signal to obtain a second clock signal, where the frequency of the second clock signal is N times that of the first clock signal, and N is a positive integer greater than 1;

The first data processing unit is used for sending one bit data on each rising edge and each falling edge of the second clock signal through a ODDR unit of the first data processing unit.

4. A communication system as claimed in claim 3, wherein the first data processing unit is further adapted to: the first clock signal is subjected to phase transformation to obtain a third clock signal, the third clock signal has the same frequency as the first clock signal but a 90-degree phase difference, and first bit data are sent on the rising edge of the third clock signal; and transmitting the third clock signal.

5. The communication system of claim 4, wherein the second phase-locked loop is configured to receive the third clock signal, and frequency convert the third clock signal to obtain a fourth clock signal, the fourth clock signal having a frequency N times the third clock signal, the N being a positive integer greater than 1;

The second data processing unit is used for respectively acquiring one bit data on each rising edge and each falling edge of the fourth clock signal through the IDDR unit of the second data processing unit.

6. The communication system of claim 4, wherein the second data processing unit is further configured to obtain the first bit data at a rising edge of the third clock signal.

7. The communication system of claim 1, wherein the first FPGA module further comprises a first buffer unit coupled to the first data processing unit, and the second FPGA module further comprises a second buffer unit coupled to the second data processing unit.

8. A communication system as claimed in claim 3, further comprising: and the clock module is connected with the first phase-locked loop and is used for providing the first clock signal for the first phase-locked loop.

9. A communication system according to claim 3, wherein N is equal to 4.

10. The communication system according to any of claims 1 to 8, wherein the first data processing unit and the second data processing unit transmit data based on an LVDS communication protocol.