KR20200138275A - MIPI D-PHY sending circuit and equipment - Google Patents

Abstract

The present invention provides a MIPI D-PHY sending circuit and device, the MIPI D-PHY sending circuit comprising: an FPGA reconfigurable sending clock circuit; An FPGA reconfigurable DPHY_IO sending circuit connected to the FPGA reconfigurable sending clock circuit; A data packet recombination circuit; And an FPGA reconfigurable DPHY_IO transmission circuit connected to the data packet recombination circuit, and a matching design is performed for the MIPI D-PHY transmission circuit and the MIPI protocol layer through the FPGA reconfigurable MIPI D-PHY transmission circuit, and the MIPI D -By adjusting the driving capability of the PHY sending circuit, it can effectively reduce the circuit area and improve the resource utilization rate of the circuit, improve the sending performance and improve the compatibility, and satisfy the various application requirements of CSI-2 and DSI. You can also make it.

Description

MIPI D-PHY sending circuit and equipment

The present invention claims the priority of the Chinese application with the application number CN201910458822.7 filed on May 29, 2019, and all the contents thereof are incorporated herein by reference.

The present invention relates to the field of high-speed serial bus technology, and more particularly to MIPI D-PHY transmission circuits and devices.

Mobile Industry Processor Interface (MIPI) DPHY is a standard general purpose interface for the mobile industry processor interface. As the application of the MIPI D-PHY interface in the mobile industry becomes more and more widespread, the demand for a variety of MIPI D-PHY supported modes is also increasing. However, since all existing MIPI D-PHY circuits use ASIC-only circuits, they cannot be flexibly configured for the application mode, and dedicated MIPI D-PHY circuits cannot satisfy different application requirements. In addition, since the general-purpose MIPI D-PHY circuit and the protocol (CSI-2/DSI) circuit are each independent, both the MIPI D-PHY and MIPI protocol layers have to process the protocol for the circuit. Exists.

The technical problem to be solved by the present invention is that the conventional MIPI D-PHY circuit cannot satisfy different application requirements, and the general-purpose MIPI D-PHY circuit and the protocol (CSI-2 protocol/DSI protocol) circuit are each independent. However, since both the MIPI D-PHY and the MIPI protocol layer have to process the protocol for the circuit, there is a problem of wasting resources due to overlapping some functions.

In order to solve the above technical problem, the present invention provides a MIPI D-PHY transmission circuit, the MIPI D-PHY transmission circuit is an FPGA reconfigurable transmission clock circuit; And an FPGA reconfigurable DPHY_IO sending circuit connected to the FPGA reconfigurable sending clock circuit.

Selectably, the MIPI D-PHY sending circuit comprises: a data packet recombination circuit; And an FPGA reconfigurable DPHY_IO transmission circuit connected to the data packet recombination circuit, wherein the data packet recombination circuit repackages the data to be transmitted according to a protocol and then sends it to the FPGA reconfigurable DPHY_IO transmission circuit.

Optionally, the MIPI D-PHY sending circuit performs data transmission based on the CSI-2 protocol or the DSI protocol.

Optionally, the FPGA reconfigurable sending clock circuit comprises a PLL module, the FPGA reconfigurable DPHY_IO sending circuit comprises a DPHY_IO clock circuit, and the PLL module comprises a clock link clock signal output circuit and a data link clock signal output circuit. The DPHY_IO clock circuit each includes a clock link clock channel connected to the clock link clock signal output circuit, and a data link clock channel connected to the data link clock signal output circuit.

Selectably, the clock link clock channel includes a first frequency division circuit CLKDIV, a first parallel serial conversion module OSERDES, and a first input output buffer IOB, and the first frequency division circuit CLKDIV is sent by the first PLL module. After receiving one clock channel data, performing frequency division on the clock channel data, obtaining first parallel data, transmitting the first parallel data in parallel to the first parallel serial conversion module OSERDES, and performing the first parallel serial The conversion module OSERDES converts the first parallel data into first serial data and transmits it to the first input output buffer IOB.

Selectably, the data link clock channel includes a second frequency division circuit CLKDIV, a second parallel serial conversion module OSERDES, and a second input output buffer IOB, and the second frequency division circuit CLKDIV is the data sent by the PLL module. Receiving channel data, performing frequency division on the data channel data, obtaining second parallel data, transmitting the second parallel data in parallel to the second parallel serial conversion module OSERDES, and performing the second parallel serial conversion The module OSERDES converts the second parallel data into second serial data and transmits it to the second input output buffer IOB.

Optionally, the FPGA reconfigurable DPHY_IO sending circuit includes up to 4 data output channels.

Selectably, the data output channel includes the DPHY_IO sending circuit and an external analog circuit, and the DPHY_IO sending circuit is connected to the external analog circuit.

Optionally, the DPHY_IO sending circuit comprises an IOL module and a sending circuit connected to the IOL module, the IOL module receiving low-speed data or high-speed data; The sending circuit outputs low-speed data or high-speed data to an external port; The external analog circuit is connected to the external port.

Optionally, the number of IOL modules is 4, and the 4 IOL modules include two first IOL modules for transmitting low-speed data and two second IOL modules for transmitting high-speed data.

Selectably, the MIPI D-PHY sending circuit further includes a first resistor, the first IOL module is connected to the external port through the first resistor, and the resistance value of the first resistor is 330 ohm. .

Selectably, the MIPI D-PHY sending circuit further includes a second resistor, the second IOL module is connected to the external port through the second resistor, and the resistance value of the second resistor is 50 ohms. .

Optionally, the level standard for the high-speed data is LVDS.

Optionally, the high-speed data is a current of 2-4mA.

Optionally, the level standard for the low-speed data is LVCMOS12.

Optionally, the high-speed data is a current of 2-12mA.

Selectably, the clock link clock channel is a unidirectional channel and the data link clock channel is a unidirectional channel or a bidirectional channel.

Selectably, the MIPI D-PHY sending circuit is for generating a clock of a clock path and a clock of a data path, and the clock of the clock path and the clock of the data path are different by a preset phase.

In addition, the present invention further provides a device including the MIPI D-PHY transmission circuit described above.

Optionally, the device includes a smartphone, a tablet PC, a notebook, a PDA and a vehicle-mounted computer.

MIPI D-PHYMIPI D-PHYMIPI D-PHY

1 is a schematic structural diagram of a MIPI D-PHY transmission circuit provided by Embodiment 1 of the present invention.
Fig. 2 is a schematic diagram of the structure of a clock circuit logical layer circuit of the MIPI D-PHY transmission circuit provided by Embodiment 1 of the present invention.
3 is a schematic structural diagram of a DPHY_IO transmission circuit of the MIPI D-PHY transmission circuit provided by Embodiment 1 of the present invention.
Figure 4 is a schematic diagram of the work flow of the MIPI D-PHY sending circuit provided by Embodiment 2 of the present invention.

Examples of the present invention will be described in detail with reference to the drawings through specific embodiments below so that the objects, means and advantages of the present invention may become clearer. It should be understood that the specific embodiments described herein are for interpreting the present invention and not for limiting it.

Example 1

Since the existing dedicated MIPI D-PHY circuit cannot satisfy different application requirements, and the general-purpose MIPI D-PHY circuit and the protocol (CSI-2/DSI) circuit are independent, both the MIPI D-PHY and MIPI protocol layers are In order to solve the problem of resource waste due to overlapping of some functions, since protocol processing must be performed for the circuit, a MIPI D-PHY transmission circuit is provided.

It should be understood that the present invention realizes the reconfiguration of the MIPI D-PHY sending circuit using an FPGA (Field-Programmable Gate Array), where MIPI is a mobile industrial processor interface whose official name is Mobile Here, MIPI D-PHY is one physical layer of MIPI, and there are two types of protocol layer, CSI and DSI, where CSI is mainly used for image access, for example an image sensor.

Referring to Figure 1, Figure 1 is a schematic diagram of the structure of the MIPI D-PHY transmission circuit provided by an embodiment of the present invention. The MIPI D-PHY sending circuit 100 includes an FPGA reconfigurable sending clock circuit 110, an FPGA reconfigurable DPHY_IO sending circuit 120 connected to the FPGA reconfigurable sending clock circuit 110, and a data packet recombination circuit (prg_tx_hs_pkg). (130) And the FPGA reconfigurable DPHY_IO sending circuit 120 connected to the data packet recombination circuit 130, including the FPGA reconfigurable DPHY_IO sending circuit 120 connected to the FPGA reconfigurable sending clock circuit 110 below. ) Is abbreviated as the DPHY_IO clock circuit 121, and the FPGA reconfigurable DPHY_IO sending circuit 120 connected to the data packet recombination circuit 130 is abbreviated as the DPHY_IO sending circuit 122.

In this embodiment, the FPGA reconfigurable dispatch clock circuit 110 is a PLL module, and the PLL module can generate a required clock according to a user configuration, and it should be explained that there are two types of generated clocks, one of which is a clock. The clock of the passage and the other is the clock of the data passage, and the two clocks maintain a constant phase relationship to satisfy the construction and maintenance time required for the digital circuit. The DPHY_IO clock circuit 121 receives the clock of the clock channel and the clock of the data channel transmitted by the PLL module through hs_clk and hs_clk_i, respectively, where hs_cl is the driving clock of the clock channel, and hs_clk_i is the driving clock of the data channel. Output by the clock channel. The data packet recombination circuit (prg_tx_hs_pkg) 130 repackages the received user data according to the protocol request, sends it to the DPHY_IO sending circuit 122, and is output through the data channel.

It should be explained that the data packet recombination circuit 130 processes the received user data, converts it into a format capable of receiving processing by the DPHY_IO transmission circuit 122 according to a protocol request, and repackages and sends it.

In this embodiment, the MIPI D-PHY sending circuit 100 and the CSI-2 protocol / DSI protocol are matched, in other words, the MIPI D-PHY sending circuit 100 is based on the CSI-2 protocol or the DSI protocol. Thus, data transmission can proceed. Specifically, it is up to the user to decide which protocol to select, and this method can effectively reduce the circuit area and improve the resource utilization rate of the circuit.

In this embodiment, the MIPI D-PHY sending circuit uses a pair of source synchronization clocks and 1 to 4 pairs of clock data lines to transmit data, and it should be explained that the clock channel is unidirectional and the data channel is unidirectional. Or both.

In this embodiment, refer to Fig. 2 for transmission of the clock signal. The PLL module includes a clock signal input terminal (clk_in) 111, a first clock signal output terminal (clkout0) 112, a second clock signal output terminal (clkout1) 113, a clock link clock signal output circuit 114, and a data link clock. Including a signal output circuit 115, the DPHY_IO clock circuit is a clock link clock channel 1211 connected to the clock link clock signal output circuit 114, respectively, and a data link connected to the data link clock signal output circuit 115 It includes a clock channel 1212, the clock link clock channel includes a frequency division circuit (CLKDIV) 1211a, a parallel serial conversion module (OSERDES) 1211b, an input output buffer (IOB) 1211c, and a data link The clock channel includes a frequency division circuit (CLKDIV) 1212a, a parallel serial conversion module (OSERDES) 1212b, and an input/output buffer (IOB) 1212c.

Specifically, the clock signal input terminal (clk_in) 111 of the PLL module receives a clock signal configured by a user, and the clock signal includes a clock signal of a clock path and a clock signal of a data path, and the clock signal of the clock path is The first clock signal output terminal (clkout0) 112 enters the clock link clock channel 1211 through the clock link clock signal output circuit 114, and the clock signal of the data path is transmitted to the second clock signal output terminal (clkout1) ( 113) enters the data link clock channel 1212 through the data link clock signal output circuit 115; The clock link clock channel 1211 receives a clock path clock signal, performs frequency division by a frequency division circuit (CLKDIV) 1211a, outputs two clock path clock signals, and outputs a parallel serial conversion module (OSERDES) ( 1211b) converts the signal to a serial signal and transmits it to the input output buffer (IOB) 1211c, outputs it to the external port 200 through the input output buffer (IOB) 1211c, and the output clock path clock signal The phase of is reversed; The data link clock channel 1212 receives the clock signal of the data path, performs frequency division by the frequency division circuit (CLKDIV) 1212a, and outputs two data path clock signals, and outputs two data path clock signals, and a parallel serial conversion module (OSERDES) ) (1212b) converts the signal into a serial signal and transmits it to the input output buffer (IOB) 1212c, outputs it to the external port 200 through the input output buffer (IOB) 1212c, and the output data path The phase of the clock signal is reversed.

It should be explained that the transmission of the data path clock signal corresponds to one data channel, and when the MIPI D-PHY transmission circuit 100 is operated, up to 4 channels can simultaneously transmit data, and each data channel is All correspond to one parallel-to-serial conversion module (OSERDES) 1212b and an input-output buffer (IOB) 1212c, and each of the parallel-to-serial conversion modules (OSERDES) 1212b is a frequency division circuit (CLKDIV) 1212a. The two data path clock signals output after frequency division are received by.

In this embodiment, both the data channel and the clock channel of the MIPI D-PHY transmission circuit can be reconfigured by the FPGA, and the data channel signal and the clock channel signal can be phase adjusted.

In this embodiment, please refer to FIG. 3 for a detailed operation flow of the DPHY_IO sending circuit.

The MIPI D-PHY transmission circuit includes two transmission modes, low-speed mode (LP, Lower Power) and high-speed mode (HS, high speed), and the two modes work in common to transmit data and commands in the MIPI interface protocol layer. To realize.

3, the DPHY_IO sending circuit 122 includes an IOL module 1221 and a sending circuit 1222. In this embodiment, the DPHY_IO sending circuit includes four IOL modules 1221, and the four IOL modules 1221 are two first IOL modules 1221a for transmitting low-speed data, and for transmitting high-speed data. It includes two second IOL modules 1221b. After receiving the low-speed data, the low-speed data is output to the external port 200 from the IOB (I/O buffer, not shown) of IO0 (p-stage) and IO3 (n-stage), and LVCMOS12 is used as a level standard. After sending LP11->LP01-> LP00, set TS of high-speed channel to 0, open high-speed channel enabling, and when sending LP11 again, set TS of high-speed channel to 1 and high-speed channel Close While opening the high-speed channel, the low-speed channel must send LP00. It should be explained that LP01 indicates that the P stage is 0 and the n stage is 1, and others are similar. After receiving the high-speed data, the two second IOL modules 1221b combine with each other to process the data, and the high-speed signal uses the differential level LVDS (Low Voltage Differential Signaling) standard and enters the IOL module. Thus, parallel serial conversion (OSERDES) is realized. For example, 8-bit parallel data is converted into serial data, output to the external port 200 through IOBs (I/O buffers, not shown) of IO1 and IO2, and IOB (I/O buffers, not shown) ) Must be controlled, TS is 0, closes the 3-state enabling, and the signal can be output from the IOB to the external port 200, and when TS is 1, the 3-state enabling is opened and the external port ( 200) is enabled in high resistance state. IO0, IO1, IO2 and IO3 are connected to the external analog circuit 300 through the external port 200, and a first resistor 140 is connected in series to the high-speed channels IO1 and IO2, where the first resistor is a 330 ohm resistor. The second resistor 150 is serially connected to the low-speed channels IO0 and IO4, and the second resistor may be a 50 ohm resistor, realizing electrical characteristics that meet MIPI normative requirements, and the electrical characteristics of the common mode voltage. (DC characteristic) and differential amplitude (AC characteristic) are included. Here, tx_byte_i_clk in FIG. 2 is a byte clock of a clock channel, and it should be understood that another related name in FIG. 2 may be a corresponding byte clock.

In this embodiment, the driving capability of the DPHY_IO sending circuit can be adjusted through the IOB, the LVDS level standard is used in the high-speed mode, and 2mA to 4mA can be selected; In low speed mode, it uses the LVCMOS12 level standard, you can choose from 2 to 12mA, it should be explained, it uses different drive currents to adapt to different application situations.

An embodiment of the present invention provides a MIPI D-PHY sending circuit 100, which is an FPGA reconfigurable sending clock circuit 110, and an FPGA reconfigurable DPHY_IO sending circuit connected to the FPGA reconfigurable sending clock circuit 110. 120, a data packet recombination circuit 130, and an FPGA reconfigurable DPHY_IO transmission circuit 120 connected to the data packet recombination circuit 130, and the MIPI D-PHY transmission circuit 110 and the MIPI protocol layer. The matching design is carried out to effectively reduce the circuit area and improve the resource utilization rate of the circuit, improve the transmission performance by adjusting the phase of the MIPI D-PHY data channel and the clock channel, and improve the transmission performance of the MIPI D-PHY transmission circuit. The drive capability can be adjusted to improve compatibility, and the MIPI D-PHY transmission circuit can satisfy the needs of various applications of CSI-2 and DSI.

Example 2

On the basis of the above embodiment, this embodiment provides a flow chart for sending a 4-channel protocol of the MIPI D-PHY sending circuit, and refer to Fig. 4 in detail.

When the system is initialized, enter the standby IDLE state.

S401: Detects whether the initialization is complete in IDLE state, and when it is completed, increases init_done and enters the ST_LP_STOP state, and the long and short initialization time is set by the user. Here, ST_LP_STOP is a low-speed idle state.

It should be explained that the detection of whether the initialization is complete can be determined according to whether or not the LP11 is sent, and when the LP11 is sent, it is explained that the initialization has already been completed, and otherwise, the initialization is continued. In this embodiment, the long and short time is set by the user, and the clock cycle is set by the PLL module of the FPGA reconfigurable sending clock circuit, and after setting the clock cycle well, the user configures the number of clock cycles as needed. Should be. The long and short of this time is determined by the number of clock cycles.

S402: Detecting the valid_hs signal in the ST_LP_STOP state, and requesting a signal for high-speed data means that high-speed data will be sent soon, enters the ST_HS_RQST state, otherwise it stops and waits.

S403: LP01 is sent in ST_HS_RQST state, the user sets the long and short time, and enters ST_HS_PRPR state when completed, otherwise stops and waits. Here, ST_HS_RQST is a fast request entry state.

S404: Send LP00 in ST_HS_PRPR state, and set the long and short time by the user, and enter ST_HS_GO state upon completion, otherwise stop and wait. Here, ST_HS_PRPR is the high-speed ready entry state.

S405: In the ST_HS_GO state, high-speed 0 is sent, the long and short time is set by the user, and upon completion, it enters the ST_HS_SYNC state, otherwise it stops and waits. Here, ST_HS_GO is the high-speed conversion entry state.

S406: Sends MIPI D-PHY synchronization head B8 in the ST_HS_SYNC state, and automatically enters the ST_HS_DATA state. Here, ST_HS_SYNC is a high-speed data synchronization state.

It should be explained that the MIPI D-PHY synchronization head B8 is for positioning and synchronizing each data in the data transmission process, in other words, it is possible to transmit data after the receiving end receives the alignment data.

S407: In the ST_HS_DATA state, it detects whether valid_hs is “high”. If it is “high”, it stops at this state and sends high-speed data of the user. If it is “low”, it enters the ST_HS_TRAIL state.

It should be understood that the high-speed data sent is valid data. Here, ST_HS_DATA is the generated high-speed data state.

S408: In the ST_HS_TRAIL state, a high-speed tail signal is sent, the long and short time is set by the user, and upon completion, it returns to the IDLE state, otherwise it stops in this state. Here, ST_HS_TRAIL is a high-speed data packet tail transmission state.

It should be explained that the long and short time of this embodiment is set by the user, and the clock period is set by the PLL module of the FPGA reconfigurable sending clock circuit, and after setting the clock period well, the user can You have to configure the number. The long and short of this time is determined by the number of clock cycles.

In this embodiment, the length of the high-speed tail signal can be determined according to the long and short time.

An embodiment of the present invention provides a specific realization process of the MIPI D-PHY transmission circuit, and performs matching design for the MIPI D-PHY transmission circuit and the MIPI protocol layer through the FPGA reconfigurable MIPI D-PHY transmission circuit, It effectively reduces the circuit area and improves the resource utilization rate of the circuit. By adjusting the phase of the MIPI D-PHY data channel and the clock channel, the transmission performance can be improved, and the drive capability of the MIPI D-PHY transmission circuit can be adjusted to improve compatibility. The MIPI D-PHY transmission circuit is CSI -2 and DSI can satisfy various application needs.

Example 3

The present embodiment provides a device, and the device may be a mobile smart device having a mirroring function, such as a smart phone, a tablet PC, a notebook, and a personal digital assistant (PDA), but is not limited thereto. Of course, it may be a fixed smart device such as a PC having a mirroring function or a vehicle-mounted computer, but is not limited thereto. The device includes the MIPI D-PHY transmission circuit according to the above-described embodiment to realize the corresponding function and will not be described herein again.

The above description has been described in detail with respect to the embodiments of the present invention in connection with the specific embodiments, but the specific implementation of the present invention is not limited by this description. Those skilled in the art to which the present invention pertains may proceed with some simple reasoning or transformation without departing from the concept of the present invention, and all such reasoning or transformation should be regarded as belonging to the protection scope of the present invention.

Claims (20)

In the MIPI D-PHY sending circuit,
FPGA reconfigurable send clock circuit; And
And an FPGA reconfigurable DPHY_IO sending circuit connected to the FPGA reconfigurable sending clock circuit.
The method of claim 1,
Data packet recombination circuit; And
Further comprising an FPGA reconfigurable DPHY_IO sending circuit connected to the data packet recombination circuit,
The data packet recombination circuit repackages the data to be transmitted according to a protocol and then transmits the repackaged data to the FPGA reconfigurable DPHY_IO transmission circuit.
The method of claim 1,
The MIPI D-PHY sending circuit is a MIPI D-PHY sending circuit, characterized in that for performing data transmission based on a CSI-2 protocol or a DSI protocol.
The method according to any one of claims 1 to 3,
The FPGA reconfigurable transmission clock circuit includes a PLL module, the FPGA reconfigurable DPHY_IO transmission circuit includes a DPHY_IO clock circuit, the PLL module includes a clock link clock signal output circuit, a data link clock signal output circuit, and the DPHY_IO clock circuits each comprising a clock link clock channel connected to the clock link clock signal output circuit, and a data link clock channel connected to the data link clock signal output circuit.
The method of claim 4,
The clock link clock channel includes a first frequency division circuit CLKDIV, a first parallel serial conversion module OSERDES, and a first input output buffer IOB,
The first frequency division circuit CLKDIV receives the clock channel data sent by the first PLL module, performs frequency division on the clock channel data, and then obtains first parallel data, and converts the first parallel data to a first MIPI D-PHY, characterized in that parallel transmission to the parallel serial conversion module OSERDES, wherein the first parallel serial conversion module OSERDES converts the first parallel data into first serial data and transmits it to the first input output buffer IOB. Sending circuit.
The method of claim 4,
The data link clock channel includes a second frequency division circuit CLKDIV, a second parallel serial conversion module OSERDES, and a second input output buffer IOB,
The second frequency division circuit CLKDIV receives the data channel data sent by the PLL module, performs frequency division on the data channel data, and then obtains second parallel data, and transfers the second parallel data to the second parallel data. Sending MIPI D-PHY, characterized in that it transmits in parallel to the serial conversion module OSERDES, and the second parallel-serial conversion module OSERDES converts the second parallel data into second serial data and transmits it to the second input output buffer IOB. Circuit.
The method of claim 1,
The FPGA reconfigurable DPHY_IO sending circuit is a MIPI D-PHY sending circuit, characterized in that it includes a maximum of 4 data output channels.
The method of claim 7,
Wherein the data output channel includes the DPHY_IO sending circuit and an external analog circuit, and the DPHY_IO sending circuit is connected to the external analog circuit.
The method of claim 8,
The DPHY_IO sending circuit includes an IOL module and a sending circuit connected to the IOL module, and the IOL module receives low-speed data or high-speed data; The sending circuit outputs low-speed data or high-speed data to an external port; The external analog circuit is a MIPI D-PHY transmission circuit, characterized in that the connection is connected to the external port.
The method of claim 9,
The number of IOL modules is 4, and the 4 IOL modules include two first IOL modules for transmitting low-speed data and two second IOL modules for transmitting high-speed data. Sending circuit.
The method of claim 10,
The MIPI D-PHY sending circuit further includes a first resistor, the first IOL module is connected to the external port through the first resistor, and the resistance value of the first resistor is 330 ohms. D-PHY sending circuit.
The method of claim 10,
The MIPI D-PHY sending circuit further includes a second resistor, the second IOL module is connected to the external port through the second resistor, and the resistance value of the second resistor is 50 ohms. D-PHY sending circuit.
The method of claim 9,
The MIPI D-PHY transmission circuit, characterized in that the level standard of the high-speed data is LVDS.
The method of claim 13,
The high-speed data is a MIPI D-PHY transmission circuit, characterized in that the current of 2 ~ 4mA.
The method of claim 9,
The MIPI D-PHY transmission circuit, characterized in that the level standard of the low-speed data is LVCMOS12.
The method of claim 15,
The high-speed data is a MIPI D-PHY transmission circuit, characterized in that the current of 2 ~ 12mA.
The method of claim 4,
Wherein the clock link clock channel is a unidirectional channel, and the data link clock channel is a unidirectional channel or a bidirectional channel.
The method according to any one of claims 1 to 17,
The MIPI D-PHY sending circuit is for generating a clock of a clock path and a clock of a data path, and the clock of the clock path and the clock of the data path are different by a preset phase. Circuit.
A device comprising the MIPI D-PHY sending circuit according to any one of claims 1 to 18.
The method of claim 19,
The device, characterized in that it comprises a smartphone, a tablet PC, a notebook, a PDA and a vehicle-mounted computer.

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